Application Note: AN-146 Guidelines for Effective LITELINK™ Designs

Application Note: AN-146Guidelines for Effective LITELINK DesignsAN-146: December 22, 2012 www.ixysic.com 1

Application Note: AN-1461. IntroductionTwo of the important functions provided by LITELINKto the host systems are high-voltage isolation betweenthe host system and the public switched telephonenetwork (PSTN), and coupling signals to and from thePSTN.these must also meet all the requirements for thesnoop capacitors listed below.Figure 1. Isolation BarrierIsolationBarrierPrinted-circuit board layout for LITELINK designsrequires attention to detail with regard to thesefunctions. This application note describes designtechniques and practices for compliance andperformance that should be considered whendesigning with LITELINK. Examples in this applicationnote are based on a dial-up modem host system, butare applicable to any LITELINK implementation.Host SideCircuitryLITELINKTelephone LineSide CircuitryTelephone JackNote that some of these guidelines are based onsafety requirements for Information TechnologyEquipment. Designs that must meet other safetyrequirements may require other considerations.Snoop CapacitorsSnoop Resistors2.5 mm MinimumIsolation Spacing2. Circuit Isolation ConsiderationsTIA/EIA/IS-968 (formerly FCC part 68) compliancerequires testing the integrity of the isolation barrier andthe surge immunity of the system. These tests include:• Leakage test - 1000 V rms applied from tip and ringto ground• Surge test - 1500 V peak applied from tip and ring togroundLITELINK provides a minimum 1500 V RMS isolationbarrier between host-side circuitry (connected to pins1 through 16) and telephone-line side circuitry(connected to pins 17-32). Passive discretecomponents used with LITELINK need to meetelectrical isolation requirements as well.The snoop circuit capacitors in the typical applicationcircuit are examples of passive discrete componentsused in conjunction with LITELINK that must meetisolation barrier requirements. Other discretecomponents may also have to meet isolationrequirements. If, for example, the circuit usescapacitors from tip and ring to Earth to suppress EMI,2.1 Snoop Capacitor and Circuit Spacing Characteristicsfor IsolationThe snoop components in Figure 1 are used inLITELINK applications for ring detection and caller IDsignal coupling. Snoop components bridge theisolation gap. To meet the requirement for basicinsulation, the capacitors must comply with therequirements of IEC384-14: 1993, subclass Y2 or Y4.In areas where supplementary insulation is required,the capacitors must either meet the requirements ofIEC384-14: 1993, subclass Y1 for a single capacitorfor each circuit, or, when two capacitors are used inseries for each circuit, both capacitors must complywith IEC384-14: 1993, subclass Y2 or Y4. Further, indesigns using two capacitors in series in each snoopcircuit, they must be rated for the total working voltageacross the pair and have the same nominalcapacitance value.Isolation spacing must include both printed-circuitboard traces and component leads. Figure 1 depictssurface-mount technology (SMT) capacitors withwrap-around leads. All component leads and tracesAN-146 www.ixysic.com 2

Application Note: AN-146must maintain a minimum of 2.5 mm (0.1 inch)creepage (where the printed-circuit board MaterialGroup is IIIa/b and the pollution degree is 2) betweenthe telephone-line side and ground or any componentor printed-circuit board trace on the host equipmentside of the circuit.Maintaining this spacing also helps to ensurecompliance with the requirements of IEC/EN60950and UL 1950.The series resistors in the snoop path may beexposed to high-voltage potentials during transients,so multiple components or resistors with largerterminal spacing may be needed.2.2 Tip and Ring Spacing ConsiderationsSimilar to isolation barrier requirements, yourLITELINK implementation must also account forhigh-voltage potentials across the tip and ringtelephone line leads.Figure 2. LITELINK Line Side Application CircuitFragmentTo LITELINKSnoop InputC7220pF2000VC8220pF2000VR6 3.6M1/10W 1%R7 3.6M1/10W 1%C15.01500VNote the surge protection block across the tip and ringleads in Figure 2. This device is normally specified toclamp surge voltages in excess of the maximum ringvoltage between tip and ring (metallic surgeprotection).Consider an FCC B ring signal. The signal is specifiedat 150 V RMS maximum, which is 212 Volts peak. Add100 Volts for loop-extended battery voltage (48 Voltsnominal), and the protection device must allow at least312 Volts before clamping.The voltage across all components either directly orindirectly across the tip and ring leads can therefor+--BRTo LITELINKC10.01500VDB1SIZB60600V_60ASP1P3100SB12TIPRINGNOTE:Reference designationsfrom LITELINKapplication circuitsreach well over 300 Volts, up to the clamp rating of thesurge protection block. All of the components shown inFigure 2 can have the clamping voltage across themduring ringing or a differential surge.These components be rated accordingly, and theprinted-circuit board design must account for thesevoltages. Maintain at least 1.4 mm (0.055 inch)spacing between all component terminals andadjacent printed-circuit board traces (if the traces areon the same plane) on the telephone line side of thedesign.Remember also that all telephone-line-sideprinted-circuit board traces must maintain at least 2.5mm (0.1 inch) creepage from all host-equipment-sidecircuits.2.3 LITELINK Circuit Isolation Guidelines• To prevent common-mode noise problems, do notuse ground or power printed-circuit board planes inthe isolation area. A BR- plane in the isolation areacould be used.• To prevent printed-circuit board trace fusing undersurge conditions, maintain a minimum 0.6 mm(0.025 inch) printed-circuit board trace widthbetween the telephone line jack and the surgeprotection device.• Observe circuit creepage and clearancerequirements per relevant standards, such asUL1950/60950 and IEC/EN60950, and with regardto the insulation grade, working voltage, materials,and pollution degrees involved. For example, if basicinsulation is required, and the insulation materialgroup is IIIa/b, and the working voltage does notexceed 100 V RMS or dc, and the pollution degree is2, then 1.4 mm (0.055 inch) creepage may berequired between printed-circuit board traces on thesame plane.• For printed-circuit boards of Material Group IIIa/band pollution degree 2, maintain minimum creepageof 2.5 mm (0.1 inch) and clearance of 2 mm (0.079inch) between all circuitry on the high-voltagetelephone line side of the printed-circuit board andthe low-voltage host equipment side, includinggrounds. Adjust this spacing for printed-circuit boardtolerances.3. Electro-Magnetic Interference (EMI)ConsiderationsThe telephone line connection in your design canbecome a source of trouble in meeting EMIAN-146 www.ixysic.com 3

Application Note: AN-146requirements such as FCC part 15. Common originsof EMI in designs that use LITELINK include:• High-speed clocks• Poor power supply decoupling• Poor grounding3.1 High-Speed ClocksYour design may include one or more high-speedclock generation circuits, crystals or oscillators.Sharp-edged clock signals can be quite spectrally richin harmonic energy, making emissions compliance achallenge.One common way to reduce clock emissions involvesadding a small resistance in series with the oscillatoroutput. The resistance, along with parasiticprinted-circuit board trace capacitance, can removeenough harmonic energy emission to supportcompliance.With this technique, care must be taken not to skewthe clock signal so much so as to create timingproblems in the system. Resistance values between10 and 47 Ohms may be enough to meet allrequirements. This technique can also be used withmicroprocessor address, data, and control lines.Some designs use enough drive for crystal oscillatorsto cause a significant spectral spike in emissions atthe fundamental frequency or one or more harmonics.In these cases, the addition of a small resistor inseries with the crystal may help reduce emissions.Consult the crystal manufacturer’s product literaturefor information on applicability of this technique to yourdesign and for suggested series resistor values. If youuse this technique, perform all the testing needed toensure that your oscillator starts and runs under alldesign temperature condition requirements.As a general design guide, keep clock and otherhigh-speed signal printed-circuit board traces as shortas possible.3.2 DecouplingDecoupling system power supplies from oscillator andother noise-generating circuits can help reduce bothconducted and radiated emissions.LITELINK application circuits include a network thatprovide acceptable power supply decoupling. Thisnetwork helps prevent coupling power supply noisethrough LITELINK to the telephone line at frequenciescommonly used with switch-mode power supplies.IXYS IC Division recommends using the inductor variantof the network described in the application circuitsif the resistor-based network provides insufficientdecoupling. A Pi network using ferrite beads andcapacitors can be a better decoupling solution forhigher problem frequencies.In either case, correct placement of the LITELINKpower supply decoupling network is vital for aneffective design. Place the network as close to theLITELINK VDD and GND pins (pins 1 and 7) aspossible.In general, keep all decoupling circuits as close aspossible to the IC being decoupled. Use good-qualitytantalum capacitors for bulk decoupling, usually with avalue of 10 µF or higher.There are several useful primers on power supplydecoupling on the World Wide Web, including:• IBM System Board Power Distribution Guidelinesfor PID9q-604eTM (Mach5)• Chrontel PCB Layout and Design Considerationsfor CH7011 TV Output Device• Altera board layout techniques3.3 GroundingFor best emission suppression in LITELINK designs,keep analog and digital grounds separate. Analog anddigital grounds should be tied together at one pointnear the power supply.To reduce ground trace impedance, use printed-circuitboard traces at least 1.3 mm (0.050 inch) wide. Groupanalog and digital circuitry in separate areas wherepossible.While ground or power printed-circuit board planesshould not be used in the isolated area, the use of aBR- plane in the isolation area is acceptable.AN-146 www.ixysic.com 4

Application Note: AN-1463.4 A LITELINK EMI FilterFigure 3. LITELINK EMI Filtermanagement. The FET designed and manufacturedby IXYS IC Division for use with LITELINK will requireheat sinking commensurate with your application. TheCPC5602C FET performs three circuit functions:• Low drop-out (LDO) linear regulator• Unity gain current buffer to the telephone line• SwitchhookIn a TBR-21 application, for example, the FET can beexpected to dissipate as much as 2 W of power.Figure 3 shows an EMI filter than can be applied toLITELINK circuits in conjunction with the standardapplication circuit in systems using Earth ground. Thiscircuit helps prevent coupling host device emissions tothe telephone line.The capacitors in this circuit must be rated for at least2 kV, since they are connected to both the telephoneline and Earth ground. See Circuit IsolationConsiderations on page 1 for more information. Earthground and host device ground are connected at asingle point in the system.IXYS IC Division suggests incorporating the FET heatsinkinto your printed-circuit board. Use 2 ounce coppermaterial under the FET heat tab on the other side ofthe printed-circuit board. Use multiple plated-throughholes to conduct heat away from the FET to the heatsink on the other side of the printed-circuit board. Formulti-layer printed-circuit board designs, you can alsouse inner metal layers between the front and backheat pads.See Figure 4 for heat sink dimension information.Figure 4. FET Heat Sink DimensionsChoose a ferrite with maximum impedance near thefrequency of interest. Often, it is difficult to predict thetroublesome frequency until you test the system.Failing frequencies are often not the fundamentalfrequency of the system’s clock oscillators, but an n thorder harmonic.Select a ferrite that can accommodate at least 120 mAof current, the maximum steady-state loop current thatcan be expected on telephone lines. Also, the ferritemust be able to withstand surges without fusing.Capacitor values will be in the range of severalhundred picofarads to one nanofarad. Actual capacitorvalues will require iterative testing after a goodfirst-order approximation.4. Heat ManagementLITELINKs have low power dissipation and do notneed any special design considerations for thermal5. Power QualityA clean LITELINK power supply is essential forhigh-quality connections with LITELINK. LITELINKapplication circuits include a power conditioningnetwork on VDD to assure clean power.AN-146 www.ixysic.com 5

Application Note: AN-146Figure 5. LITELINK Power Conditioning NetworkWith particularly noisy power supplies, substitute aninductor for R23. IXYS IC Division recommends a valueof 220 µH in this application, Toko 380HB-2215 or similar.6. Optimizing LITELINK Circuit PerformanceModem performance is, in part, limited bysignal-to-noise ratio (SNR). Careful circuit layout canmaximize SNR and provide greater modemthroughput.Figure 6. Modem Design Using LITELINKFETheatsinkSnoopcapacitorsC10.1A3.3 or 5 VR2310*FB1600 Ω200 mAIsolation barrierC1610ALITELINK VDD(pin 1)LITELINK mountedon opposite side of PCB,under snoop capacitorsIn addition to the techniques and guidelines describedpreviously in this application note, consider thefollowing points to optimize your modem design forSNR and performance:• Do not use Earth or power planes in the line-sidearea of your LITELINK implementation printed-circuitboard. BR- planes are acceptable.• Keep the TX +/- and RX +/- line printed-circuit boardtraces as short as possible. Treat them as differentialpairs, running parallel to each other and equidistant.• Observe isolation barrier requirements when placingsnoop circuit and other capacitors connected to tipand ring.• Treat the snoop circuit lines, including C SNOOP , andR SNOOP as a differential pair. Keep printed-circuitboard traces as short as possible, parallel andequidistant.• Keep analog circuitry referenced to analog powerand ground. Keep digital circuitry referenced todigital power and ground. Tie analog and digitalgrounds together at a common point near the powersupply.• Keep FET gate trace lengths as short as possible. Fortrace lengths longer than IXYS IC Division referencedesigns, you may want to increase the value of R GATto assure FET stability. Note: Higher R GAT valuesincrease FET sensitivity to transient events.• If the design uses a speaker, make sure that thespeaker return and audio amplifier return go toanalog ground. Also make sure that they have asshort as possible a run to power supply ground.• For audio amplifier (if used) power connections, usethe decoupling techniques described in Decouplingon page 4, with the addition of a bulk decouplingcapacitor as close as possible to the audio amplifierpower supply pin.• If your design uses an RS-232-type serial port, useferrite beads in series with the connections to helplimit emissions from the port. Consider adding apopulation option for small 0603-size capacitors fromsignal lines to analog ground to further diminishemissions, if needed.• If possible, group the microprocessor, digital signalprocessor, RAM, and ROM as close together aspossible to keep address and data line printed-circuitboard traces as short as possible.• Coder/decoders (CODECs) often have both analogand digital ground connections. Keep these groundsseparate. Make sure the LITELINK ground pinconnects to analog ground.• Use decoupling techniques appropriate for theproblem frequency using ferrites and capacitors toform Pi filters in appropriate places.AN-146 www.ixysic.com 6

Application Note: AN-1467. LITELINK Design Resources7.1 IXYS IC Division Design ResourcesThe IXYS IC Division web site has much informationuseful for designing with LITELINK, includingapplication notes and reference designs that alreadymeet all applicable regulatory requirements. LITELINKdata sheets also contains additional application anddesign information. See the following links:LITELINK datasheets and reference designsApplication note AN-117 Customize Caller-ID Gain andRing Detect Voltage ThresholdApplication note AN-141, Enhanced Pulse Dialing withLITELINKApplication note AN-143, Loop Reversal Detection withLITELINKApplication note AN-149, Increased LITELINK II TransmitPowerFor additional information please visit our website at: www.ixysic.comIXYS Integrated Circuits Division makes no representations or warranties with respect to the accuracy or completeness of the contents of this publicationand resert descriptions at any time without notice. Neither circuit patent licenses nor indemnityare expressed or implied. Except as set forth in IXYS Integrated Circuits Division’s Standard Terms and Conditions of Sale, IXYS Integrated Circuits Divisionassumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warrantyof merchantability or a particular purpose, or infringement of any intellectual property right.The products described in this document are not designed, intended, authorized or warranted for use as components in systems intended for surgicalimplant into the body, or in other applications intended to support or sustain life, or where malfunction of IXYS Integrated Circuits Division’s product mayresult in direct physical harm, injury, or death to a person or severe property or environmental damage. IXYS Integrated Circuits Division reserves the rightto discontinue or make changes to its products at any time without notice.Specification: AN-146-December-22-2012©Copyright 2012, IXYS Integrated Circuits DivisionAll rights reserved. Printed in USA.12/22/2012AN-146 www.ixysic.com 7