<strong>GPU</strong> SuperBlade® SBI-7127RG Suports 20 <strong>GPU</strong>s in 7U 4U 4 <strong>GPU</strong> SuperServer® SS7047GR Series Supports Up to 4 Double-Width <strong>GPU</strong>s in 4U ����������������������������������� HPC Systems Optimized for Scientifi c, Engineering and Computational Finance Applications �� Up to 20 <strong>GPU</strong>s in 7U �� Non-Blocking Native PCI-E 3.0 x16 Direct Connections to <strong>GPU</strong>s �� Centralized Remote Management Module (IPMI 2.0, KVM-over-IP, Remote Virtual Media) �� Redundant Platinum Level (94%+) High-Effi ciency Power Supplies �� New Dual Intel® Xeon® E5-2600 Processor Family 2U 4/6 <strong>GPU</strong> SuperServer® SS2027GR Series Supports Up to 6 Double-Width <strong>GPU</strong>s in 2U www.supermicro.com/X9 1U 3/4 <strong>GPU</strong> SuperServer® SS1027GR Series Supports Up to 4 Double-Width <strong>GPU</strong>s in 1U © Super Micro Computer, Inc. Specifi cations subject to change without notice. Intel®, the Intel® logo, Xeon®, and Xeon® Inside, are trademarks or registered trademarks of Intel Corporation in the US and other countries. All other brands and names are the property of their respective owners. SMCI-<strong>2012</strong>0221- 1
Speaker(s): James Lin (Assistant Professor, Shanghai Jiao Tong University) Topic(s): Computational Fluid Dynamics (Intermediate) TUESDAY, MAY 15, 10:00 (25 MINUTES) MARRIOTT BALLROOM 3 S0255 Telecom Systems Simulations Acceleration via CPU/<strong>GPU</strong> Co-Processing: Turbo Codes Case Study Learn how the struggle for acceleration of simulations of a Serially Concatenated turbo code (SCCC) led to the knowledge of new techniques applicable to a broad range of non-natively parallel physical layer telecommunication systems simulations. The overall architectural features of CUDA became inspiring for newer parallelization techniques involving algorithm engineering; the simulation acceleration attained for iterative SCCC Decoder represents an example of efficiency of leveraging on heterogeneous <strong>GPU</strong>-CPU coprocessing concepts. The registrants will deep dive into data sets and tasks organization strategies as well as into results and insights, all widely presented and discussed. Speaker(s): Paolo Spallaccini (System Engineer, Ericsson) Topic(s): Algorithms & Numerical Techniques, Audio, Image and Video Processing, Supercomputing (Intermediate) TUESDAY, MAY 15, 10:00 (25 MINUTES) ROOM A2 S0300 Jet: A Domain-Specific Approach to Parallelism for Film Fluid Simulation Discover how a domain-specific language can not only provide fast parallel performance but a simpler user experience in an environment that highly values flexibility. This talk will present the Jet language and heterogeneous compiler built on the LLVM compiler framework that enables efficient generation of X86 machine code or NVIDIA PTX for stencil computation on structured grids. We show that moving target-specific optimizations upstream into the compiler can greatly improve the ability to manipulate the logic of the solver and thus lower the barrier-to-entry for artists and developers without compromising on performance. Speaker(s): Dan Bailey (R&D, Double Negative) Topic(s): Parallel <strong>Program</strong>ming Languages & Compilers, Digital Content Creation & Film, Computational Fluid Dynamics (Intermediate) TUESDAY, MAY 15, 10:00 (25 MINUTES) ROOM L S0343 A Quantum Chemistry Domain-Specific Language For Heterogeneous Clusters This talk discuss the development of a Domain-Specific Language (DSL), the tools and the related runtime for efficiently generating Tensor Contractions (generalized matrix multiplications), an important part of many quantum chemistry methods (e.g. Coupled Cluster Theory). Starting from a high level description of the computation, the tool analyses it and generates optimized C, OpenCL or CUDA implementations. The runtime, supporting a task based computation model, is then able to execute the generated code on <strong>GPU</strong>-accelerated heterogeneous large scale clusters, maximizing the utilization of the processing elements and minimizing communication costs. Speaker(s): Antonino Tumeo (Research Scientist, Pacific Northwest National Laboratory), Oreste Villa (Research Scientist, Pacific Northwest National Laboratory) Topic(s): Quantum Chemistry, Supercomputing (Intermediate) TUESDAY, MAY 15, 10:00 (25 MINUTES) ROOM K S0376 Dynamic <strong>Program</strong>ming on CUDA: Finding the Most Similar DNA Sequence Learn a couple of techniques to speed up compute-heavy Dynamic <strong>Program</strong>ming algorithms on the <strong>GPU</strong>. Our particular problem regarded DNA sequences: given a reference sequence, how to find the one most similar to it among a large database? The sequences are millions characters long, and their similarity is calculated with a (quadratic) DP algorithm, which makes the problem very tough even for the <strong>GPU</strong>s. We speed up both the theoretical and practical side: we present programming techniques that enable Dynamic <strong>Program</strong>ming to be performed at the hardware speed, and improvements to the algorithm itself that drastically lower the execution time. Speaker(s): Grzegorz Kokosinski (Software Engineer, IBM Poland), Krzysztof Zarzycki (Senior Software Developer, IBM Poland) Topic(s): Bioinformatics, Algorithms & Numerical Techniques (Intermediate) TUESDAY, MAY 15, 10:00 (25 MINUTES) ROOM J3 S0520 Using <strong>GPU</strong>s to Speedup Chip Verification As VLSI designs become more complex, the process of verifying them becomes increasingly expensive and time consuming. Verification of such designs has become quite taxing as they take simulators to the edge in terms of both runtime demands and host memory requirements. In order to reduce verification time, different verification methodologies have been adopted including the use of emulators. However, emulators’ price point is high and so is the engineering time to set them up. Rocketick develops a Verilog co-simulator that uses <strong>GPU</strong>s as an acceleration platform. Rocketick’s product, RocketSim® is now part of NVIDIA’s design flow and it is being used to accelerate simulations by 10X-30X compared to the standard simulator and to reduce the memory footprint by 5X. In this session RocketSim ® will be presented using some real-world examples of verification flows. Speaker(s): Tomer Ben-David (Co-Founder and Vice President, R&D, Rocketick) Topic(s): Electronic Design Automation (Beginner) TUESDAY, MAY 15, 10:30 (80 MINUTES) KEYNOTE – HALL 1 S3000 Opening Keynote Do not miss this opening keynote, featuring Jen-Hsun Huang, CEO and Co-Founder of NVIDIA. Hear about what’s next in computing and graphics, and preview disruptive technologies and exciting demonstrations from across industries. Jen-Hsun co-founded NVIDIA in 1993 and has served since its inception as president, chief executive officer and a member of the board of directors. Speaker(s): Jen-Hsun Huang (CEO & Co-Founder, NVIDIA) Topic(s): General Interest (All Levels) TUESDAY, MAY 15, 14:00 (50 MINUTES) ROOM A3 S0024 <strong>GPU</strong>-Accelerated Path Rendering Standards such as Scalable Vector Graphics (SVG), PostScript, TrueType outline fonts, and immersive web content such as Flash depend on a resolution-independent 2D rendering paradigm that <strong>GPU</strong>s have not traditionally accelerated. This session explains a new opportunity to greatly accelerate vector graphics, path rendering, and immersive web standards using the <strong>GPU</strong>. By 31 CONFERENCE GUIDE TUESDAY
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GPU Consolidation and Virtualizatio
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SPEAKERS AND PANELISTS Arutyun Avet
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SPONSORS AND EXHIBITORS PLATINUM SP
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SPONSORS AND EXHIBITORS GOLD SPONSO
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