ENP-2505 Hardware Reference - Radisys

March 2002Copyright ©2002 by RadiSys Corporation.All rights reserved.EPC, INtime, iRMX, and RadiSys are registered trademarks of RadiSys Corporation. ASM, Brahma, DAI, DAQ,MultiPro, SAIB, Spirit, and ValuePro are trademarks of RadiSys Corporation.DAVID, MAUI, OS-9, and OS-9000 are registered trademarks of RadiSys Microware Communications SoftwareDivision, Inc. FasTrak, Hawk, SoftStax, and UpLink are trademarks of RadiSys Microware CommunicationsSoftware Division, Inc.† All other trademarks, registered trademarks, service marks, and trade names are the property of theirrespective owners.

Before you beginAbout related RadiSys productsENP software development kit (SDK)The ENP-2505 provides programming and runtime libraries for the Intel InternetExchange Architecture (IXA) SDK that adds software functionality specific toRadiSys platforms. You use the ENP-2505 to quickly develop optimizedapplications for the Intel IXP1200 network processor.OtherENP-2505 componentsFor additional information about some ENP-2505 components, see the followingdocuments located on the IXA SDK CD-ROM:• IXF440 Multiport 10/100 Mbps Ethernet Controller Data Sheet• IXP1200 Network Processor Data Sheet• IXP1200 Hardware Reference ManualThe following web site provides additional information about the maincomponents on the board:http://developer.intel.comWind River TornadoThese documents are part of the document set provided when youpurchase Tornado:Tornado User’s Guide, Explains how to use Tornado, an integrated StrongARMdevelopment environment from Wind River.Tornado API Programmer’s Guide and VxWorks Programmer’s Guide, Explains how tomodify VxWorks source code.PCI architecturePCI System Architecture, Fourth Edition, published by Addison-Wesley and authoredby Mindshare, Inc.PCI specifications, available at the PCI SIG web site:www.pcisig.comv

ContentsFiguresFigure 1-1. ENP-2505 ............................................................................................................................. 1.Figure 2-1. ENP-2505 DIP switches: default settings............................................................................... 4.Figure 3-1. ENP-2505: block diagram..................................................................................................... 12.Figure 3-1. Interrupt circuit..................................................................................................................... 15.Figure C-1. ENP-2505 connector locations ............................................................................................. 28.Figure C-2. 10/100 Mbps ports ............................................................................................................... 32.Figure D-1. Flash chip configuration ....................................................................................................... 35.ix

ENP-2505 Hardware ReferenceFeatures• Six 232 MHz microengines and a 232 MHz StrongARM core processor.• 256 megabyte (Mbyte) 144-pin PC100 SODIMM.• PCI interface:• 21555 PCI-to-PCI non-transparent bridge.• 64- or 32-bit, 2.2-compliant PCI bus running at 33 or 66 MHz.• Universal PCI card edge.• Four 10/100 megabit per second (Mbps), 10BASE-T and 100BASE-TX Ethernetinterfaces (IEEE 802.3 compliant).SpecificationsTable 1-1. ENP-2505 environmental specificationsCharacteristic State ValueMechanicalDimensions Width 10.6 cm (4.2")Height 28.9 cm (11.0")Component area 3.875" highBoard thickness 1.6 mmForm factorPCI 2.2; Single-slot PCIHeightHeat sink and 15.00 mmCPUHard disk drive/ 14.77 mmbracket assemblyEnvironmentalTemperature Operating 0°C to +55°.(ambient) Storage–4°C to +70°C.Relative humidity Operating Up to 95% relative humidity non-condensing.StorageUp to 95% relative humidity non-condensing.Altitude Maximum 10,000 feetAirflow Minimum 40LFMPowerPower consumption4.25amps at +3.3V (typical)2

Installation and configuration Chapter 2This chapter describes how to install an ENP-2505 reference board in aWindows NT workstation.For information about...Go to this page...Before you begin..................................................................................................... 4Setting jumpers and switches .................................................................................. 4DIP switches ........................................................................................................ 4Installing the ENP-2505 .......................................................................................... 5Changing boot options............................................................................................ 7Changing DIP switch settings............................................................................... 7Using the Boot Manager ..................................................................................... 8Post-installation troubleshooting.............................................................................. 9Maintaining and upgrading the ENP-2505 ............................................................. 9Removing the ENP-2505..................................................................................... 9Installing memory on the ENP-2505.................................................................. 10Avoid causing ESD (electrostatic discharge) damage:• Keep the card in its anti-static bag until you are ready to install.• Install the card (as described later in this chapter) only in a static-freeenvironment:• Wear an antistatic wrist strap attached to a known ground such as anantistatic lab mat.• Remove the card from its antistatic bag only in a static-free environment.• Avoid touching printed circuits, connector pins, and components. Wherepossible, hold the card only by its edges or mounting hardware.• Make the least possible movement with your body to minimize electrostaticcharges created by contact with clothing fibers, carpet, and furniture.• Keep one hand on the computer chassis, if possible, as you insert orremove a card.• Avoid placing the card on the chassis cover or on a metal table. The coverand metal table increase the risk of damage because they provide anelectrical path from your body through the card.• Always turn the computer off before removing a card from the chassis.The ENP-2505, like most other electronic devices, is susceptible to ESD damage.ESD damage is not always immediately obvious. It can cause a partialbreakdown in semiconductor devices that might not result in immediate failure.3

ENP-2505 Hardware ReferenceBefore you beginThe ENP-2505 requires the following:• Adequate ventilation, as described in Table 1-1: ENP-2505 environmentalspecifications on page 2.• A PC that runs Windows NT 4.0, Service Pack 6.• The serial cable that comes with the ENP-2505. (The cable connects the serialport on the board to the Windows NT workstation.)For a description of the serial cable, including pin information, see Debugconsole on page 33.• Software:• Internet Exchange Architecture (IXA) Software Developers Kit version 1.3(1.3.141) or 2.0 (2.0.83) for the Windows NT workstation, and the version1.3A patch for the Windows NT workstation. This is an integrateddevelopment VxWorks environment for developing and delivering codetargeted for microengines.• Tornado 2.0, available from Wind River Systems, Inc., for StrongARM †development.• ENP SDK 2.0. The ENP SDK supports VXworks version 5.4.Setting jumpers and switchesDIP switchesThe ENP-2505 includes one 4-position (SW0201) and one 8-position (SW1301)DIP switch for user configuration:Figure 2-1. ENP-2505 DIP switches: default settingsONON1 2 3 4SW02011 2 3 4 5 6 7 8SW1301Table 2-1. SW0201 DIP switch settingsSwitch Value Description1 0 On (Default) Puts the board in slave mode (hosted environment).Selecting this option causes ~SPCI_INTA to go to theWindows NT workstation through the 21555 PCI-to-PCI bridge.1 Off Puts the board in master mode (hostless environment). Selectingthis option causes these signals to come from the Windows NTworkstation and drive ~IXP1200_INTA on the target:~PCI_INTA~PCI_INTC~PCI_INTB~PCI_INTD4

Chapter 2: Installation and configurationFor more information about setting boot options, see Changing boot options onpage 7.Installing the ENP-2505Table 2-1. SW0201 DIP switch settings2 0 On (Default) Enables the primary PCI bus 64-bit extension.1 Off Disables the primary PCI bus 64-bit extension.3 0 On (Default) Enables the 21555 PCI-to-PCI bridge serial EEPROM.1 Off Disables the 21555 PCI-to-PCI bridge serial EEPROM.4 0 On (Default) Specifies a 32-bit BootROM.1 Off Specifies a 16-bit BootROM.Table 2-2. SW1301 DIP switch settingsSwitch Value Description1 0 On (Default) Enables Configuration register bit 0 (the leastsignificant bit).1 Off Disables Configuration register bit 0 (the least significant bit).2 0 On Enables Configuration register bit 1.1 Off (Default) Disables Configuration register bit 1.3 0 On (Default) Enables Configuration register bit 2.1 Off Disables Configuration register bit 2.4 0 On (Default) Enables Configuration register bit 3.1 Off Disables Configuration register bit 3.5 0 On (Default) Enables Configuration register bit 4.1 Off Disables Configuration register bit 4.6 0 On (Default) Enables Configuration register bit 5.1 Off Disables Configuration register bit 5.7 0 On (Default) Enables Configuration register bit 6.1 Off Disables Configuration register bit 6.8 0 On (Default) Enables Configuration register bit 7 (the mostsignificant bit).1 Off Disables Configuration register bit 7 (the most significant bit).To install the ENP-2505 in your Windows NT workstation:1. Remove the ENP-2505 from the packaging:A. Remove the ENP-2505 from its antistatic bag.B. Check the ENP-2505 for any visible signs of damage.The ENP-2505 has a 256MB unbuffered 144-pin SODIMM on the board. Ifyou do not have onboard memory, see Installing memory on the ENP-2505 onpage 10.5

ENP-2505 Hardware Reference2. Set the last three switches of the Configuration register to boot one of these:VxWorks module: System Monitor: Boot Manager:ONONON123123123If you select Boot Manager, you choose the operating system when thesystem starts.For detailed information about the Boot Manager and its commands, see oneof these:• Changing boot options on page 7.• The Boot Manager chapter in the ENP SDK Programmer’s Reference guide.3. Install the board:A. Select a PCI card slot in which to install the ENP-2505.The ENP-2505 must be installed in a PCI slot that supports busmastering. Most PCI slots in most systems do; however, a few do not.Check with the motherboard manufacturer.B. Remove the screw that secures the slot’s cover plate to the rear panel of thePC, and remove the cover plate.Slot cover plate6

Chapter 2: Installation and configurationC. Line up the ENP-2505 visually with your PCI card slot as shown:PCI card bracketENP-2505PCI card slotD. Slide the flat outside edge of the board under the bracket closest to thesystem board and align the PCI card bracket with the card support on therear panel of the PC.E. Insert the ENP-2505 into the PCI card slot and push firmly to seat the boardin the slot.F. Secure the board to the PC with the screw you removed in step 3B.G. Replace the PC’s cover following the manufacturer’s instructions.4. Connect the custom serial cable shown in the figure in Debug console on page 33.Do not connect or handle the cable during a lightning storm.5. Connect all other peripherals to the PC and connect it to a power source.Changing boot optionsYou can specify which application executes at boot—VxWorks, Boot Manager, orSystem Monitor—using any of the methods described below. For more informationabout these applications, see the ENP SDK Programmer’s Reference.Changing DIP switch settingsThe ENP-2505 provides Configuration register settings (SW1301) that you use toconfigure the board. Only the last three data bits are currently defined.These DIP switch positions, which you can change at any time, determine whichapplication executes at boot:VxWorks module: System Monitor: Boot Manager:ONONON1231231237

ENP-2505 Hardware ReferenceUsing the Boot ManagerThe ENP Software Development Kit (SDK) includes the Boot Manager. From thisapplication you can execute other available boot options.To select a boot option:1. Set your COM port to:Baud rate: 38400Parity:N (no parity)Data bits: 8Stop bits: 1Flow control: N (no flow control)2. Set the ENP-2505 DIP switches for Boot Manager.3. Power on the ENP-2505. The Boot Manager starts and displays this on theserial port:Press space bar to stop auto-boot...104. Press the space bar before the numerical value reaches zero. The Boot Managerprompt displays:[BootMgr]:5. (Optional) Enter this command to list available operating systems:p6. Enter this command:b [n]where n is the number of the OS you want to boot. You can enter only listed OSnumbers.The Boot Manager provides more operating system choices than thoseshown in the switch settings.For detailed information about the Boot Manager and its commands, see the BootManager chapter in the ENP SDK Programmer’s Reference guide.8

Chapter 2: Installation and configurationPost-installation troubleshootingYou can use the diagnostics and System Monitor that come with the ENP SoftwareDevelopment Kit to diagnose and correct hardware problems in the ENP-2505. Fora description of these diagnostic tools, see the ENP SDK Programmer’s Reference.In addition, the next table lists symptoms and possible solutions to some hardwareproblems that might occur after you install the ENP-2505.SymptomThe ENP-2505 LEDs D1301through D1304 do not turn on atall or are very dim.The ENP-2505 LEDs D1301through D1304 turn on (solid) butdo not change.The PC does not recognize a PCIcard in the ENP-2505 slot.The PC does see a PCI card in theENP-2505 slot, but does notrecognize it as an ENP-2505.Your system boots, but takes along time to do so.Your PC does not receive data.Possible solutionsEnsure that the power supply can provide the ratedpower required for the ENP-2505. If the problemstill persists, discontinue using the ENP-2505.Re-seat the memory module. If the problem stillpersists, the flash may be corrupt.Ensure that the ENP-2505 board, memory, andcable are properly installed.Ensure that the ENP-2505 is functioning by:• Watching LEDs D1301 through 01304 forchanges.• Using the debug port to watch for serial output.If the PC still does not recognize the ENP-2505,use the diagnostics provided with Windows NT 4.0.Ensure that the workbench was successfullyinstalled on the host PC.This is normal operation.When the operating system initializes, it must resetthe Primary Access Lockout Bit in the 21555,allowing the CPU controller to read configurationinformation. In some cases, this can take twentyseconds or more.Ensure that the network cables are:• TIA/EIA-568A Category 5 twisted-pairEthernet cables.• Properly installed.Maintaining and upgrading the ENP-2505Removing the ENP-2505To remove the ENP-2505 from your Windows NT workstation:1. Unplug the PC and all attached devices from power sources.2. Remove:A. The PC’s cover, following the manufacturer’s instructions.B. All cables from the board.9

ENP-2505 Hardware ReferenceC. The screw that secures the ENP-2505 to the rear panel of the PC.3. Pull the ENP-2505 straight out of the slot.4. Place the ENP-2505 on a flat, static-free surface.Installing memory on the ENP-2505Your ENP-2505 should have 256 megabyte (MB) unbuffered 144-pin SODIMMalready installed. If your board does not have SDRAM, you must install it beforeinstalling the board in your Windows NT workstation.The next table lists ENP-2505 SDRAM configuration options.Total NumberConfiguration Internal Bank RAS CASSize DRAMmemory of chips(per bank) Banks Bits Bits Bits256 MB 8 256 Mbit 8M x 8-bit 4 2 13 10To ensure reliable operation, use only SODIMMs qualified by RadiSys.Qualified SODIMMs include:DIMM Size Supplier Part Number256 MB Unigen A57326-001To install a SODIMM on the ENP-2505:1. If the ENP-2505 is already installed in your PC, remove it as described inRemoving the ENP-2505 on page 9.2. Locate the memory interface on the ENP-2505 board.3. To remove an existing SODIMM, push the clips on both sides away from theSODIMM. The SODIMM pops up to a 45-degree angle from the board. Pullthe old SODIMM out of the connector, maintaining the 45-degree angle.4. Align the new SODIMM with the connector, at about a 45-degree angle from theboard, and push it firmly into the connector as shown in the following side view.SODIMMPush inConnector45°Board5. Press the SODIMM toward the board; the clips lock themselves into place whenthe SODIMM is properly seated.10

Theory of operation Chapter 3This chapter provides information about the ENP-2505’s board layout andmain components.The ENP-2505 reference board uses a single Intel IXP1200 network processor for avariety of applications. It is PCI 2.2 compliant and works in both hosted andhostless environments.The ENP-2505 can operate in any Windows NT workstation with a standard PCIslot. It performs optimally in a 64 bit, 66 MHz PCI slot, and can also perform in a32-bit, 33 megahertz (MHz) slot.The ENP-2505 supports four 10/100 Mbps Ethernet ports, supported by an IXF440multiport Ethernet controller, along with four LXT972 PHY transceivers, and a21555 PCI-to-PCI bridge.When reading this file online, you can immediately view information about anyENP-2505 topic by placing the mouse cursor over the topic name and clicking:For information about...Go to this page...Organization ......................................................................................................... 12Block Diagram................................................................................................... 12Software interface................................................................................................. 13Memory map..................................................................................................... 13Peripheral register definitions............................................................................. 13Interrupts........................................................................................................... 15Hardware components.......................................................................................... 17IXP1200............................................................................................................ 17IX bus................................................................................................................ 17PCI interfaces .................................................................................................... 18Ethernet interfaces ............................................................................................ 19CPLD................................................................................................................. 20SRAM................................................................................................................ 20SDRAM ............................................................................................................. 21Timing components........................................................................................... 21Power supply ..................................................................................................... 22LEDs.................................................................................................................. 2211

ENP-2505 Hardware ReferenceOrganizationBlock DiagramThe next figure shows the clock frequencies driving the ENP-2505’s main componentsand the bandwidths and frequencies of the buses that link these components.Figure 3-1. ENP-2505: block diagramPC workstationPrimary PCI bus(32-bit/33 MHz or 64-bit/66 MHz)21555 PCI-to-PCI bridgePCI option cardconnectors (2) (2)Secondary PCI bus32-bit, (33/66 MHz)SDRAM(8 MB)Flash (8 MB)SRAM data bus(32-bit, 116 MHz)IXP1200 (232MHz)IXP1200 (200 MHz)Microengines (6)SDRAM data bus(64-bit, 116 MHz)SDRAM(256 MB)Microengines(6)IX bus StrongARMIX interface bus interface of Strong coreprocessor ARMof IXP1200 coreprocessorIXP 1200CPLD66 MHz clockIX bus(64-bit, 66 MHz)IXF440IXF4403.68 MHz clock25 MHz clock LXT972 LXT972 PHY PHYtransceivers (4)Quad RJ-45connector12

Chapter 3: Theory of operationSoftware interfaceMemory mapThe IXP1200’s SDRAM, SRAM, and BootROM address spaces use linearaddressing, with the memory devices occupying addresses starting at 0000h andextending for the size of the installed memory. The next table shows the memorymap for these storage devices and peripheral address space. The peripheral addressspace is decoded in the CPLD, which includes processor-accessible registers andprovides the chip select signal to the IXF440.Peripheral register definitionsAll CPLD register accesses are eight bits wide. Set undefined bits to logic 0 onwrites. All undefined register bits and all undefined register addresses returnundetermined bit values on reads, except that weak pull-ups may pull unusedbits to a logic 1 level.Base address Address size Access Location Register0x00000000 8 MB R (to write, use Flash N/Athe flash utility)0x10000000 8 MB R/W SRAM N/A0x38400000 32 KB R/W IXF440 IXF440 Ports 1 through4CSR0x38508000 4 B R/W CPLD User-defined board LEDCSR. Only the last fourdata bits are significant.0x38518000 8 bits R CPLD CPLD revision0x38528000 8 bits R CPLD PCB revision0x385B8000 4 B R CPLD Configuration register. Thelast eight data bits aresignificant, but only the lastthree are currently defined.0x38538000 8 bits R CPLD Interrupt status register0xB0044000 4 KB R/W Scratch N/Amemory0xC0000000 256 MB R/W SDRAM N/AUser-defined board LED Control Status registerThe 8-bit, read-only user-defined LED control status register (CSR) controls thefour software controlled board LEDs. The register is cleared to 00h at a reset. Thefollowing table describes the user-defined LED CSR field.Table 3-1. LED Control Status registerBit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 00 0 0 0 LED3(D1304)LED2(D1303)LED1(D1302)LED0(D1301)13

ENP-2505 Hardware Reference0 The specified LED is on.1 The specified LED is off.For example:• 0000b indicates that LED0 through LED3 are on.• 0001b indicates that LED0 is off and LED1 through LED3 are on.• 0011b indicates that LED0 and LED1 are off and the other two are on.There are sixteen possible board LED configurations (00h to 0Fh).CPLD Revision registerThis 8-bit read-only register contains the current CPLD revision number, which is abinary-encoded value.PCB Revision registerThis 8-bit read-only register contains the current PCB artwork revision number,which is a binary-encoded value. This value is assigned during PCB fabrication.Interrupt Status registerThis 8-bit read-only register indicates the states of the interrupt signals on the PCIbus in the master/slave mode.The next table describes the value of the Interrupt Status register fields. For moreinformation, see Table 2-1: SW0201 DIP switch settings on page 4.Configuration register settingsTable 3-2. LED Control Status registerBit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 00 0 Master/slave SPCI INTA PPCI INTD PPCI INTC PPCI INTB PPCI INTAmodeSignal name/mode Value Possible settingsPPCI INT [A:D]0 (Default) No interrupt is pending.Host PCI bus interrupt 1 An interrupt is pending.SPCI INTA0 (Default) No interrupt is pending.PCI option card interrupt 1 An interrupt is pending.Master/slave mode 0 (Default) Slave mode; interrupts route to host PC.Interrupt handling mode 1 Master mode; all interrupts route to the IXP1200.This 8-bit, read-only register (SW1301) indicates the setting of the eightconfiguration DIP switch positions. Only the last three data bits are currentlydefined. The default value (010 or “on, off, on”) boots VxWorks.Within these fields, 0 indicates that a switch is on, while 1 indicates that a switch isoff. The configuration register fields are described in Table 2-2: SW1301 DIPswitch settings on page 5.14

Chapter 3: Theory of operationInterruptsPCI interruptsThe ENP-2505 can operate in two interrupt modes:• Slave mode (default in hosted environment). The ENP-2505 is a slave moduleon the host PCI bus and the IXP1200 can generate an interrupt to the hostprocessor. The IXP1200’s ~PCI_IRQ output drives the ~s_pme input to the21555 PCI bridge, which (if not masked) generates an ~INTA interrupt on thehost PCI bus.• Master mode. The ENP-2505 acts as the master of the back plane PCI bus andthe IXP1200 services any pending interrupts. The ~INTA through ~INTDsignals on the host PCI bus and on the PCI option card connectors areconnected to the CPLD. The CPLD generates an interrupt on ~PCI_IRQ to theIXP1200 if any of them are low. The status of all eight interrupt signals isavailable to the IXP1200 in the Interrupt Status Register.The CPLD controls interrupt signal routing, based on a bit in the module controlregister, but the ~PCI_IRQ pin on the IXP1200 must also be configured as input oroutput.Figure 3-1. Interrupt circuit+3.3V~spci_intaIXP1200~ixp1200_inta~spci_spme21555AB+3.3VENPNot hosted~pci_master/slaveHosted~PCI_INT~pci_inta, ~pci_intb, ~paci_intc, ~pci_intdHost15

ENP-2505 Hardware ReferenceI 2 C EEPROM contentsThe next table lists the description and default contents for each I 2 CEEPROM field.Table 3-3. I 2 C EEPROM formatBase address Size Description0x00 1 bytes PROM format0x01 12 bytes Manufacturer0x0D 14 bytes Model ID0x1B 2 bytes Chip revision0x1D 2 bytes PLL value0x1F 2 bytes IX speed0x21 3 bytes Processor speed0x24 3 bytes SDRAM size0x27 2 bytes SRAM size0x29 2 bytes MAC port number.0x2B 12 bytes MAC address 10x37 12 bytes MAC address 20x43 12 bytes MAC address 30x4F 12 bytes MAC address 40x5B 10 bytes Part number0x65 2 bytes Part revision0x67 10 bytes Serial number0x71 10 bytes Date0x7B 2 bytes Test status0x7D 10 bytes Reserved0x87 2 bytes Checksum21555 PCI-to-PCI bridge serial EEPROMYou can overload the PCI configuration space registers and state values of the21555 PCI-to-PCI bridge from a serial EEPROM. Using the serial EEPROM tochange internal default values allows you to avoid modifying the bridge itself.The serial EEPROM’s factory default values are listed in Appendix B, 21555 PCIto-PCIbridge serial EEPROM.16

Chapter 3: Theory of operationHardware componentsThis section describes the following ENP-2505 components:For information about...Go to this page...IXP1200 ............................................................................................................... 17IX bus ................................................................................................................... 17PCI interfaces ....................................................................................................... 18Ethernet interfaces................................................................................................ 19CPLD .................................................................................................................... 20SRAM ................................................................................................................... 20SDRAM................................................................................................................. 21Timing components .............................................................................................. 21Power supply ......................................................................................................... 22IXP1200IX busThe IXP1200 network processor features:• A StrongARM core processor which runs at an operating frequency of up to232 MHz. This 32-bit RISC processor features:• Large amounts of local memory and registers, including 16 kilobyte (KB)instruction cache, 8 KB data cache, and 512 byte cache for data used onceand discarded.• Write buffer.• Memory management unit.• Access to the IXP1200 FBI unit, PCI unit, and SDRAM unit through the IX bus.• Six microengines, which run at an operating frequency of up to 232 MHz. Each32-bit RISC microengine features:• Support for four threads using four independent counters.• Single-cycle arithmetic logic unit (ALU) and shift operations.• No overhead for context switching.• Large amounts of local memory and registers, including 1 K x 32 bitinstruction control store, 128 32-bit general purpose registers, and 12832-bit transfer registers.• Access to the IXP1200 FBI Unit, PCI DMA channels, SRAM, and SDRAM.The IX bus provides a 4.2 Gbps interface to peripheral devices. The maximumoperating frequency of the IX bus is 66 MHz. The IX bus consists of 64 data pins,23 control pins, and a clock input pin.The IX bus operates in 64-bit bidirectional mode. The entire 64-bit data path ofsignal name FDAT[63:0] is used for reads and writes to IX bus devices. TheIXP1200 drives and receives all 64 bits of the IX bus in this mode.17

ENP-2505 Hardware ReferencePCI interfacesValid bytes are indicated on signal name ~FBE[7:0] driven by the IXP1200 duringwrites and by the IX bus slave device on reads.A shared IX bus mode is supported in 64-bit bidirectional mode. For the signalnames that the IX bus masters must drive and IX bus slaves must tri-state, see thelist at the bottom of Table 25 in the IXP1200 Network Processor Data Sheet.FBI unitThe FBI unit services fast peripherals on the IX bus. It contains the IXP1200 receivefirst-in-first-out (RFIFO) and transmit first-in-first-out (TFIFO) elements, thecontrol and status registers (CSR), 4 KB scratchpad memory, and a hash unit forgenerating 48 and 64-bit hash keys. It also contains the drivers and receivers for theIX bus.Ready busThe ready bus, a sideband bus that operates parallel to the IX bus, consists of eightadditional data pins and five control pins. Synchronous to the IX bus clock, aprogrammable hardware sequencer controls its operation. Ready bus cycles areseparate and distinct from IX bus cycles.Up to twelve sequencer commands load at chip initialization time and run in acontinuous loop. You use the commands to sample FIFO status for the IX busdevices, send Flow Control messages to MAC devices, and perform reads/writes toother IXP1200 devices.Primary and secondary PCI busesThe primary PCI bus (external host bus) and secondary PCI bus (internal PCI bus)are linked through the 21555 PCI-to-PCI bridge. The external host bus can be either32 or 64 bits wide and may operate at either 33 or 66 MHz. It connects the 21555PCI-to-PCI bridge and the PC host.The internal PCI bus operates only at +3V signaling. It connects the 21555PCI-to-PCI bridge to the IXP1200 and PCI option card connectors.A serial EEPROM connects to the SROM interface of the 21555 bridge device. Thisserial EEPROM stores the 21555 PCI-PCI bridge configuration space informationand module configuration information, such as vendor ID and device ID. The serialEEPROM is accessible from both the IXP1200 processor and a host processor. Fora description of the serial EEPROM contents, see Appendix B, 21555 PCI-to-PCIbridge serial EEPROM.18

Chapter 3: Theory of operationEthernet interfacesThe next table lists the PCI configuration space locations for devices on thesecondary PCI bus. Each device’s IDSEL pin connects to the listed secondary PCIaddress pin. To select the configuration registers of a given device, you must make aPCI configuration space access with the device’s corresponding IDSEL address bitset. For additional PCI configuration space register data, see Appendix A, PCIconfiguration registers.21555 PCI-to-PCI bridgeTable 3-4. Secondary PCI bus device configurationPeripheral IDSEL INTSecondary PCI arbitrationREQ/GNT pairIXP1200 AD12 A 021555 PCI-to-PCI bridge AD11 A N/AThe primary PCI bus connects to the host through the A and B PCI connectors. Thesecondary PCI bus for the 21555 PCI-to-PCI bridge uses a 32-bit +3.3V data buswhich runs at 33 or 66 MHz. The 21555 PCI-to-PCI bridge accepts universalsignalling voltages on the primary bus side.Note that when running in a hostless environment, a PCI clock (33 or 66 MHz) andan active low PCI reset signal must be made available to the ENP-2505.IXF440 Ethernet controller and LXT972 PHY transceiversThe IXF440 Ethernet controller and four LXT972 PHY transceivers providesupport for four 10BASE-T and 100BASE-TX connections on the ENP-2505. TheIXF440 Ethernet controller also supports the IX bus interface on the IXP1200.Each LXT972 PHY transceiver sends and receives continuous 10 Mbps or100 Mbps using an RJ-45 connector.Each LXT972 PHY transceiver supports:• Auto-negotiation and parallel detection.• Standard half or full-duplex operation.• Integrated LED drivers.For pinout information, see Ethernet connectors and LEDs on page 32. For adescription of the port LED indicators, see Port LEDs on page 22.The next table lists base memory address and address size for each port.Table 3-5. Port memory addressesPort number Base memory address Address size1 38400000 4 KB2 38401000 4 KB19

ENP-2505 Hardware ReferenceTable 3-5. Port memory addressesPort number Base memory address Address size3 38402000 4 KB4 38403000 4 KBCPLDThe complex programmable logic device (CPLD):• Decodes peripheral bus access addresses and enables the appropriate resourcesonto the bus.• Internally implements various status and control registers, including user strapoption status, LED indicator control, and PHY multiplexor control registers.• Drives the user-defined board LED indicators.• Implements interrupt routing logic for master and slave mode operation.CPLD program headerA 6-pin, 0.1" spacing male header interfaces to the control CPLD’s JTAG port, withthe pin assignments shown in the following table. The JTAG port on the IXP1200 isdisabled using biasing resistors and connects to test pads so that JTAG testing canbe done with an ICT fixture.Table 3-6. CPLD programming header pin assignmentsPin Signal Comments Pin Signal Comments1 Ground Power 4 TMI Mode in2 TDI Data in 5 TDO Data out3 TCK Clock in 6 +3.3VDC PowerSRAMThe 32-bit wide SRAM interface of the IXP1200 connects synchronous SRAM forhigh-speed data storage and a buffered interface for BootROM for program startupand peripherals (also referred to as slow port access).The SRAM interface operates at half the StrongARM core processor speed. 8MB ofsync burst DCD SRAM are installed on the ENP-2505, using four devices.Each device has these features:• +3.3V operation in a 100-pin TQFP package.• 512K x 32-bit configuration (2 MB capacity).• Synchronous, linear or interleaved burst, double-cycle deselect operation.The following tables shows possible SRAM configuration options:Total memory Number of chips Size SRAM Configuration4 MB 4 1 MB 256 Mbit x 32 bit8MB 4 2 MB 512 Mbit x 32 bit20

Chapter 3: Theory of operationFlashBy default, the ENP-2505 comes with 8 MB of flash memory, consisting of two4 MB, 16-bit flash BootROM devices. The two BootROM devices share the sameaddress and control lines; the upper flash uses data bits D(31:16) and the lowerflash uses data bits D(15:0) from the SRAM bus.The next table lists BootROM flash configuration options.Total memory Number of chips Bus width Configuration8MB 2 32 2 Mbit x 16 bitFor a map of the flash memory space, see Appendix D, Flash memory addresses.SDRAMThe IXP1200 uses SDRAM for mass data storage and supports up to 256 MB of64-bit wide memory. On the ENP-2505, the SDRAM interface addresses 256 MB of32-bit wide memory. The SDRAM has an access time of 6 nanoseconds or less witha minimum CAS latency of 2 and is PC133-compliant.The SDRAM interface is implemented as a 256MB SODIMM module with thefollowing characteristics:• JEDEC standard 144 pin small outline, dual inline memory module (SODIMM).• Single 3.3 V power supply.• LVTTL compatible inputs and outputs.• Unbuffered.• SDRAM 133 MHz timing ( –7.5 speed grade).• Single CS number.• 13 row, 10 column configuration.The next table lists ENP-2505 SDRAM configuration options.Timing componentsTotal NumberSize SDRAMConfiguration Internal Bank RAS CASmemory of chips(per bank) banks bits bits bits256 MB 8 32 MB 8 Mbit x 8 bit 4 2 13 10Speed and timingThe –7.5 speed grade is made up of different versions. Each version addresses adifferent setting PC133 supports at the 133 MHz bus level. For more details, see theUnigen specification.The diagram shown in figure 3-1 on page 12 shows the following timingcomponents on the ENP-2505:21

ENP-2505 Hardware Reference• The PCI bus clock drives the 21555 PCI-to-PCI bridge, the secondary interfaceof the IXP1200. You can configure it to run at 33 or 66 MHz.• The 116 MHz IXP1200 processor clock drives the SDRAM, SRAM, andflash devices.• The 66 MHz IX bus clock drives the IXF440 Ethernet controller, the CPLD, andthe IX bus interface. Asynchronous to the core clock, it is driven by an externallow voltage phase lock loop (PLL) clock driver.• The 25 MHz transceiver clock drives the four LXT972 PHY transceivers.• The 3.68 MHz core clock drives the StrongARM core processor andmicroengines at 232 MHz. The clock is driven by an external low voltage phaselock loop (PLL) clock driver.Power supplyLEDsThe ENP-2505 uses less than 16.5 watts. The PCI local bus specification stipulates25 watts of power total per slot. Power comes onto the ENP-2505 through the hostPCI bus interface. The board is a universal PCI card that uses +5.0V DC and +3.3VDC supplied by the system power supply and provides for on-board regulation togenerate the required +2.0V rail.+2.0V DC supplyA linear regulator generates the +2.0V DC supply rail from the +3.3V DC supply.Primarily, the core of the IXP1200 uses this supply. This configuration ensures thatthe +3.3V DC rail is stable earlier than the +2.0V DC rail during power-on andtherefore protects the IXP1200 against latch up. An adjustable 5 Amp linearregulator generates the +2.0V DC supply.Port LEDsEach of the four 10/100 Mbps ports has two LEDs:• Yellow indicates port link. When this LED lights, the link is up.• Green indicates port activity. When the green LED lights (either solid orblinking), the port is transmitting or receiving packets.For more information about these LEDs, see Ethernet connectors and LEDs onpage 32.User-defined board LEDsFour right-angle green LED indicators, mounted along the top edge of theENP-2505, are under software control and can be used to debug the board.The base memory address for board LEDs is 0x38508000. The address size is4 MB; only the last four data bits are signficant.22

PCI configuration registersAppendix AThis appendix describes PCI configuration registers on the IXP1200 unique to theENP-2505. PCI configuration registers not listed in this appendix are the same as onany other PCI device and can be found in PCI System Architecture, Fourth Edition.The PCI configuration registers are part of the main PCI interface of the IXP1200.They are accessible on the PCI bus using the CFG_RD and CFG_WR commands.They are shown as 32-bit entities as they appear on PCI[31:0].Do not change the values of these fields. Doing so prevents the Workbenchdriver from running.Table A-1. PCI configuration CSRsOffset Field(in hex) name Description R/W Reset0x00 DEV_ID Device ID R 0xB5550x02 VEND_ID Vendor ID R 0x80860x2c SUB_VENDOR_ID Subsystem vendor ID RW 0x13310x2e SUB_SYSTEM_ID Subsystem device ID RW 0x0024R = Read-only; writes ignored. RW = Read and write.23

ENP-2505 Hardware Reference24

21555 PCI-to-PCI bridgeserial EEPROMAppendix BYou can overload the PCI configuration space registers and state values of the21555 PCI-to-PCI bridge from a serial EEPROM. Using the serial EEPROM tochange internal default values allows you to avoid modifying the bridge itself.You can use the mksrom utility to the contents of the serial EEPROM. For adefinition of the mksrom commands, see mksrom.doc located on the SDKinstallation CD. The next table lists the serial EEPROM’s factory default values.Base address Contents Base address Contents0x00 80 0x22 000x01 00 0x23 000x02 00 0x24 000x03 00 0x25 000x04 00 0x26 000x05 80 0x27 000x06 06 0x28 000x07 31 0x29 000x08 13 0x2A 000x09 24 0x2B 000x0A 00 0x2C 000x0B 00 0x2D 000x0C 00 0x2E 000x0D 00 0x2F 000x0E 08 0x30 000x0F 06 0x31 0C0x10 00 0x32 000x11 00 0x33 000x12 00 0x34 000x13 00 0x35 020x14 00 0x36 000x15 00 0x37 000x16 00 0x38 000x17 00 0x39 000x18 00 0x3A 000x19 00 0x3B 000x1A 00 0x3C 000x1B 00 0x3D 000x1C 00 0x3E 0025

ENP-2505 Hardware ReferenceBase address Contents Base address Contents0x1D 00 0x3F 000x1E 00 0x40 000x1F 00 0x41 000x20 00 0x42 000x21 0026

Connectors and cablesAppendix CThis appendix details the connectors on the ENP-2505 CPU board and gives thesignal pinout of each connector.This product includes the connectors listed in the table below. When reading thisfile online, you can immediately view information about any connector by placingthe mouse cursor over a connector name and clicking:For information about...Go to this page...Connector locations ............................................................................................... 28PCI connector........................................................................................................ 29Ethernet connectors and LEDs................................................................................ 32User-defined board LEDs........................................................................................ 32Debug console....................................................................................................... 33Serial port .......................................................................................................... 33Null-modem serial cable..................................................................................... 3327

ENP-2505 Hardware ReferenceConnector locationsFigure C-1 shows the locations of the connectors on the ENP-2505.For information about installation and DIP switch settings, see Chapter 2,Installation and configuration.Figure C-1. ENP-2505 connector locationsPCI connectorEthernet connectorsand LEDs28

Appendix C: Connectors and cablesPCI connectorThe next table lists the connector pin assignments for the primary PCI bus interfaceon the ENP-2505. The electrical and mechanical specifications are defined in thePCI Local Bus specification.Signal ~PRSNT1(B9) has been tied low to GND for Komodo to be able todetect PA1120 card versus a SCSI PCI card.Pin Side B Side A Comments1 –12V ~TRST 32-bit start2 TCK +12V3 Ground TMS4 TDO TDI5 +5V +5V6 +5V ~INTA7 ~INTB ~INTC8 ~INTD +5V9 ~PRSNT1** Reserved/P2_TX_ERR10 Reserved/P3_TX_ERR +VI/O11 ~PRSNT2 Reserved/P2_RX_ERR12 KEYWAY KEYWAY +3.3V key13 KEYWAY KEYWAY +3.3V key14 Reserved/P3_RX_ERR Reserved15 Ground ~RST16 CLK +VI/O17 Ground ~GNT18 REQ Ground19 +VI/O Reserved20 AD[31] AD[30]21 AD[29] +3.3V22 Ground AD[28]23 AD[27] AD[26]24 AD[25] Ground25 +3.3V AD[24]26 C/~BE[3] IDSEL27 AD[23] +3.3V28 Ground AD[22]29 AD[21] AD[20]30 AD[19] Ground31 +3.3V AD[18]32 AD[17] AD[16]33 C/~BE[2] +3.3V34 Ground ~FRAME29

ENP-2505 Hardware ReferencePin Side B Side A Comments35 ~IRDY Ground36 +3.3V ~TRDY37 ~DEVSEL Ground38 Ground ~STOP39 ~LOCK +3.3V40 PERR SDONE41 +3.3V ~SBO42 ~SERR Ground43 +3.3V PAR44 C/~BE[1] AD[15]45 AD[14] +3.3V46 Ground AD[13]47 AD[12] AD[11]48 AD[10] Ground49 M66EN AD[09] 66 MHz/gnd50 KEYWAY KEYWAY 5V key51 KEYWAY KEYWAY 5V key52 AD[08] C/~BE[0]53 AD[07] +3.3V54 +3.3V AD[06]55 AD[05] AD[04]56 AD[03] Ground57 Ground AD[02]58 AD[01] AD[00]59 +VI/O +VI/O60 ~ACK64 ~REQ6461 +5V +5V62 +5V +5V 32-bit endKEYWAY KEYWAY 64-bit spacerKEYWAY KEYWAY 64-bit spacer63 Reserved Ground 64-bit start64 Ground C/~BE[7]65 C/~BE[6] C/~BE[5]66 C/~BE[4] +VI/O67 Ground PAR6468 AD[63] AD[62]69 AD[61] Ground70 +VI/O AD[60]71 AD[59] AD[58]72 AD[57] Ground73 Ground AD[56]30

Appendix C: Connectors and cablesPin Side B Side A Comments74 AD[55] AD[54]75 AD[53] +VI/O76 Ground AD[52]77 AD[51] AD[50]78 AD[49] Ground79 +VI/O AD[48]80 AD[47] AD[46]81 AD[45] Ground82 Ground AD[44]83 AD[43] AD[42]84 AD[41] +VI/O85 Ground AD[40]86 AD[39] AD[38]87 AD[37] Ground88 +VI/O AD[36]89 AD[35] AD[34]90 AD[33] Ground91 Ground AD[32]92 Reserved Reserved93 Reserved Ground94 Ground Reserved 64-bit end31

ENP-2505 Hardware ReferenceEthernet connectors and LEDsThese RJ-45 connectors, located on the front panel, provide support for one10/100BASE-T Ethernet channel apiece:Figure C-2. 10/100 Mbps portsPort 1Port 2Port 3Green (link) LEDYellow (speed) LEDPort 4LED2LED112345678Table C-1. Ethernet RJ-45 pinoutPin Signal Pin Signal1 Transmit+ 5 Terminated2 Transmit– 6 Receive–3 Receive+ 7 Terminated4 Terminated 8 TerminatedTable C-2. Port LEDsLED Color Signal Description1 Yellow Speed Indicates the following:• Lit: 100 mbit port speed.• Not lit: 10 mbit port speed.2 Green Link When lit, the link is active.User-defined board LEDsFour right-angle green LED indicators, mounted along the top edge of theENP-2505, are under software control and can be used to debug the board. Formore information about these LEDs, see User-defined board LEDs on page 22.32

Appendix C: Connectors and cablesDebug consoleSerial portA 3-pin, 0.1" spacing male header interfaces to the RS-232 debug console, with thepin assignments shown in the next table.Null-modem serial cablePin 1 is the square pin, as viewed from the back of the board, and is located onthe leftmost side of the RS-232. Pin 3 is located on the rightmost side of RS-232.Table C-3. IXP1200 debug console header pin assignmentsPin number Signal Comments1 TXA Serial output2 RXA Serial input3 GroundThe next figure shows the custom serial cable shipped with the board. This cable isconfigured as a null-modem connection.HostENP-2505Molex termination pin532Six feet cable123Female DB-9 connectorMolex housing with LRampHostGroundRxTxElectrical connectionsENP-2505GroundTxRx33

ENP-2505 Hardware Reference34

Flash memory addressesAppendix DThe ENP-2505 flash chip contains these major sections:Figure D-1. Flash chip configuration0x080000000x0800FFFF0x080100000x0807FFFF0x080800000x080BFFFF0x080C00000x080FFFFF0x081C0000Boot ManagerBoot parametersand System MonitorReservedOS(such as VxWorks)User-defined area0x087FFFFF35

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GlossaryBARbig-endianBISTCRCcyclicredundancycheckDIMMdirectmemoryaccessdual in-linememorymoduleEPBGAendiannessENP-2505ESPHISRIXP1200networkprocessorlightemittingdiodeAcronym for PCI base address register.Byte ordering such that byte[0] is the leftmost, or most significant, byte in any datum.See also little-endian.Built-in self test.Cyclic redundancy check.(CRC) A common technique for detecting data transmission errors. A number of filetransfer protocols, including Zmodem, use CRC in addition to checksum.Dual inline memory module.(DMA) A technique for transferring data from main memory to a device withoutpassing it through the CPU. Computers that have DMA channels can transfer datato and from devices much more quickly than computers without a DMA channelcan. This is useful for making quick backups and for real-time applications.(DIMM) A small circuit board with a 64-bit path that holds memory chips. A singlein-line memory module (SIMM) has a 32-bit path to the memory chips whereas aDIMM has 64-bit path. Because the Pentium processor requires a 64-bit path tomemory, you need to install SIMMs two at a time. With DIMMs, you can installmemory one DIMM at a time.Enhanced plastic ball grid array.Byte order. See also big endian and little endian.The ENP-2505 is a reference board that contains the Intel IXP1200 networkprocessor, a high-speed packet-processing chip. The ENP-2505 has two primaryaudiences: application developers that create and test network applications andnetwork equipment vendors and original equipment manufacturers that want tointegrate the architecture into a variety of network equipment devices.Enhanced serial port.Host Interrupt Status register.The Intel IXP1200 network processor, a high-speed packet-processing chip in theENP-2505, performs the following packet classification tasks: arithmetic and logicaloperations, field extracts, compares, Boolean reductions, and checksums. TheIXP1200 features a StrongARM core processor and six programmable microengines.See also StrongARM core processor and microengine.(LED) A semiconductor device that converts electrical energy into light, used, forexample, for the activity lights on computer disk drives. Light-emitting diodes work37

ENP-2505 Referencelittle-endianmediumaccesscontrollermemorymanagement unitmicroengineMIBMIIMMUmuxNATNICNEVPCIon the principle of electroluminescence and are highly efficient, producing little heatfor the amount of light output.Byte ordering such that byte[0] is the rightmost, or least significant, byte in anydatum. See also big-endian.(MAC) A hardware address that uniquely identifies each node of a network. In IEEE802 networks, the Data Link Control (DLC) layer of the OSI Reference Model isdivided into two sublayers: the Logical Link Control (LLC) layer and the MediaAccess Control (MAC) layer. The MAC layer interfaces directly with the networkmedia.The hardware component that manages virtual memory systems. Typically, theMMU is part of the CPU, though in some designs it is a separate chip. The MMUincludes a small amount of memory that holds a table matching virtual addresses tophysical addresses. This table is called the Translation Look-aside Buffer (TLB). Allrequests for data are sent to the MMU, which determines whether the data is in RAMor needs to be fetched from the mass storage device. If the data is not in memory, theMMU issues a page fault interrupt.A fast packet processor. There are six microengines on every IXP1200 networkprocessor. This processor handles packets from the network and sends exceptionpackets to the StrongARM core processor. See also StrongARM core processor andIXP1200 network processor.(Management Information Base) A database of objects that can be monitored by anetwork management system. Both SNMP and RMON use standardized MIBformats that allows any SNMP and RMON tools to monitor any device defined bya MIB.Medium independent interface. See also PHY.(Memory Management Unit) The hardware component that manages virtualmemory systems.Another term for multiplexor, a communications device that combines severalsignals for transmission over a single medium. A demultiplexor completes theprocess by separating multiplexed signals from a transmission line. Frequently amultiplexor and demultiplexor are combined into a single device capable ofprocessing both outgoing and incoming signals.(Network Address Translation) An Internet standard that enables a local-areanetwork (LAN) to use one set of IP addresses for internal traffic and a second set ofaddresses for external traffic.(Network Interface Card) An expansion board inserted into a computer so thecomputer can be connected to a network. Most NICs are designed for a particulartype of network, protocol, and media, although some can serve multiple networks.Network equipment vendor.(Peripheral component interconnect) A specification for a type of card controller/bussystem. A local bus standard developed by Intel Corporation. Most modern PCsinclude a PCI bus in addition to a more general ISA expansion bus. PCI is a 64-bitbus, though it is usually implemented as a 32-bit bus. It can run at clock speeds of38

GlossaryPCSRPHYRISCStrongArmcoreprocessorTCPVPN33 or 66 MHz. At 32 bits and 33 MHz, it yields a throughput rate of 133 MBps. TheENP-2505 can operate in any desktop or rack-mount server with a standard PCI slot,including a 32-bit 33 megahertz (MHz) slot, but performs optimally at 64 bit/66MHz PCI. The IXP1200 side of the bridge can be configured for 32 bit/66 MHz or32 bit/33 MHz, depending on the needs of the customer.Processor Control and Status Register.Abbreviation for physical layer, as in Ethernet physical layer device, the first, orlowest, of the seven layers in the International Organization for Standardization'sOpen Systems Interconnection (OSI) model for standardizing computer-to-computercommunications.The physical layer is totally hardware-oriented and deals with allaspects of establishing and maintaining a physical link between communicatingcomputers. Among specifications covered on the physical layer are cabling, electricalsignals, and mechanical connections. Manages putting data onto the network mediaand taking the data off.Reduced instruction set computer.The embedded RISC processor used in an IXP1200 to handle exceptionpackets sent by fast packet processing microengines. See also microengine andIXP1200 network processor.(Transmission Control Protocol) A communications protocol for handling (sendingand acknowledging) packets transmitted end-to-end.(Virtual Private Network) A network that is constructed by using public wires toconnect nodes. For example, there are a number of systems that enable you to createnetworks using the Internet as the medium for transporting data. These systems useencryption and other security mechanisms to ensure that only authorized users canaccess the network and that the data cannot be intercepted. A set of nodes on a publicnetwork such as the Internet that communicate among themselves using encryptiontechnology so that their messages are as safe from being intercepted and understoodby unauthorized users as if the nodes were connected by private lines.39

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IndexS A B C D E F G H I J K L M N O P Q R S T U V W X Y ZAaddresses, flash memory 35.addresses, serial PROM 25.altitude 2.Bboardblock diagram 12.clock frequencies 12.layout 1., 11.–12.LEDs 22., 32.Boot Manager 6., 7.boot optionsBoot Manager 6., 7.System Monitor 6., 7.using Configuration register switches 7.VxWorks 6., 7.Ccable requirements 4.clock frequencies, board 12.complex programmable logic device, see CPLDcomponents, timing 21.Configuration register switches, booting with 7.configuration registers 23.connectorsEthernet 32.conventions, notational iv.CPLDhardware description 20.Eelectrostatic discharge, avoiding 3.e-mail address, RadiSys iv.ENP-2505installing onto Windows NT 5.–7.removing 9.ESD, avoiding 3.Ethernet, connector 32.external serial PROM contents 25.FFBI unit, IX bus 18.flash memoryaddresses 35.SRAM 21.front panelEthernet connector 32.Gglossary 37.–??, 39.–??Hhandling static-sensitive devices 3.hardware21555 PCI-to-PCI bridge 19.board layout 1., 11.–12.component descriptions 11.–22.CPLD 20.Ethernet interfaces 19.IX bus 17.IXP1200 17.PCI interfaces 18.help iv.humidity 2.Iinstallationbefore you begin 5.ENP-2505 on Windows NT workstation 5.–??ENP-2505 onto Windows NT workstation ??–7.memory 10.policy accelerator 6.process description 3.–9.SODIMMs 10.troubleshooting 9.IX busFBI unit 18.features 17.operating modes 17.ready bus 18.IXF440 Ethernet controllerfeatures 19.41

ENP-2505 Hardware ReferenceS A B C D E F G H I J K L M N O P Q R S T U V W X Y ZIXP1200configuration registers 23.features 17.LLEDs, board 22., 32.LXT972 PHY transceiversdescription 19.Mmemoryflash addresses 35.installation 10.Nnetwork interface specifications 2.notational conventions iv.PPCIconfiguration registers 23.interfacesprimary and secondary 18.secondary bus configuration 19.specifications 2.power 22.PCI-to-PCI bridge (21555)descrpition 19.primary and secondary buses 18.policy accelerator installation 6.powerconsumption specifications 2.PCI 22.processor specifications 2.RRadiSys, contacting iv.ready bus, IX bus 18.SSDRAM, configuration options 10.serial PROM, external contents 25.SODIMMs, installing 10.SODIMMs, qualified 10.specifications 2.SRAM, flash memory 21.static-sensitive devices, handling 3.StrongARM processor 17.support iv.switches, Configuration register 7.System Monitor 6., 7.Ttechnical support iv.temperature 2.terminology 37.–??, 39.–??timing components 21.troubleshootinggeneral iv.post-installation 9.UURLsIntel v.PCI SIG v.RadiSys iv.VVxWorks 6., 7.WWorld-Wide Web URLsIntel v.PCI SIG v.RadiSys iv.42