Intel® Pentium® P6000 and U5000 Mobile Processor Series

Intel® Pentium® P6000 and U5000Mobile Processor SeriesDatasheetThis is volume 1 of 2. Refer to Document 322813 for Volume 2Revision 004January 2011Document Number: 323873-004

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3 Technologies............................................................................................................363.1 Intel Graphics Dynamic Frequency .......................................................................364 Power Management .................................................................................................374.1 ACPI States Supported .......................................................................................374.1.1 System States........................................................................................374.1.2 Processor Core/Package Idle States...........................................................374.1.3 Integrated Memory Controller States .........................................................384.1.4 PCIe Link States .....................................................................................384.1.5 DMI States ............................................................................................384.1.6 Integrated Graphics Controller States ........................................................384.1.7 Interface State Combinations ...................................................................394.2 Processor Core Power Management ......................................................................394.2.1 Enhanced Intel SpeedStep® Technology....................................................404.2.2 Low-Power Idle States.............................................................................404.2.3 Requesting Low-Power Idle States ............................................................424.2.4 Core C-states .........................................................................................434.2.5 Package C-States ...................................................................................444.3 IMC Power Management .....................................................................................474.3.1 Disabling Unused System Memory Outputs.................................................484.3.2 DRAM Power Management and Initialization ...............................................484.4 PCIe Power Management ....................................................................................494.5 DMI Power Management .....................................................................................504.6 Integrated Graphics Power Management ...............................................................504.6.1 Intel ® Display Power Saving Technology 5.0 (Intel ® DPST 5.0).....................504.6.2 Graphics Render C-State .........................................................................504.6.3 Graphics Performance Modulation Technology.............................................504.6.4 Intel ® Smart 2D Display Technology (Intel ® S2DDT)...................................504.7 Thermal Power Management ...............................................................................515 Thermal Management ..............................................................................................525.1 Thermal Design Power and Junction Temperature...................................................525.1.1 Intel Graphics Dynamic Frequency ............................................................525.1.2 Intel Graphics Dynamic Frequency Thermal Design Considerations andSpecifications .........................................................................................535.1.3 Idle Power Specifications .........................................................................555.1.4 Intelligent Power Sharing Control Overview ................................................565.1.5 Component Power Measurement/Estimation Error .......................................575.2 Thermal Management Features............................................................................575.2.1 Processor Core Thermal Features ..............................................................575.2.2 Integrated Graphics and Memory Controller Thermal Features ......................645.2.3 Platform Environment Control Interface (PECI) ...........................................676 Signal Description ....................................................................................................696.1 System Memory Interface ...................................................................................706.2 Memory Reference and Compensation ..................................................................726.3 Reset and Miscellaneous Signals ..........................................................................736.4 PCI Express Graphics Interface Signals .................................................................746.5 Embedded DisplayPort (eDP)...............................................................................756.6 Intel Flexible Display Interface Signals..................................................................756.7 DMI .................................................................................................................766.8 PLL Signals .......................................................................................................766.9 TAP Signals.......................................................................................................774 Datasheet

6.10 Error and Thermal Protection .............................................................................. 786.11 Power Sequencing ............................................................................................. 796.12 Processor Power Signals ..................................................................................... 806.13 Ground and NCTF .............................................................................................. 826.14 Processor Internal Pull Up/Pull Down.................................................................... 827 Electrical Specifications ........................................................................................... 847.1 Power and Ground Pins ...................................................................................... 847.2 Decoupling Guidelines ........................................................................................ 847.2.1 Voltage Rail Decoupling........................................................................... 847.3 Processor Clocking (BCLK, BCLK#) ...................................................................... 847.3.1 PLL Power Supply ................................................................................... 857.4 Voltage Identification (VID) ................................................................................ 857.5 Reserved or Unused Signals................................................................................ 897.6 Signal Groups ................................................................................................... 907.7 Test Access Port (TAP) Connection....................................................................... 927.8 Absolute Maximum and Minimum Ratings ............................................................. 937.9 Storage Conditions Specifications ........................................................................ 937.10 DC Specifications............................................................................................... 947.10.1 Voltage and Current Specifications............................................................ 957.11 Platform Environmental Control Interface (PECI) DC Specifications......................... 1027.11.1 DC Characteristics ................................................................................ 1027.11.2 Input Device Hysteresis......................................................................... 1038 Processor Pin and Signal Information.................................................................... 1048.1 Processor Pin Assignments................................................................................ 1048.2 Package Mechanical Information........................................................................ 178FiguresFigure 1-1 Intel® Pentium® P6000 and U5000 Mobile Processor Series on the CalpellaPlatform................................................................................................ 10Figure 2-2 Intel Flex Memory Technology Operation ................................................... 22Figure 2-3 Dual-Channel Symmetric (Interleaved) and Dual-Channel Asymmetric Modes . 23Figure 2-4 PCI Express Layering Diagram ................................................................. 25Figure 2-5 Packet Flow through the Layers ................................................................ 26Figure 2-6 PCI Express Related Register Structures in the Processor ............................. 27Figure 2-7 Integrated Graphics Controller Unit Block Diagram...................................... 29Figure 2-8 Processor Display Block Diagram .............................................................. 32Figure 4-9 Idle Power Management Breakdown of the Processor Cores.......................... 41Figure 4-10 Thread and Core C-State Entry and Exit .................................................... 41Figure 4-11 Package C-State Entry and Exit ................................................................ 46Figure 5-12 Frequency and Voltage Ordering............................................................... 59Figure 7-13 Active V CC and I CC Loadline (PSI# Asserted) .............................................. 96Figure 7-14 Active V CC and I CC Loadline (PSI# Not Asserted) ........................................ 96Figure 7-15 VAXG/IAXG Static and Ripple Voltage Regulation ........................................ 98Figure 7-16 Input Device Hysteresis......................................................................... 103Figure 8-17 Socket-G (rPGA988A) Pinmap (Top View, Upper-Left Quadrant).................. 105Figure 8-18 Socket-G (rPGA988A) Pinmap (Top View, Upper-Right Quadrant)................ 106Figure 8-19 Socket-G (rPGA988A) Pinmap (Top View, Lower-Left Quadrant).................. 107Figure 8-20 Socket-G (rPGA988A) Pinmap (Top View, Lower-Right Quadrant)................ 108Figure 8-21 BGA1288 Ballmap (Top View, Upper-Left Quadrant) .................................. 137Datasheet 5

Table 7-41 Processor Core (VCC) Active and Idle Mode DC Voltage and CurrentSpecifications......................................................................................... 95Table 7-42 Processor Uncore I/O Buffer Supply DC Voltage and Current Specifications..... 97Table 7-43 Processor Graphics VID based (VAXG) Supply DC Voltage and CurrentSpecifications......................................................................................... 98Table 7-44 DDR3 Signal Group DC Specifications ........................................................ 99Table 7-45 Control Sideband and TAP Signal Group DC Specifications.......................... 100Table 7-46 PCI Express DC Specifications ................................................................ 101Table 7-47 eDP DC Specifications ........................................................................... 102Table 7-48 PECI DC Electrical Limits ....................................................................... 103Table 8-49 rPGA988A Processor Pin List by Pin Number ............................................. 109Table 8-50 rPGA988A Processor Pin List by Pin Name ................................................ 123Table 8-51 BGA1288 Processor Ball List by Ball Name ............................................... 141Table 8-52 BGA1288 Processor Ball List by Ball Number ............................................ 159Datasheet 7

Revision HistoryRevisionNumberDescriptionRevision Date001 Initial release May 2010002 Added Pentium P6000 sku information June 2010003 Added Pentium P6100 and P6200 sku information September 2010004 Added Pentium U5600 SKU information January 2011§8 Datasheet

Features Summary1 Features Summary1.1 IntroductionNote:Intel® Pentium® P6000 and U5000 Mobile Processor Series is the next generation of64-bit, multi-core mobile processor built on 32-nanometer process technology. Basedon the low-power/high-performance Nehalem micro-architecture, the processor isdesigned for a two-chip platform as opposed to the traditional three-chip platforms(processor, GMCH, and ICH). The two-chip platform consists of a processor and thePlatform Controller Hub (PCH) and enables higher performance, lower cost, easiervalidation, and improved x-y footprint. The PCH may also be referred to as MobileIntel® 5 Series Chipset (formerly Ibex Peak-M). Intel® Pentium® P6000 and U5000Mobile Processor Series is designed for the Calpella platform and is offered in rPGA988Aand BGA1288 package respectively.Included in this family of processors is Intel® HD graphics and memory controller dieon the same package as the processor core die. This two-chip solution of a processorcore die with an integrated graphics and memory controller die is known as a multi-chippackage (MCP) processor.1. Throughout this document, Intel® Pentium® P6000 and U5000 Mobile ProcessorSeries is referred to as processor.2. Throughout this document, Intel® HD graphics is referred as integrated graphics.3. Integrated graphics and memory controller die is built on 45-nanometer processtechnology4. Intel® Pentium® P6000 and U5000 Mobile Processor Series is not Intel® vProeligibleDatasheet 9

Features SummaryFigure 1-1. Intel® Pentium® P6000 and U5000 Mobile Processor Series on the CalpellaPlatformDual CoreProcessorDiscrete Graphics(PEG)OREmbeddedDisplayPort* (eDP)PCI Express x 1PCI Express* x16ProcessorGPU, MemoryController800/1066 MT/s2 Channels1 SO-DIMM / ChannelDDR3 SO-DIMMsIntel® FlexibleDisplay InterfaceDMI2(x4)Digital Display x 3LVDS Flat PanelIntel®ManagementEngineSerial ATAUSB 2.06 Ports3 Gb/s14 PortsAnalog CRTMobile Intel® 5 Series ChipsetPCHWiMaxDual Channel NANDInterfaceIntel ® HD AudioSMBUS 2.0SPI FlashSPIController Link 1PCIPCIPCI Express*WiFiFWHSuper I/OLPC8 PCI Express* x1Ports(2.5 GT/s)GigabitNetwork ConnectionPECIGPIO10 Datasheet

Features Summary1.2 Processor Feature Details Two execution cores A 32-KB instruction and 32-KB data first-level cache (L1) for each core A 512-KB shared instruction/data second-level cache (L2), 256-KB for each core Up to 3-MB shared instruction/data third-level cache (L3), shared among all cores1.2.1 Supported Technologies Intel® 64 architecture Execute Disable Bit Processor Context Identifier (PCID) (U5000 processor series only)Note:Please refer to the Intel® Pentium® P6000 and U5000 Mobile Processor SeriesSpecification Update for feature support details1.3 Interfaces1.3.1 System Memory Support One or two channels of DDR3 memory with a maximum of one SO-DIMM perchannel Single- and dual-channel memory organization modes Data burst length of eight for all memory organization modes Memory DDR3 data transfer rates of 800 MT/s (SV/ULV) and 1066 MT/s (SV) 64-bit wide channels DDR3 I/O Voltage of 1.5 V Non-ECC, unbuffered DDR3 SO-DIMMs only Theoretical maximum memory bandwidth of: 12.8 GB/s in dual-channel mode assuming DDR3 800 MT/s 1-Gb, and 2-Gb DDR3 DRAM technologies are supported for x8 and x16 devices. Using 2-Gb device technologies, the largest memory capacity possible is 8 GB,assuming dual-channel mode with two x8, double-sided, un-buffered, non-ECC,SO-DIMM memory configuration. Up to 32 simultaneous open pages, 16 per channel (assuming 4 Ranks of 8 BankDevices) Memory organizations: Single-channel modes Dual-channel modes - Intel® Flex Memory Technology:Datasheet 11

Features SummaryDual-channel symmetric (Interleaved)Dual-channel asymmetric Command launch modes of 1n/2n Partial Writes to memory using Data Mask (DM) signals On-Die Termination (ODT) Intel® Fast Memory Access (Intel® FMA): Just-in-Time Command Scheduling Command Overlap Out-of-Order Scheduling1.3.2 PCI Express* The Processor PCI Express ports are fully compliant to the PCI Express BaseSpecification Revision 2.0. One 16-lane PCI Express* port intended for graphics attach. Gen1 (2.5 GT/s) PCI Express* frequency is supported. Gen1 Raw bit-rate on the data pins of 2.5 Gb/s, resulting in a real bandwidth perpair of 250 MB/s given the 8b/10b encoding used to transmit data across thisinterface. This also does not account for packet overhead and link maintenance. Maximum theoretical bandwidth on interface of 4 GB/s in each directionsimultaneously, for an aggregate of 8 GB/s when x16 Gen 1. Hierarchical PCI-compliant configuration mechanism for downstream devices. Traditional PCI style traffic (asynchronous snooped, PCI ordering). PCI Express extended configuration space. The first 256 bytes of configurationspace aliases directly to the PCI compatibility configuration space. The remainingportion of the fixed 4-KB block of memory-mapped space above that (starting at100h) is known as extended configuration space. PCI Express Enhanced Access Mechanism. Accessing the device configuration spacein a flat memory mapped fashion. Automatic discovery, negotiation, and training of link out of reset. Traditional AGP style traffic (asynchronous non-snooped, PCI-X Relaxed ordering). Peer segment destination posted write traffic (no peer-to-peer read traffic) inVirtual Channel 0: DMI -> PCI Express Port 0 64-bit downstream address format, but the processor never generates an addressabove 64 GB (Bits 63:36 will always be zeros). 64-bit upstream address format, but the processor responds to upstream readtransactions to addresses above 64 GB (addresses where any of Bits 63:36 are12 Datasheet

Features Summarynon-zero) with an Unsupported Request response. Upstream write transactions toaddresses above 64 GB will be dropped. Re-issues configuration cycles that have been previously completed with theConfiguration Retry status. PCI Express reference clock is 100-MHz differential clock buffered out of systemclock generator. Power Management Event (PME) functions. Static lane numbering reversal Does not support dynamic lane reversal, as defined (optional) by the PCIExpress Base Specification. PCI Express 1x16 configurationNormal (1x16): PEG_RX[15:0]; PEG_TX[15:0]Reversal (1x16): PEG_RX[0:15]; PEG_TX[0:15] Supports Half Swing low-power/low-voltage mode. Message Signaled Interrupt (MSI and MSI-X) messages PEG Lanes shared with Embedded DisplayPort* (see eDP, Section 1.3.6). Polarity inversion1.3.3 Direct Media Interface (DMI) Compliant to Direct Media Interface second generation (DMI2). Four lanes in each direction. 2.5 GT/s point-to-point DMI interface to PCH is supported. Raw bit-rate on the data pins of 2.5 Gb/s, resulting in a real bandwidth per pair of250 MB/s given the 8b/10b encoding used to transmit data across this interface.Does not account for packet overhead and link maintenance. Maximum theoretical bandwidth on interface of 1 GB/s in each directionsimultaneously, for an aggregate of 2 GB/s when DMI x4. Shares 100-MHz PCI Express reference clock. 64-bit downstream address format, but the processor never generates an addressabove 64 GB (Bits 63:36 will always be zeros). 64-bit upstream address format, but the processor responds to upstream readtransactions to addresses above 64 GB (addresses where any of Bits 63:36 arenonzero) with an Unsupported Request response. Upstream write transactions toaddresses above 64 GB will be dropped. Supports the following traffic types to or from the PCH: DMI -> PCI Express Port 0 write traffic DMI -> DRAM DMI -> processor core (Virtual Legacy Wires (VLWs), Resetwarn, or MSIs only)Datasheet 13

Features Summary Processor core -> DMI APIC and MSI interrupt messaging support: Message Signaled Interrupt (MSI and MSI-X) messages Downstream SMI, SCI and SERR error indication. Legacy support for ISA regime protocol (PHOLD/PHOLDA) required for parallel portDMA, floppy drive, and LPC bus masters. DC coupling no capacitors between the processor and the PCH. Polarity inversion. PCH end-to-end lane reversal across the link. Supports Half Swing low-power/low-voltage.1.3.4 Platform Environment Control Interface (PECI)The PECI is a one-wire interface that provides a communication channel between aPECI client (the processor) and a PECI master (the PCH).1.3.5 Intel® HD Graphics Controller The integrated graphics controller contains a refresh of the fifth generation graphicscore Intel® Dynamic Video Memory Technology (Intel® DVMT) support Intel® Graphics Performance Modulation Technology (Intel® GPMT) Intel® Smart 2D Display Technology (Intel® S2DDT) Intel® Clear Video Technology MPEG2 Hardware Acceleration WMV9/VC1 Hardware Acceleration AVC Hardware Acceleration ProcAmp Advanced Pixel Adaptive De-interlacing Sharpness Enhancement De-noise Filter High Quality Scaling Film Mode Detection (3:2 pull-down) and Correction Intel® TV Wizard 12 EUs Dedicated analog and digital display ports are supported through the Intel 5 SeriesChipset PCH14 Datasheet

Features Summary1.3.6 Embedded DisplayPort* (eDP*) Shared with PCI Express Graphics port Shared on upper four logical lanes, after any lane reversal eDP[3:0] map to PEG[12:15] (non-reversed) eDP[3:0] map to PEG[3:0] (reversed) Concurrent eDP and PEG x1 supported1.3.7 Intel® Flexible Display Interface (Intel® FDI) Carries display traffic from the integrated graphics controller in the processor to thelegacy display connectors in the PCH. Based on DisplayPort standard. Two independent links - one for each display pipe. Four unidirectional downstream differential transmitter pairs: Scalable down to 3X, 2X, or 1X based on actual display bandwidth requirements Fixed frequency 2.7 GT/s data rate Two sideband signals for Display synchronization: FDI_FSYNC and FDI_LSYNC (Frame and Line Synchronization) One Interrupt signal used for various interrupts from the PCH: FDI_INT signal shared by both Intel FDI Links PCH supports end-to-end lane reversal across both links.1.4 Power Management Support1.4.1 Processor Core Full support of ACPI C-states as implemented by the following processor C-states: Ultra low voltage supports C0, C1, C1E, C3, C6 Standard voltage supports C0, C1, C1E, C3 Enhanced Intel SpeedStep® Technology1.4.2 System S0, S3, S4, S5Datasheet 15

Features Summary1.4.3 Memory Controller Conditional self-refresh (Intel® Rapid Memory Power Management (Intel® RMPM)) Dynamic power-down1.4.4 PCI Express* L0s and L1 ASPM power management capability1.4.5 DMI L0s and L1 ASPM power management capability1.4.6 Integrated Graphics Controller Intel Smart 2D Display Technology (Intel S2DDT) Intel® Display Power Saving Technology (Intel® DPST) Graphics Render C-State (RC6)1.5 Thermal Management Support Digital Thermal Sensor Adaptive Thermal Monitor THERMTRIP# and PROCHOT# support On-Demand Mode Open and Closed Loop Throttling Memory Thermal Throttling External Thermal Sensor (TS-on-DIMM and TS-on-Board) Render Thermal Throttling Fan speed control with DTS1.6 Package The Intel® Pentium® P6000 and U5000 Mobile Processor Series is available isavailable on: A 37.5 x 37.5 mm rPGA package (rPGA988A) (Standard Voltage only) A 34 x 28 mm BGA package (BGA1288) (Ultra Low voltage only)16 Datasheet

Features Summary1.7 TerminologyBLTTermDeep Power DownTechnologyCRTDDR3DPDMADMIDTSECCeDP*Intel® DPSTEnhanced IntelSpeedStep®TechnologyExecute Disable Bit(G)MCHGPUICHIMCIntel® 64 TechnologyITPMIOVLCDLVDSMCPNCTFBlock Level TransferDescriptionCode named as C6 state throughout the documentCathode Ray TubeThird-generation Double Data Rate SDRAM memory technologyDisplayPort*Direct Memory AccessDirect Media InterfaceDigital Thermal SensorError Correction CodeEmbedded DisplayPort*Intel ® Display Power Saving TechnologyTechnology that provides power management capabilities to laptops.The Execute Disable bit allows memory to be marked as executable ornon-executable, when combined with a supporting operating system.If code attempts to run in non-executable memory the processorraises an error to the operating system. This feature can prevent someclasses of viruses or worms that exploit buffer overrun vulnerabilitiesand can thus help improve the overall security of the system. See theIntel® 64 and IA-32 Architectures Software Developer's Manuals formore detailed information.Legacy component - Graphics Memory Controller HubGraphics Processing UnitThe legacy I/O Controller Hub component that contains the main PCIinterface, LPC interface, USB2, Serial ATA, and other I/O functions. Itcommunicates with the legacy (G)MCH over a proprietary interconnectcalled DMI.Integrated Memory Controller64-bit memory extensions to the IA-32 architectureIntegrated Trusted Platform ModuleI/O VirtualizationLiquid Crystal DisplayLow Voltage Differential Signaling. A high speed, low power datatransmission standard used for display connections to LCD panels.Multi-Chip Package.Non-Critical to Function. NCTF locations are typically redundantground or non-critical reserved, so the loss of the solder jointcontinuity at end of life conditions will not affect the overall productfunctionality.Datasheet 17

Features SummaryTermNehalemPCHPECIPEGProcessorProcessor CoreRankSCIStorage ConditionsTACTDPV CCV SSV AXGV TTV DDQVLDx1x4x8x16Intels 45-nm processor design, follow-on to the 45-nm Penryn design.Platform Controller Hub. The new, 2009 chipset with centralizedplatform capabilities including the main I/O interfaces along withdisplay connectivity, audio features, power management,manageability, security and storage features. The PCH may also bereferred to using the name (Mobile) Intel® 5 Series ChipsetPlatform Environment Control Interface.PCI Express* Graphics. External Graphics using PCI ExpressArchitecture. A high-speed serial interface whose configuration issoftware compatible with the existing PCI specifications.The 64-bit, single-core or multi-core component (package).The term processor core refers to Si die itself which can containmultiple execution cores. Each execution core has an instructioncache, data cache, and 256-KB L2 cache. All execution cores share theL3 cache.A unit of DRAM corresponding four to eight devices in parallel, ignoringECC. These devices are usually, but not always, mounted on a singleside of a SO-DIMM.System Control Interrupt. Used in ACPI protocol.A non-operational state. The processor may be installed in a platform,in a tray, or loose. Processors may be sealed in packaging or exposedto free air. Under these conditions, processor landings should not beconnected to any supply voltages, have any I/Os biased or receive anyclocks. Upon exposure to free air (i.e., unsealed packaging or adevice removed from packaging material) the processor must behandled in accordance with moisture sensitivity labeling (MSL) asindicated on the packaging material.Thermal Averaging Constant.Thermal Design Power.Processor core power supply.Processor ground.Graphics core power supply.L3 shared cache, memory controller, and processor I/O power rail.DDR3 power rail.Variable Length Decoding.DescriptionRefers to a Link or Port with one Physical Lane.Refers to a Link or Port with four Physical Lanes.Refers to a Link or Port with eight Physical Lanes.Refers to a Link or Port with sixteen Physical Lanes.18 Datasheet

Features Summary1.8 Related DocumentsDocumentDocument Number/LocationPublic SpecificationsAdvanced Configuration and Power Interface Specification 3.0PCI Local Bus Specification 3.0PCI Express Base Specification 2.0DDR3 SDRAM SpecificationDisplayPort SpecificationIntel® 64 and IA-32 Architectures Software Developer's ManualsVolume 1: Basic Architecture 253665Volume 2A: Instruction Set Reference, A-M 253666Volume 2B: Instruction Set Reference, N-Z 253667Volume 3A: System Programming Guide 253668Volume 3B: System Programming Guide 253669§http://www.acpi.info/http://www.pcisig.com/specificationshttp://www.pcisig.comhttp://www.jedec.orghttp://www.vesa.orghttp://www.intel.com/products/processor/manuals/index.htmDatasheet 19

Interfaces2 InterfacesThis chapter describes the interfaces supported by the processor.2.1 System Memory Interface2.1.1 System Memory Technology SupportedThe Integrated Memory Controller (IMC) supports DDR3 protocols with two,independent, 64-bit wide channels each accessing one SO-DIMM. It supports amaximum of one, unbuffered non-ECC DDR3 SO-DIMM per-channel thus allowing up totwo device ranks per-channel.DDR3 Data Transfer Rates: 800 MT/s (PC3-6400) and 1066 MT/s (PC3-8500) DDR3 SO-DIMM Modules: Raw Card A double-sided x16 unbuffered non-ECC Raw Card B single-sided x8 unbuffered non-ECC Raw Card C single-sided x16 unbuffered non-ECC Raw Card D double-sided x8 (stacked) unbuffered non-ECC Raw Card F double-sided x8 (planar) unbuffered non-ECC DDR3 DRAM Device Technology: Standard 1-Gb, and 2-Gb technologies and addressing are supported for x16and x8 devices. There is no support for memory modules with differenttechnologies or capacities on opposite sides of the same memory module. If oneside of a memory module is populated, the other side is either identical orempty.Table 2-1. Supported SO-DIMM Module Configurations 1RawCardVersionDIMMCapacityDRAMDeviceTechnologyDRAMOrganization# ofDRAMDevices# ofPhysicalDeviceRanks# of Row/ColAddressBits# ofBanksInsideDRAMPageSizeA 1 GB 1 Gb 64 M x 16 8 2 13/10 8 8KA 2 GB 2 Gb 128 M x 16 8 2 14/10 8 8KB 1 GB 1 Gb 128 M x 8 8 1 14/10 8 8KB 2 GB 2 Gb 256 M x 8 8 1 15/10 8 8KC 512 MB 1 Gb 64 M x 16 4 1 13/10 8 8KC 1 GB 2 Gb 128 M x 16 4 1 14/10 8 8K20 Datasheet

InterfacesTable 2-1. Supported SO-DIMM Module Configurations 1RawCardVersionDIMMCapacityDRAMDeviceTechnologyDRAMOrganization# ofDRAMDevices# ofPhysicalDeviceRanks# of Row/ColAddressBits# ofBanksInsideDRAMPageSizeD 2 4 GB 2 Gb 256 M x 8 16 2 15/10 8 8KF 2 GB 1 Gb 128 M x 8 16 2 14/10 8 8KF 4 GB 2 Gb 256 M x 8 16 2 15/10 8 8KNOTES:1. System memory configurations are based on availability and are subject to change.2. Only Raw Card D SO-DIMMs at 1066 MT/s are supported.2.1.2 System Memory Timing SupportThe IMC supports the following DDR3 Speed Bin, CAS Write Latency (CWL), andcommand signal mode timings on the main memory interface: tCL = CAS Latency tRCD = Activate Command to READ or WRITE Command delay tRP = PRECHARGE Command Period CWL = CAS Write Latency Command Signal modes = 1n indicates a new command may be issued every clockand 2n indicates a new command may be issued every 2 clocks. Command launchmode programming depends on the transfer rate and memory configuration.Table 2-2. DDR3 System Memory Timing SupportTransferRate(MT/s)tCL(tCK)tRCD(tCK)tRP(tCK)CWL(tCK)CMD ModeNotes800 6 6 6 5 1n 11066 7 7 7 6 1n 18 8 8NOTES:1. System memory timing support is based on availability and is subject to change.2.1.3 System Memory Organization ModesThe IMC supports two memory organization modes, single-channel and dual-channel.Depending upon how the SO-DIMM Modules are populated in each memory channel, anumber of different configurations can exist.Datasheet 21

Interfaces2.1.3.1 Single-Channel ModeIn this mode, all memory cycles are directed to a single-channel. Single-channel modeis used when either Channel A or Channel B SO-DIMM connectors are populated in anyorder, but not both.2.1.3.2 Dual-Channel Mode - Intel® Flex Memory Technology ModeThe IMC supports Intel Flex Memory Technology Mode. This mode combines theadvantages of the Dual-Channel Symmetric (Interleaved) and Dual-ChannelAsymmetric Modes. Memory is divided into a symmetric and a asymmetric zone. Thesymmetric zone starts at the lowest address in each channel and is contiguous until theasymmetric zone begins or until the top address of the channel with the smallercapacity is reached. In this mode, the system runs with one zone of dual-channel modeand one zone of single-channel mode, simultaneously, across the whole memory array.Figure 2-2. Intel Flex Memory Technology OperationCT O MBBCN o n in te rle a v e da c c e s sC H AC H BBCD u a l c h a n n e lin te rle a v e d a c c e s sBBBC H AC H BB – T h e la rg e s t p h y s ic a l m e m o ry a m o u n t o f th e s m a lle r s iz e m e m o ry m o d u leC – T h e re m a in in g p h y s ic a l m e m o ry a m o u n t o f th e la rg e r s iz e m e m o ry m o d u le2.1.3.2.1 Dual-Channel Symmetric ModeDual-Channel Symmetric mode, also known as interleaved mode, provides maximumperformance on real world applications. Addresses are ping-ponged between thechannels after each cache line (64-byte boundary). If there are two requests, and thesecond request is to an address on the opposite channel from the first, that request canbe sent before data from the first request has returned. If two consecutive cache linesare requested, both may be retrieved simultaneously, since they are ensured to be onopposite channels. Use Dual-Channel Symmetric mode when both Channel A andChannel B SO-DIMM connectors are populated in any order, with the total amount ofmemory in each channel being the same.22 Datasheet

InterfacesWhen both channels are populated with the same memory capacity and the boundarybetween the dual channel zone and the single channel zone is the top of memory, IMCoperates completely in Dual-Channel Symmetric mode.Note:The DRAM device technology and width may vary from one channel to the other.2.1.3.2.2 Dual-Channel Asymmetric ModeThis mode trades performance for system design flexibility. Unlike the previous mode,addresses start at the bottom of Channel A and stay there until the end of the highestrank in Channel A, and then addresses continue from the bottom of Channel B to thetop. Real world applications are unlikely to make requests that alternate betweenaddresses that sit on opposite channels with this memory organization, so in mostcases, bandwidth is limited to a single channel.This mode is used when Intel Flex Memory Technology is disabled and both Channel Aand Channel B SO-DIMM connectors are populated in any order with the total amountof memory in each channel being different.Figure 2-3. Dual-Channel Symmetric (Interleaved) and Dual-Channel Asymmetric ModesDual Channel Interleaved(memory sizes must match)Dual Channel Asymmetric(memory sizes can differ)CLCH. BTop ofMemoryCLCH. BTop ofMemoryCH. ACH. ACH.A-topDRBCH. BCH. ACH. BCH. A002.1.4 Rules for Populating Memory SlotsIn all modes, the frequency of system memory is the lowest frequency of all memorymodules placed in the system, as determined through the SPD registers on thememory modules. The system memory controller supports only one SO-DIMMDatasheet 23

Interfacesconnector per channel. For dual-channel modes both channels must have an SO-DIMMconnector populated. For single-channel mode, only a single-channel can have anSO-DIMM connector populated.2.1.5 Technology Enhancements of Intel ® Fast Memory Access(Intel ® FMA)The following sections describe the Just-in-Time Scheduling, Command Overlap, andOut-of-Order Scheduling Intel FMA technology enhancements.2.1.5.1 Just-in-Time Command SchedulingThe memory controller has an advanced command scheduler where all pendingrequests are examined simultaneously to determine the most efficient request to beissued next. The most efficient request is picked from all pending requests and issuedto system memory Just-in-Time to make optimal use of Command Overlapping. Thus,instead of having all memory access requests go individually through an arbitrationmechanism forcing requests to be executed one at a time, they can be started withoutinterfering with the current request allowing for concurrent issuing of requests. Thisallows for optimized bandwidth and reduced latency while maintaining appropriatecommand spacing to meet system memory protocol.2.1.5.2 Command OverlapCommand Overlap allows the insertion of the DRAM commands between the Activate,Precharge, and Read/Write commands normally used, as long as the insertedcommands do not affect the currently executing command. Multiple commands can beissued in an overlapping manner, increasing the efficiency of system memory protocol.2.1.5.3 Out-of-Order SchedulingWhile leveraging the Just-in-Time Scheduling and Command Overlap enhancements,the IMC continuously monitors pending requests to system memory for the best use ofbandwidth and reduction of latency. If there are multiple requests to the same openpage, these requests would be launched in a back to back manner to make optimumuse of the open memory page. This ability to reorder requests on the fly allows the IMCto further reduce latency and increase bandwidth efficiency.2.1.6 DRAM Clock GenerationEvery supported SO-DIMM has two differential clock pairs. There are total of four clockpairs driven directly by the processor to two SO-DIMMs.2.1.7 System Memory Pre-Charge Power Down Support DetailsThe IMC supports and enables slow exit DDR3 DRAM Device pre-charge power downDLL control. During a pre-charge power down, a slow exit is where the DRAM deviceDLL is disabled after entering pre-charge power down for potential power savings.24 Datasheet

Interfaces2.2 PCI Express InterfaceThis section describes the PCI Express interface capabilities of the processor. See thePCI Express Base Specification for details of PCI Express.The processor has one PCI Express controller that can support one external x16 PCIExpress Graphics Device or two external x8 PCI Express Graphics Devices. The primaryPCI Express Graphics port is referred to as PEG 0 and the secondary PCI ExpressGraphics port is referred to as PEG 1.2.2.1 PCI Express ArchitectureCompatibility with the PCI addressing model is maintained to ensure that all existingapplications and drivers operate unchanged.The PCI Express configuration uses standard mechanisms as defined in the PCIPlug-and-Play specification. The initial recovered clock speed of 1.25 GHz results in2.5 Gb/s/direction which provides a 250 MB/s communications channel in eachdirection (500 MB/s total). That is close to twice the data rate of classic PCI. The factthat 8b/10b encoding is used accounts for the 250 MB/s where quick calculations wouldimply 300 MB/s.The PCI Express architecture is specified in three layers: Transaction Layer, Data LinkLayer, and Physical Layer. The partitioning in the component is not necessarily alongthese same boundaries. Refer to Figure 2-4 for the PCI Express Layering Diagram.Figure 2-4. PCI Express Layering DiagramPCI Express uses packets to communicate information between components. Packetsare formed in the Transaction and Data Link Layers to carry the information from thetransmitting component to the receiving component. As the transmitted packets flowthrough the other layers, they are extended with additional information necessary tohandle packets at those layers. At the receiving side, the reverse process occurs andDatasheet 25

Interfacespackets get transformed from their Physical Layer representation to the Data LinkLayer representation and finally (for Transaction Layer Packets) to the form that can beprocessed by the Transaction Layer of the receiving device.Figure 2-5. Packet Flow through the Layers2.2.1.1 Transaction LayerThe upper layer of the PCI Express architecture is the Transaction Layer. TheTransaction Layer's primary responsibility is the assembly and disassembly ofTransaction Layer Packets (TLPs). TLPs are used to communicate transactions, such asread and write, as well as certain types of events. The Transaction Layer also managesflow control of TLPs.2.2.1.2 Data Link LayerThe middle layer in the PCI Express stack, the Data Link Layer, serves as anintermediate stage between the Transaction Layer and the Physical Layer.Responsibilities of Data Link Layer include link management, error detection, and errorcorrection.The transmission side of the Data Link Layer accepts TLPs assembled by theTransaction Layer, calculates and applies data protection code and TLP sequencenumber, and submits them to Physical Layer for transmission across the Link. Thereceiving Data Link Layer is responsible for checking the integrity of received TLPs andfor submitting them to the Transaction Layer for further processing. On detection of TLPerror(s), this layer is responsible for requesting retransmission of TLPs until informationis correctly received, or the Link is determined to have failed. The Data Link Layer alsogenerates and consumes packets which are used for Link management functions.2.2.1.3 Physical LayerThe Physical Layer includes all circuitry for interface operation, including driver andinput buffers, parallel-to-serial and serial-to-parallel conversion, PLL(s), and impedancematching circuitry. It also includes logical functions related to interface initialization andmaintenance. The Physical Layer exchanges data with the Data Link Layer in animplementation-specific format, and is responsible for converting this to an appropriateserialized format and transmitting it across the PCI Express Link at a frequency andwidth compatible with the remote device.26 Datasheet

Interfaces2.2.2 PCI Express Configuration MechanismThe PCI Express (external graphics) link is mapped through a PCI-to-PCI bridgestructure.Figure 2-6. PCI Express Related Register Structures in the ProcessorPCIExpressDevicePEG0PCI-PCIBridgerepresentingroot PCIExpress port(Device 1)PCICompatibleHost BridgeDevice(Device 0)DMIPCI Express extends the configuration space to 4096 bytes per-device/function, ascompared to 256 bytes allowed by the Conventional PCI Specification. PCI Expressconfiguration space is divided into a PCI-compatible region (which consists of the first256 bytes of a logical device's configuration space) and an extended PCI Express region(which consists of the remaining configuration space). The PCI-compatible region canbe accessed using either the mechanisms defined in the PCI specification or using theenhanced PCI Express configuration access mechanism described in the PCI ExpressEnhanced Configuration Mechanism section.The PCI Express Host Bridge is required to translate the memory-mapped PCI Expressconfiguration space accesses from the host processor to PCI Express configurationcycles. To maintain compatibility with PCI configuration addressing mechanisms, it isrecommended that system software access the enhanced configuration space using32-bit operations (32-bit aligned) only. See the PCI Express Base Specification fordetails of both the PCI-compatible and PCI Express Enhanced configurationmechanisms and transaction rules.2.2.3 PCI Express Ports and BifurcationThe external graphics attach (PEG) on the processor is a single, 16-lane (x16) port thatcan be: configured at narrower widths bifurcated into two x8 PCI Express ports that may train to narrower widthsThe PEG port is being designed to be compliant with the PCI Express BaseSpecification, Revision 2.0.Datasheet 27

Interfaces2.2.3.1 PCI Express Bifurcated ModeWhen bifurcated, the signals which had previously been assigned to Lanes 15:8 of thesingle x16 Primary port are reassigned to lanes 7:0 of the x8 Secondary Port. Thisassignment applies whether the lane numbering is reversed or not. PCI Express Port 0is mapped to PCI Device 1 and PCI Express Port 1 is mapped to PCI Device 6.2.2.3.2 Static Lane Numbering ReversalDoes not support dynamic lane reversal, as defined (optional) by the PCI Express BaseSpecification.PCI Express 1x16 configuration: Normal (1x16): PEG_RX[15:0]; PEG_TX[15:0] Reversal (1x16): PEG_RX[0:15]; PEG_TX[0:15]2.3 DMIDMI connects the processor and the PCH chip-to-chip. DMI2 is supported. The DMI issimilar to a four-lane PCI Express supporting up to 1 GB/s of bandwidth in eachdirection.Note:Only DMI x4 configuration is supported.2.3.1 DMI Error FlowDMI can only generate SERR in response to errors, never SCI, SMI, MSI, PCI INT, orGPE. Any DMI related SERR activity is associated with Device 0.2.3.2 Processor/PCH Compatibility AssumptionsThe processor is compatible with the PCH and is not compatible with any previous(G)MCH or ICH products.2.3.3 DMI Link DownThe DMI link going down is a fatal, unrecoverable error. If the DMI data link goes todata link down, after the link was up, then the DMI link hangs the system by notallowing the link to retrain to prevent data corruption. This is controlled by the PCH.Downstream transactions that had been successfully transmitted across the link priorto the link going down may be processed as normal. No completions from downstream,non-posted transactions are returned upstream over the DMI link after a link downevent.28 Datasheet

Interfaces2.4 Intel® HD Graphics ControllerThis section details the 2D, 3D and video pipeline and their respective capabilities.The integrated graphics is powered by a refresh of the fifth generation graphics coreand supports twelve, fully-programmable execution cores. Full-precision, floating-pointoperations are supported to enhance the visual experience of compute-intensiveapplications.The integrated graphics controller contains several types of components;the graphics engines, planes, pipes, port and the Intel FDI. The integrated graphics hasa 3D/2D Instruction Processing unit to control the 3D and 2D engines respectively. Theintegrated graphics controllers 3D and 2D engines are fed with data through the IMC.The outputs of the graphics engine are surfaces sent to memory, which are thenretrieved and processed by the planes. The surfaces are then blended in the pipes andthe display timings are transitioned from display core clock to the pixel (dot) clock.Figure 2-7. Integrated Graphics Controller Unit Block DiagramVideo EnginePlane AeDPSprite A2D Engine3D EngineVertex Fetch/VertexShaderGeometry ShaderClipperMemoryCursor AVGAPlane BSprite BAlphaBlend/Gamma/PanelFitterPipe APipe BMUXIntel®FDIStrip & Fan/SetupWindower/IZCursor B2.4.1 3D and Video Engines for Graphics ProcessingThe 3D graphics pipeline architecture simultaneously operates on different primitives oron different portions of the same primitive. All the cores are fully programmable,increasing the versatility of the 3D Engine. The Gen 5.75 3D engine provides thefollowing performance and power-management enhancements: Execution units (EUs) increased to 12 from the previous 10 EUsin Gen 5.0. Includes Hierarchal-Z Includes video quality enhancements2.4.1.1 3D Engine Execution Units Support 12 EUs. The EUs perform 128-bit wide execution per clock.Datasheet 29

Interfaces2.4.1.2 3D Pipeline Support SIMD8 instructions for vertex processing and SIMD16 instructions for pixelprocessing.2.4.1.2.1 Vertex Fetch (VF) StageThe VF stage executes 3DPRIMITIVE commands. Some enhancements have beenincluded to better support legacy D3D APIs as well as SGI OpenGL*.2.4.1.2.2 Vertex Shader (VS) StageThe VS stage performs shading of vertices output by the VF function. The VS unitproduces an output vertex reference for every input vertex reference received from theVF unit, in the order received.2.4.1.2.3 Geometry Shader (GS) StageThe GS stage receives inputs from the VS stage. Compiled application-provided GSprograms, specifying an algorithm to convert the vertices of an input object into someoutput primitives. For example, a GS shader may convert lines of a line strip intopolygons representing a corresponding segment of a blade of grass centered on theline. Or it could use adjacency information to detect silhouette edges of triangles andoutput polygons extruding out from the edges.2.4.1.2.4 Clip StageThe Clip stage performs general processing on incoming 3D objects. However, it alsoincludes specialized logic to perform a Clip Test function on incoming objects. The ClipTest optimizes generalized 3D Clipping. The Clip unit examines the position of incomingvertices, and accepts/rejects 3D objects based on its Clip algorithm.2.4.1.2.5 Strips and Fans (SF) StageThe SF stage performs setup operations required to rasterize 3D objects. The outputsfrom the SF stage to the Windower stage contain implementation-specific informationrequired for the rasterization of objects and also supports clipping of primitives to someextent.2.4.1.2.6 Windower/IZ (WIZ) StageThe WIZ unit performs an early depth test, which removes failing pixels and eliminatesunnecessary processing overhead.The Windower uses the parameters provided by the SF unit in the object-specificrasterization algorithms. The WIZ unit rasterizes objects into the corresponding set ofpixels. The Windower is also capable of performing dithering, whereby the illusion of ahigher resolution when using low-bpp channels in color buffers is possible. Colordithering diffuses the sharp color bands seen on smooth-shaded objects.30 Datasheet

Interfaces2.4.1.3 Video Engine2.4.1.4 2D EngineThe Video Engine handles the non-3D (media/video) applications. It includes supportfor VLD and MPEG2 decode in hardware.The 2D Engine contains BLT (Block Level Transfer) functionality and an extensive set of2D instructions. To take advantage of the 3D during engines functionality, some BLTfunctions make use of the 3D renderer.2.4.1.4.1 Integrated Graphics VGA RegistersThe 2D registers consists of original VGA registers and others to support graphicsmodes that have color depths, resolutions, and hardware acceleration features that gobeyond the original VGA standard.2.4.1.4.2 Logical 128-Bit Fixed BLT and 256 Fill EngineThis BLT engine accelerates the GUI of Microsoft Windows* operating systems. The128-bit BLT engine provides hardware acceleration of block transfers of pixel data formany common Windows operations. The BLT engine can be used for the following: Move rectangular blocks of data between memory locations Data alignment To perform logical operations (raster ops)The rectangular block of data does not change, as it is transferred between memorylocations. The allowable memory transfers are between: cacheable system memoryand frame buffer memory, frame buffer memory and frame buffer memory, and withinsystem memory. Data to be transferred can consist of regions of memory, patterns, orsolid color fills. A pattern is always 8 x 8 pixels wide and may be 8, 16, or 32 bits perpixel.The BLT engine expands monochrome data into a color depth of 8, 16, or 32 bits. BLTscan be either opaque or transparent. Opaque transfers move the data specified to thedestination. Transparent transfers compare destination color to source color and writeaccording to the mode of transparency selected.Data is horizontally and vertically aligned at the destination. If the destination for theBLT overlaps with the source memory location, the BLT engine specifies which area inmemory to begin the BLT transfer. Hardware is included for all 256 raster operations(source, pattern, and destination) defined by Microsoft, including transparent BLT.The BLT engine has instructions to invoke BLT and stretch BLT operations, permittingsoftware to set up instruction buffers and use batch processing. The BLT engine canperform hardware clipping during BLTs.Datasheet 31

Interfaces2.4.2 Integrated Graphics Display PipesThe integrated graphics controller display pipe can be broken down into threecomponents: Display Planes Display Pipes Embedded DisplayPort and Intel FDIFigure 2-8. Processor Display Block DiagramPlane AeDPSprite ACursor AVGAPlane BAlphaBlend/Gamma/PanelFitterPipe AMUXIntel®FDISprite BPipe BCursor B2.4.2.1 Display PlanesA display plane is a single displayed surface in memory and contains one image(desktop, cursor, overlay). It is the portion of the display HW logic that defines theformat and location of a rectangular region of memory that can be displayed on displayoutput device and delivers that data to a display pipe. This is clocked by the CoreDisplay Clock.2.4.2.1.1 Planes A and BPlanes A and B are the main display planes and are associated with Pipes A and Brespectively. The two display pipes are independent, allowing for support of twoindependent display streams. They are both double-buffered, which minimizes latencyand improves visual quality.2.4.2.1.2 Sprite A and BSprite A and Sprite B are planes optimized for video decode, and are associated withPlanes A and B respectively. Sprite A and B are also double-buffered.32 Datasheet

Interfaces2.4.2.1.3 Cursors A and BCursors A and B are small, fixed-sized planes dedicated for mouse cursor acceleration,and are associated with Planes A and B respectively. These planes support resolutionsup to 256 x 256 each.2.4.2.1.4 VGAUsed for boot, safe mode, legacy games, etc. Can be changed by an application withoutOS/driver notification, due to legacy requirements.2.4.2.2 Display PipesThe display pipe blends and synchronizes pixel data received from one or more displayplanes and adds the timing of the display output device upon which the image isdisplayed. This is clocked by the Display Reference clock inputs.The display pipes A and B operate independently of each other at the rate of 1 pixel perclock. They can attach to any of the display ports. Each pipe sends display data to thePCH over the Intel Flexible Display Interface (Intel FDI).2.4.2.3 Display PortsThe display ports consist of output logic and pins that transmit the display data to theassociated encoding logic and send the data to the display device (i.e., LVDS, HDMI,DVI, SDVO, etc.). All display interfaces connecting external displays are nowrepartitioned and driven from the PCH with the exception of the eDP DisplayPort.2.4.2.4 Embedded DisplayPort (eDP)The DisplayPort abbreviated as DP (different than the generic term display port)specification is a VESA standard. DisplayPort consolidates internal and externalconnection methods to reduce device complexity, support cross industry applications,and provide performance scalability. The integrated graphics supports an embeddedDisplayPort (eDP) interface for display devices that are integrated into the system(e.g., laptop LCD panel). All other display interfaces connecting to the LVDS or externalpanels are driven from the PCH.The eDP interface is physically shared with a subset of the PCIe interface. Specifically,eDP[3:0] map to Logical Lanes PEG[12:15] of the PCIe interface. Mapping for reversedcase is: eDP[3:0] maps to PEG[3:0], ex: eDP[0]=PEG[15] in non reversed case. Inreversed case: eDP[0] = PEG[0].Table 2-3. eDP/PEG Ball MappingeDP Signal PEG Signal Lane ReversaleDP_AUX PEG_RX[13] PEG_RX[2]eDP_AUX# PEG_RX#[13] PEG_RX#[2]eDP_HPD# PEG_RX[12] PEG_RX[3]Datasheet 33

InterfacesTable 2-3. eDP/PEG Ball MappingeDP Signal PEG Signal Lane ReversaleDP_TX[0] PEG_TX[15] PEG_TX[0]eDP_TX#[0] PEG_TX#[15] PEG_TX#[0]eDP_TX[1] PEG_TX[14] PEG_TX[1]eDP_TX#[1] PEG_TX#[14] PEG_TX#[1]eDP_TX[2] PEG_TX[13] PEG_TX[2]eDP_TX#[2] PEG_TX#[13] PEG_TX#[2]eDP_TX[3] PEG_TX[12] PEG_TX[3]eDP_TX#[3] PEG_TX#[12] PEG_TX#[3]When eDP is enabled, the lower logical lanes are still available for standard PCIedevices, using the PEG 0 controller. PEG 0 is limited to x1. The board manufacturechooses whether to use eDP and whether to use lane numbering reversal.The eDP interface supports link-speeds of 1.62 Gbps and 2.7 Gbps on 1, 2 or 4 datalanes. The eDP and PCI Express x1 may be supported concurrently. eDP interface maysupport -0.5% SSC and non-SSC clock settings.2.4.3 Intel Flexible Display InterfaceThe Intel Flexible Display Interface (Intel FDI) is a proprietary link for carrying displaytraffic from the integrated graphics controller to the PCH display I/Os. Intel FDIsupports two independent channels; one for pipe A and one for pipe B. Each channel has four transmit (Tx) differential pairs used for transporting pixeland framing data from the display engine. Each channel has one single-ended LineSync and one FrameSync input (1-V CMOSsignaling). One display interrupt line input (1-V CMOS signaling). Intel FDI may dynamically scalable down to 2X or 1X based on actual displaybandwidth requirements. Common 100-MHz reference clock is sent to both processor and PCH. Each channel transports at a rate of 2.7 Gbps. PCH supports end-to-end lane reversal across both channels (no reversal supportrequired)2.5 Platform Environment Control Interface (PECI)The PECI is a one-wire interface that provides a communication channel between aPECI client (processor) and a PECI master, usually the PCH. The processor implementsa PECI interface to:34 Datasheet

Interfaces Allow communication of processor thermal and other information to the PECImaster. Read averaged Digital Thermal Sensor (DTS) values for fan speed control.2.6 Interface Clocking2.6.1 Internal Clocking RequirementsTable 2-4. Processor Reference ClocksReference Input Clocks Input Frequency Associated PLLBCLK/BCLK# 133 MHz Processor/Memory/GraphicsPEG_CLK/PEG_CLK# 100 MHz PCI Express*/DMI/Intel® FDIDPLL_REF_SSCLK/DPLL_REF_SSCLK# 120 MHz Embedded DisplayPort* (eDP)§Datasheet 35

Technologies3 Technologies3.1 Intel Graphics Dynamic FrequencyGraphics render frequency are selected by the Intel graphics driver dynamically basedon graphics workload demand as permitted by Intel Turbo Boost Technology Driver. Theprocessor core die and the integrated graphics and memory controller core die have anindividual TDP limit. If one component is not consuming enough thermal power toreach its TDP, the other component can increase its TDP limit and take advantage of theunused thermal power headroom. For the integrated graphics, this could mean anincrease in the render core frequency (above its rated frequency) and increasedgraphics performance.Note:Please note that processor Turbo is not supported on Pentium processor skus.Processor Utilization of Intel Graphics Dynamic Frequency require the following Graphics driver Intel Turbo Boost Technology DriverEnabling Intel Turbo Boost Technology and Intel Graphics Dynamic Frequency willmaximize the performance of the GPU within its specified power levels. Compared withprevious generation products, Intel Turbo Boost Technology and Intel GraphicsDynamic Frequency will increase the ratio of application power to TDP. Thus, thermalsolutions and platform cooling that are designed to less than thermal design guidancemight experience thermal and performance issues since more applications will tend torun at the maximum power limit for significant periods of time. For more details, referto Chapter 5, Thermal Management.§36 Datasheet

Power Management4 Power ManagementThis chapter provides information on the following power management topics: ACPI States Processor Core Integrated Memory Controller (IMC) PCI Express Direct Media Interface (DMI) Integrated Graphics Controller4.1 ACPI States SupportedThe ACPI states supported by the processor are described in this section.4.1.1 System StatesTable 4-5. System StatesStateG0/S0G1/S3-ColdG1/S4G2/S5G3Full OnDescriptionSuspend-to-RAM (STR). Context saved to memory (S3-Hot is notsupported by the processor).Suspend-to-Disk (STD). All power lost (except wakeup on PCH).Soft off. All power lost (except wakeup on PCH). Total reboot.Mechanical off. All power (AC and battery) removed from system.4.1.2 Processor Core/Package Idle StatesTable 4-6. Processor Core/Package State SupportStateDescriptionC0C1C1EC3C6Active mode, processor executing code.AutoHALT state.AutoHALT state with lowest frequency and voltage operating point.Execution cores in C3 flush their L1 instruction cache, L1 data cache,and L2 cache to the L3 shared cache. Clocks are shut off to each core.Execution cores in this state save their architectural state beforeremoving core voltage.Datasheet 37

Power Management4.1.3 Integrated Memory Controller StatesTable 4-7. Integrated Memory Controller StatesStatePower upPre-charge Power downActive Power downSelf-RefreshDescriptionCKE asserted. Active mode.CKE deasserted (not self-refresh) with all banks closed.CKE deasserted (not self-refresh) with minimum one bank active.CKE deasserted using device self-refresh.4.1.4 PCIe Link StatesTable 4-8. PCIe Link StatesStateDescriptionL0L0sL1L3Full on Active transfer state.First Active Power Management low power state Low exit latency.Lowest Active Power Management - Longer exit latency.Lowest power state (power-off) Longest exit latency.4.1.5 DMI StatesTable 4-9. DMI StatesStateDescriptionL0L0sL1L3Full on Active transfer state.First Active Power Management low power state Low exit latency.Lowest Active Power Management - Longer exit latency.Lowest power state (power-off) Longest exit latency.4.1.6 Integrated Graphics Controller StatesTable 4-10.Integrated Graphics Controller StatesStateDescriptionD0D3 ColdFull on, display active.Power-off.38 Datasheet

Power Management4.1.7 Interface State CombinationsTable 4-11.G, S and C State CombinationsGlobal(G) StateSleep(S) StateProcessorCore(C) StateProcessorStateSystem ClocksDescriptionG0 S0 C0 Full On On Full OnG0 S0 C1/C1E Auto-Halt On Auto-HaltG0 S0 C3 Deep Sleep On Deep SleepG0 S0 C6 Deep PowerDownOnDeep Power DownG1 S3 Power off Off, except RTC Suspend to RAMG1 S4 Power off Off, except RTC Suspend to DiskG2 S5 Power off Off, except RTC Soft OffG3 NA Power off Power off Hard offTable 4-12.D, S, and C State CombinationGraphics Adapter(D) StateSleep (S) State Package (C) State DescriptionD0 S0 C0 Full On, DisplayingD0 S0 C1/C1E Auto-Halt, DisplayingD0 S0 C3 Deep sleep, DisplayingD0 S0 C6 Deep Power Down,DisplayingD3 S0 Any Not displayingD3 S3 N/A Not displaying, GraphicsCore is powered offD3 S4 N/A Not displaying, suspend todisk4.2 Processor Core Power ManagementWhile executing code, Enhanced Intel SpeedStep Technology optimizes the processorsfrequency and core voltage based on workload. Each frequency and voltage operatingpoint is defined by ACPI as a P-state. When the processor is not executing code, it isidle. A low-power idle state is defined by ACPI as a C-state. In general, lower powerC-states have longer entry and exit latencies.Datasheet 39

Power Management4.2.1 Enhanced Intel SpeedStep® TechnologyThe following are the key features of Enhanced Intel SpeedStep Technology: Multiple frequency and voltage points for optimal performance and powerefficiency. These operating points are known as P-states. Frequency selection is software controlled by writing to processor MSRs. Thevoltage is optimized based on the selected frequency and the number of activeprocessor cores. If the target frequency is higher than the current frequency, V CC is ramped up insteps to an optimized voltage. This voltage is signaled by the VID[6:0] pins tothe voltage regulator. Once the voltage is established, the PLL locks on to thetarget frequency. If the target frequency is lower than the current frequency, the PLL locks to thetarget frequency, then transitions to a lower voltage by signaling the targetvoltage on the VID[6:0] pins. All active processor cores share the same frequency and voltage. In a multi-coreprocessor, the highest frequency P-state requested amongst all active cores isselected. Software-requested transitions are accepted at any time. If a previous transitionis in progress, the new transition is deferred until the previous transition iscompleted. The processor controls voltage ramp rates internally to ensure glitch-freetransitions. Because there is low transition latency between P-states, a significant number oftransitions per-second are possible.4.2.2 Low-Power Idle StatesWhen the processor is idle, low-power idle states (C-states) are used to save power.More power savings actions are taken for numerically higher C-states. However, higherC-states have longer exit and entry latencies. Resolution of C-states occur at thethread, processor core, and processor package level. Thread-level C-states areavailable if Intel Hyper-Threading Technology is enabled.40 Datasheet

Power ManagementFigure 4-9. Idle Power Management Breakdown of the Processor CoresThread 0Thread 0Core 0 StateCore 1 StateProcessor Package StateEntry and exit of the C-States at the thread and core level are shown in below figure.Figure 4-10.Thread and Core C-State Entry and ExitMWAIT(C1), HLTMWAIT(C1), HLT(C1E Enabled)C0MWAIT(C6),P_LVL3 I/O ReadMWAIT(C3),P_LV2 I/O ReadC1 C1E C3C6While individual threads can request low power C-states, power saving actions onlytake place once the core C-state is resolved. Core C-states are automatically resolvedby the processor. For thread and core C-states, a transition to and from C0 is requiredbefore entering any other C-state.Datasheet 41

Power ManagementTable 4-13.Coordination of Thread Power States at the Core LevelProcessor CoreC-StateThread 1C0 C1 C3 C6C0 C0 C0 C0 C0C1 C0 C1 1 C1 1 C1 1C3 C0 C1 1 C3 C3C6 C0 C1 1 C3 C6NOTE:If enabled, the core C-state will be C1E if all actives cores have also resolved acore C1 state or higher4.2.3 Requesting Low-Power Idle StatesThe primary software interfaces for requesting low power idle states are through theMWAIT instruction with sub-state hints and the HLT instruction (for C1 and C1E).However, software may make C-state requests using the legacy method of I/O readsfrom the ACPI-defined processor clock control registers, referred to as P_LVLx. Thismethod of requesting C-states provides legacy support for operating systems thatinitiate C-state transitions via I/O reads.For legacy operating systems, P_LVLx I/O reads are converted within the processor tothe equivalent MWAIT C-state request. Therefore, P_LVLx reads do not directly result inI/O reads to the system. The feature, known as I/O MWAIT redirection, must beenabled in the BIOS.Note:The P_LVLx I/O Monitor address needs to be set up before using the P_LVLx I/O readinterface. Each P-LVLx is mapped to the supported MWAIT(Cx) instruction as follows.Table 4-14.P_LVLx to MWAIT ConversionP_LVLx MWAIT(Cx) NotesP_LVL2 MWAIT(C3) The P_LVL2 base address is defined in the PMG_IO_CAPTUREMSR, described in the RS - Nehalem Processor Family BWG.P_LVL3 MWAIT(C6) C6. No sub-states allowed.The BIOS can write to the C-state range field of the PMG_IO_CAPTURE MSR to restrictthe range of I/O addresses that are trapped and emulate MWAIT like functionality. AnyP_LVLx reads outside of this range does not cause an I/O redirection to MWAIT(Cx) likerequest. They fall through like a normal I/O instruction.Note:When P_LVLx I/O instructions are used, MWAIT substates cannot be defined. TheMWAIT substate is always zero if I/O MWAIT redirection is used. By default, P_LVLx I/Oredirections enable the MWAIT 'break on EFLAGS.IF feature which triggers a wakeupon an interrupt even if interrupts are masked by EFLAGS.IF.42 Datasheet

Power Management4.2.4 Core C-statesThe following are general rules for all core C-states, unless specified otherwise: A core C-State is determined by the lowest numerical thread state (e.g., Thread 0requests C1E while Thread 1 requests C3, resulting in a core C1E state). SeeTable 4-11. A core transitions to C0 state when: An interrupt occurs4.2.4.1 Core C0 State There is an access to the monitored address if the state was entered via anMWAIT instruction For core C1/C1E, and core C3, an interrupt directed toward a single thread wakesonly that thread. However, since both threads are no longer at the same coreC-state, the core resolves to C0. For core C6, an interrupt coming into either thread wakes both threads into C0state. Any interrupt coming into the processor package may wake any core.The normal operating state of a core where code is being executed.4.2.4.2 Core C1/C1E StateC1/C1E is a low power state entered when all threads within a core execute a HLT orMWAIT(C1/C1E) instruction.A System Management Interrupt (SMI) handler returns execution to either Normalstate or the C1/C1E state. See the Intel ® 64 and IA-32 Architecture SoftwareDeveloper’s Manual, Volume 3A/3B: System Programmer’s Guide for more information.While a core is in C1/C1E state, it processes bus snoops and snoops from otherthreads. For more information on C1E, see Package C1/C1E.4.2.4.3 Core C3 StateIndividual threads of a core can enter the C3 state by initiating a P_LVL2 I/O read tothe P_BLK or an MWAIT(C3) instruction. A core in C3 state flushes the contents of itsL1 instruction cache, L1 data cache, and L2 cache to the shared L3 cache, whilemaintaining its architectural state. All core clocks are stopped at this point. Because thecores caches are flushed, the processor does not wake any core that is in the C3 statewhen either a snoop is detected or when another core accesses cacheable memory.Datasheet 43

Power Management4.2.4.4 Core C6 StateIndividual threads of a core can enter the C6 state by initiating a P_LVL3 I/O read or anMWAIT(C6) instruction. Before entering core C6, the core will save its architecturalstate to a dedicated SRAM. Once complete, a core will have its voltage reduced to zerovolts. During exit, the core is powered on and its architectural state is restored.4.2.4.5 C-State Auto-DemotionIn general, deeper C-states such as Deep Power Down Technology (code named C6state) have long latencies and have higher energy entry/exit costs. The resultingperformance and energy penalties become significant when the entry/exit frequency ofa deeper C-state is high. Therefore incorrect or inefficient usage of deeper C-stateshave a negative impact on battery life. In order to increase residency and improvebattery life in deeper C-states, the processor supports C-state auto-demotion.There are two C-State auto-demotion options: Deep Power Down Technology (code named C6 state) to C3 Deep Power Down Technology (code named C6 state)/C3 To C1The decision to demote a core from Deep Power Down Technology (code named C6state) to C3 or C3/Deep Power Down Technology (code named C6 state) to C1 is basedon each cores immediate residency history. Upon each core Deep Power DownTechnology (code named C6 state) request, the core C-state is demoted to C3 or C1until a sufficient amount of residency has been established. At that point, a core isallowed to go into C3/Deep Power Down Technology (code named C6 state). Eachoption can be run concurrently or individually.This feature is disabled by default.4.2.5 Package C-StatesThe processor supports C0, C1/C1E, C3, and Deep Power Down Technology (codenamed C6 state) package idle power states. The following is a summary of the generalrules for package C-state entry. These apply to all package C-states unless specifiedotherwise: A package C-state request is determined by the lowest numerical core C-stateamongst all cores. A package C-state is automatically resolved by the processor depending on thecore idle power states and the status of the platform components. Each core can be at a lower idle power state than the package if the platformdoes not grant the processor permission to enter a requested package C-state. The platform may allow additional power savings to be realized in the processor.Refer to Section 4.3.2.2 For package C-states, the processor is not required to enter C0 before entering anyother C-state.44 Datasheet

Power ManagementThe processor exits a package C-state when a break event is detected. Depending onthe type of break event, the processor does the following: If a core break event is received, the target core is activated and the break eventmessage is forwarded to the target core. If the break event is not masked, the target core enters the core C0 state andthe processor enters package C0. If the break event is masked, the processor attempts to re-enter its previouspackage state. If the break event was due to a memory access or snoop request. But the platform did not request to keep the processor in a higher package C-state, the package returns to its previous C-state. And the platform requests a higher power C-state, the memory access or snooprequest is serviced and the package remains in the higher power C-state.Table 4-15 shows package C-state resolution for a dual-core processor. Figure 4-11summarizes package C-state transitions.Table 4-15.Coordination of Core Power States at the Package LevelCore 1Package C-StateC0 C1 C3Deep PowerDownTechnology(code namedC6 state)C0 C0 C0 C0 C0C1 C0 C1 1 C1 1 C1 1C3 C0 C1 1 C3 C3C6 C0 C1 1 C3 C6NOTE:1. If enabled, the package C-state will be C1E if all actives cores have resolved a core C1state or higher.Datasheet 45

Power ManagementFigure 4-11.Package C-State Entry and ExitC0C3C1C64.2.5.1 Package C0The normal operating state for the processor. The processor remains in the normalstate when at least one of its cores is in the C0 or C1 state or when the platform hasnot granted permission to the processor to go into a low power state. Individual coresmay be in lower power idle states while the package is in C0.4.2.5.2 Package C1/C1ENo additional power reduction actions are taken in the package C1 state. However, ifthe C1E sub-state is enabled, the processor automatically transitions to the lowestsupported core clock frequency, followed by a reduction in voltage.The package enters the C1 low power state when: At least one core is in the C1 state. The other cores are in a C1 or lower power state.The package enters the C1E state when: All cores have directly requested C1E via MWAIT(C1) with a C1E sub-state hint. All cores are in a power state lower that C1/C1E but the package low power state islimited to C1/C1E via the PMG_CST_CONFIG_CONTROL MSR. All cores have requested C1 using HLT or MWAIT(C1) and C1E auto-promotion isenabled in IA32_MISC_ENABLES.46 Datasheet

Power ManagementNo notification to the system occurs upon entry to C1/C1E.4.2.5.3 Package C3 StateA processor enters the package C3 low power state when: At least one core is in the C3 state. The other cores are in a C3 or lower power state, and the processor has beengranted permission by the platform. The platform has not granted a request to a package C6 state but has allowed apackage C6 state.In package C3-state, the L3 shared cache is snoopable.4.2.5.4 Package C6 StateA processor enters the package C6 low power state when: At least one core is in the C6 state. The other cores are in a C6 or lower power state, and the processor has beengranted permission by the platform.In package C6 state, all cores have saved their architectural state and have had theircore voltages reduced to zero volts. The L3 shared cache is still powered and snoopablein this state. The processor remains in package C6 state as long as any part of the L3cache is active.4.2.5.5 Power Status Indicator (PSI#) and DPRSLPVR#PSI# and DPRSLPVR# are signals used to optimize VR efficiency over a wide powerrange depending on amount of activity within the processor core. The PSI# signal isutilized by the processor core to: Improve intermediate and light load efficiency of the voltage regulator when theprocessor is active (P-states). Optimize voltage regulator efficiency in very low power states. Assertion ofDPRSLPVR# indicates that the processor core is in a C6 low power state.The VR efficiency gains result in overall platform power savings and extended batterylife.4.3 IMC Power ManagementThe main memory is power managed during normal operation and in low-power ACPICx states.Datasheet 47

Power Management4.3.1 Disabling Unused System Memory OutputsAny system memory (SM) interface signal that goes to a memory module connector inwhich it is not connected to any actual memory devices (such as SO-DIMM connector isunpopulated, or is single-sided) is tri-stated. The benefits of disabling unused SMsignals are: Reduced power consumption. Reduced possible overshoot/undershoot signal quality issues seen by the processorI/O buffer receivers caused by reflections from potentially un-terminatedtransmission lines.When a given rank is not populated, the corresponding chip select and CKE signals arenot driven.At reset, all rows must be assumed to be populated, until it can be proven that they arenot populated. This is due to the fact that when CKE is tristated with an SO-DIMMpresent, the SO-DIMM is not guaranteed to maintain data integrity.4.3.2 DRAM Power Management and InitializationThe processor implements extensive support for power management on the SDRAMinterface. There are four SDRAM operations associated with the Clock Enable (CKE)signals, which the SDRAM controller supports. The processor drives four CKE pins toperform these operations.4.3.2.1 Initialization Role of CKEDuring power-up, CKE is the only input to the SDRAM that has its level is recognized(other than the DDR3 reset pin) once power is applied. It must be driven LOW by theDDR controller to make sure the SDRAM components float DQ and DQS during powerup.CKE signals remain LOW (while any reset is active) until the BIOS writes to aconfiguration register. Using this method, CKE is guaranteed to remain inactive formuch longer than the specified 200 micro-seconds after power and clocks to SDRAMdevices are stable.4.3.2.2 Conditional Self-RefreshThe processor conditionally places memory into self-refresh in the package C3 and C6low-power states.When entering the Suspend-to-RAM (STR) state, the processor core flushes pendingcycles and then enters all SDRAM ranks into self refresh. In STR, the CKE signalsremain LOW so the SDRAM devices perform self-refresh.The target behavior is to enter self-refresh for the package C3 and C6 states as long asthere are no memory requests to service. The target usage is shown in Table 4-16.48 Datasheet

Power ManagementTable 4-16.Targeted Memory State ConditionsMode Memory State with Internal Graphics Memory State with External GraphicsC0, C1, C1E Dynamic memory rank power down based onidle conditions.C3, C6 If the internal graphics engine is idle and thereare no pending display requests when in singledisplay mode, then enter self-refresh.Otherwise use dynamic memory rank powerdown based on idle conditions.S3 Self-Refresh Mode. Self-Refresh Mode.4.3.2.3 Dynamic Power Down OperationDynamic power-down of memory is employed during normal operation. Based on idleconditions, a given memory rank may be powered down. The IMC implementsaggressive CKE control to dynamically put the DRAM devices in a power down state.The processor core controller can be configured to put the devices in active power down(CKE deassertion with open pages) or precharge power down (CKE deassertion with allpages closed). Precharge power down provides greater power savings but has a biggerperformance impact, since all pages will first be closed before putting the devices inpower down mode.If dynamic power-down is enabled, all ranks are powered up before doing a refreshcycle and all ranks are powered down at the end of refresh.4.3.2.4 DRAM I/O Power ManagementDynamic memory rank power down based onidle conditions.If there are no memory requests, then enterself-refresh. Otherwise use dynamic memoryrank power down based on idle conditions.S4 Memory power down (contents lost). Memory power down (contents lost)Unused signals should be disabled to save power and reduce electromagneticinterference. This includes all signals associated with an unused memory channel.Clocks can be controlled on a per SO-DIMM basis. Exceptions are made for per SO-DIMM control signals such as CS#, CKE, and ODT for unpopulated SO-DIMM slots.The I/O buffer for an unused signal should be tri-stated (output driver disabled), theinput receiver (differential sense-amp) should be disabled, and any DLL circuitryrelated ONLY to unused signals should be disabled. The input path must be gated toprevent spurious results due to noise on the unused signals (typically handledautomatically when input receiver is disabled).4.4 PCIe Power Management Active power management support using L0s, and L1 states. All inputs and outputs disabled in L2/L3 Ready state.Datasheet 49

Power Management4.5 DMI Power ManagementActive power management support using L0s/L1 state.4.6 Integrated Graphics Power Management4.6.1 Intel ® Display Power Saving Technology 5.0(Intel ® DPST 5.0)Intel DPST maintains visual experience by managing display image brightness andcontrast while adaptively dimming the backlight. As a result, the display backlightpower can be reduced by up to 25% depending on Intel DPST settings and system use.Intel DPST 5.0 provides enhanced image quality over the previous version of IntelDPST.4.6.2 Graphics Render C-StateRender C-State (RC6) is a technique designed to optimize the average power to thegraphics render engine during times of idleness of the render engine. RC6 is enteredwhen the graphics render engine, blitter engine and the video engine have no workloadbeing currently worked on and no outstanding graphics memory transactions. Whenthe render engine idleness condition is met: The graphics VR will lower the graphicsvoltage rail (V AXG ) into a lower voltage state (0.3 V).The render frequency clock willshut down.4.6.3 Graphics Performance Modulation TechnologyGraphics Performance Modulation Technology (GPMT) is a method for optimizing thepower efficiency in the graphics render engine while continuing to render 3D objectsduring battery operation. The GPMT feature will dynamically switch the renderfrequency based on the render workload, on power policy, skew, and environmentalconditions.4.6.4 Intel ® Smart 2D Display Technology (Intel ® S2DDT)Intel S2DDT reduces display refresh memory traffic by reducing memory readsrequired for display refresh. Power consumption is reduced by less accesses to the IMC.Intel S2DDT is most effective with: Display images well suited to compression, such as text windows, slide shows, etc.Poor examples are 3D games. Static screens such as screens with significant portions of the background showing2D applications, CPU benchmarks, etc., or conditions when the CPU is idle. Poorexamples are full-screen 3D games and benchmarks that flip the display image ator near display refresh rates.50 Datasheet

Power Management4.7 Thermal Power Management See Section 5, Thermal Management on page 52 for all graphics thermal powermanagement-related features.§Datasheet 51

Thermal Management5 Thermal ManagementA multi-chip package (MCP) processor requires a thermal solution to maintaintemperatures of the processor core and graphics/memory core within operating limits.A complete thermal solution provides both the component-level and the system-levelthermal management. To allow for the optimal operation and long-term reliability ofIntel processor-based systems, the system/processor thermal solution should bedesigned so that the processor: Remains below the maximum junction temperature (T j,Max ) specification at themaximum thermal design power (TDP). Conforms to system constraints, such as system acoustics, system skintemperatures,and exhaust-temperature requirements.Caution:Thermal specifications given in this chapter are on the component and package leveland apply specifically to the processor. Operating the processor outside the specifiedlimits may result in permanent damage to the processor and potentially othercomponents in the system.5.1 Thermal Design Power and Junction TemperatureThe TDP of an MCP processor is the expected maximum power from each of itscomponents (processor core and integrated graphics and memory controller) whilerunning realistic, worst case applications (TDP applications).TDP is not the absoluteworst case power of each component. It could, for example, be exceeded under asynthetic worst case condition or under short power spikes. In production, a range ofpower is to be expected from the components due to the natural variation in themanufacturing process. The thermal solution, at a minimum, needs to ensure that thejunction temperatures of both components do not exceed the maximum junctiontemperature (T j,max ) limit while running TDP applications.5.1.1 Intel Graphics Dynamic FrequencyTypical workloads are not intensive enough to push both the processor core and theintegrated graphics and memory controller towards their TDP limit simultaneously. Assuch, the opportunity exists to share thermal power between the components andboost the performance of either the processor core or integrated graphics and memorycontroller on demand. This intelligent power sharing capability is implemented by IntelTurbo Boost Technology Driver on these processors. When enabled, the integratedgraphics and memory controller can increase its thermal power consumption above itsown component TDP limit. However, the sum of component thermal powers adhere tothe specified MCP thermal power limit.On this processor, Intel Graphics Dynamic Frequency is implemented via a combinationof Intel silicon capabilities, graphics driver and the Intel Turbo Boost Technology driver.If Intel provides Intel Graphics Dynamic Frequency support for the target operating52 Datasheet

Thermal Managementsystem that is shipped with the customers platform and Intel Graphics DynamicFrequency is enabled, the Intel Turbo Boost Technology driver and graphics driver mustbe installed and operating to keep the product operating within specification limits.Caution:The TURBO_POWER_CURRENT_LIMIT MSR is exclusively reserved for Intel TurboTechnology Driver use. Under no circumstances should this value be altered from thedefault register value after reset of the processor. Altering this MSR value may result inunpredictable behavior.5.1.2 Intel Graphics Dynamic Frequency Thermal DesignConsiderations and SpecificationsWhen designing a thermal solution for Intel Graphics Dynamic frequency enabledprocessor: Both component TDPs as well as extreme thermal power levels for the processorcore and integrated graphics and memory controller must be considered. Note that the processor can consume close to its maximum thermal power limitmore frequently, and for prolonged periods of time. One must ensure that the component T j,max limits are not exceeded when eithercomponent is operating at its extreme thermal power limit.There are two extreme design points: The processor core operating at maximum thermal power level (which is greaterthan its component TDP) and the integrated graphics and memory controlleroperating at its minimum thermal power. The integrated graphics operates at its maximum thermal power level, while theprocessor core consumes the remaining thermal power budget.In both cases, the combined component thermal power will not exceed the total MCPpackage power limit. The design approach accommodating two extreme power levels isreferred to as a two-point design.The following notes apply to Table 5-17 and Table 5-19.NoteDefinition1 The component TDPs given are not the maximum power the components can generate. Analysisindicates that real applications are unlikely to cause the processor to consume the theoreticalmaximum power dissipation for sustained periods of time.2 A range of power is to be expected among the components due to the natural variation in themanufacturing process. Nevertheless, the individual component powers are not to exceed thecomponent TDPs specified.3 Concurrent package power refers to the actual power consumed by the package while TDPapplications are running simultaneously by the processor core and the integrated graphicscontroller. An example of this could be the processor core running a Prime95* application, and theintegrated graphics core running a Star Wars: Jedi Knight* menu simultaneously.4 The thermal solution needs to ensure that the temperatures of both components do not exceed themaximum junction temperature (T j,max ) limit, as measured by the DTS and the critical temperaturebit. Please refer to processor Specification Update for Tjmax value per sku.Datasheet 53

Thermal ManagementNoteDefinition5 Processor core and integrated graphics and memory controller junction temperatures are monitoredby their respective DTS. A DTS outputs a temperature relative to the maximum supported junctiontemperature. The error associated with DTS measurements will not exceed ±5°C within theoperating range.6 The power supply to the processor core and the integrated graphics /Memory core should bedesigned as per Intels guidelines.7 Processor core currents is monitored by IMON VR feedback (ISENSE) and calculated using a movingaverage method. Error associated with power monitoring will depend upon individual VR design.8 A thermal solution for an power sharing enabled system needs to ensure that the Tj limit is notexceeded while operating under the two extreme power conditions between the processor core andthe integrated graphics and memory controller components.9 Projected range in advance of the measured product data. Measured values will be available aftersilicon characterization.10 For power sharing designs it is recommended to establish the full cooling capability within 10°C ofthe T j,max specifications. Some processors may have a different Tj max value, please refer to theprocessor Specification Update for details.11 In rare occasions the specified maximum power limits may be violated when the package is not at athermally constrained environment12 Tj, min =0 deg13 While running intensive graphical and computational workloads simultaneously the concurrentpackage power may exceed specified limits in exceptional occasions. Nevertheless, the individualcomponent powers are not to exceed the component TDPs specified.Table 5-17.Intel Pentium U5000 Mobile Processor Series Dual-Core ULV Thermal PowerSpecificationsTDP 1,2,6,7FrequencyPower Sharing DesignPoints 8 T j,max4,5,10,12HFM 10.5 8.5 18 1.20166up to500Proc: 10.5Int. Gfx:7.5Proc: 7Int Gfx:1118105 100LFM 9 8.5 17.5 667 MHz N/A N/A N/A N/AHFM 10.5 8.5 18 1.33166up to500Proc: 10.5Int. Gfx:7.5Proc: 7Int Gfx:1118105 100LFM 9 8.5 17.5 667 MHz N/A N/A N/A N/A54 Datasheet

Thermal ManagementTable 5-18.Intel Pentium P6000 Mobile Processor Series Dual-Core SV Thermal PowerSpecificationsTDP 1,2,6,7FrequencyPower SharingDesign Points 8 T j,max4,5,10,12HFM 25 12.5 35 1.86500up to667 90 85LFM 20 12.5 32.5 933 MHz N/AHFM 25 12.5 35 2.00500up to667 90 85LFM 20 12.5 32.5 933 MHz N/AHFM 25 12.5 35 2.13500up to667 90 85LFM 20 12.5 32.5 933 MHz N/A5.1.3 Idle Power SpecificationsThe idle power specifications in Table 5-17 and Table 5-19 are not 100% tested. Thesepower specifications are determined by the characterization of the processor currentsat higher temperatures and extrapolating the values for the junction temperatureindicated.Table 5-19.18 W Ultra Low Voltage (ULV) Processor Idle PowerSymbol Parameter Min Typ Max T jP C1E Idle power in the Package C1e state - - 12 W 50ºCP C3 Idle power in the Package C3 state - - 5.0 W 35ºCP C6 Idle power in the Package C6 state - - 2.6 W 35ºCDatasheet 55

Thermal ManagementTable 5-20.35 W Standard Voltage (SV) Processor Idle PowerSymbol Parameter Min Typ Max T jP C1E Idle power in the Package C1e state - - 16 W 50 ºCP C3 Idle power in the Package C3 state - - 7.5 W 35 ºC5.1.4 Intelligent Power Sharing Control OverviewBased upon knowledge of the processor core and integrated graphics and memorycontroller thermal power, performance state, and temperature, power sharing controldoes the following: Utilizes internal graphics controller dynamic frequency performance states toachieve their highest performance within the rated thermal power envelope. IntelDynamic Frequency enabled processors will offer a range of upside performancecapability beyond their rated or guaranteed frequency. Controls the processor core and internal graphics controller Intel Turbo Boostperformance states to ensure that overall MCP thermal power consumption doesnot exceed the specified MCP thermal power limit. Limits MCP component usage to ensure that each of the components' T j,max value isnot exceeded.It is possible that the thermal influence between the MCP components could potentiallycause a component to reach its T j,max , invoking undesirable component hardware autothrottling.It is expected that when running the TDP workload, power sharing controlmay limit the entire range of component Intel Turbo Boost capabilities (effectively,disabling them).The principal component of the power sharing control architecture is the policymanager within the Intel Turbo Boost Technology driver which: Communicates with the graphics software driver to limit, or increase, internalgraphics thermal power. Communicates with the processor core via the PCH to processor core PECI interfaceto limit, or increase, processor core thermal power.The Intel Turbo Boost Technology policy manager will set a thermal power limit towhich the graphics driver and processor core will adjust their Intel Turbo BoostTechnology performance dynamically, to stay within the limit.Note:The processor PECI pin must be connected to the PCH PECI pin in order for Intel TurboBoost Technology to properly function.56 Datasheet

Thermal Management5.1.5 Component Power Measurement/Estimation ErrorThe processor input pin (ISENSE) informs the processor core of how much amperagethe processor core is consuming. This information is provided by the processor core VR.The process will calculate its current power based upon the ISENSE input informationand current voltage state. The internal graphics and memory controller power isestimated by the GFX driver using PMON.Any error in power estimation or measurement may limit or completely eliminate theperformance benefit of Intel Turbo Boost Technology. When a power limit is reached,Power sharing control will adaptively remove Intel Turbo Boost Technology states toremain with the MCP thermal power limit. Power sharing control assumes the powererror is always accurate so if the ISENSE input reports power greater than the actualpower, control mechanisms will lower performance before the actual TDP power limit isreached. Intelligent Power sharing will provide better overall Intel Turbo BoostTechnology performance with increasing VR current sense accuracy. Designers andsystem manufacturers should study trade-offs on VR component accuracycharacteristics, such as inductors, to find the best balance of cost vs. performance fortheir system price and performance targets.5.2 Thermal Management FeaturesThis section will cover thermal management features for the processor.5.2.1 Processor Core Thermal FeaturesOccasionally the processor core will operate in conditions that exceed its maximumallowable operating temperature. This can be due to internal overheating or due tooverheating in the entire system. In order to protect itself and the system from thermalfailure, the processor core is capable of reducing its power consumption and thereby itstemperature until it is back within normal operating limits via the Adaptive ThermalMonitor.The Adaptive Thermal Monitor can be activated when any core temperature, monitoredby a digital thermal sensor (DTS), exceeds its maximum junction temperature (T j,Max )and asserts PROCHOT#. The assertion of PROCHOT# activates the thermal controlcircuit (TCC). The TCC will remain active as long as any core exceeds its temperaturelimit. Therefore, the Adaptive Thermal Monitor will continue to reduce the processorcore power consumption until the TCC is de-activated.Caution:The Adaptive Thermal Monitor must be enabled for the processor to remain withinspecification.5.2.1.1 Adaptive Thermal MonitorThe purpose of the Adaptive Thermal Monitor is to reduce processor core powerconsumption and temperature until it operates at or below its maximum operatingtemperature. Processor core power reduction is achieved by:Datasheet 57

Thermal Management Adjusting the operating frequency (via the core ratio multiplier) and input voltage(via the VID signals). Modulating (starting and stopping) the internal processor core clocks (duty cycle).The Adaptive Thermal Monitor dynamically selects the appropriate method. BIOS is notrequired to select a specific method as with previous-generation processors supportingIntel® Thermal Monitor 1 (TM1) or Intel® Thermal Monitor 2 (TM2). The temperatureat which the Adaptive Thermal Monitor activates the Thermal Control Circuit is not userconfigurable but is software visible in the IA32_TEMPERATURE_TARGET (0x1A2) MSR,Bits 23:16. The Adaptive Thermal Monitor does not require any additional hardware,software drivers, or interrupt handling routines. Note that the Adaptive ThermalMonitor is not intended as a mechanism to maintain processor TDP. The system designshould provide a thermal solution that can maintain TDP within its intended usagerange.5.2.1.1.1 Frequency/VID ControlUpon TCC activation, the processor core attempts to dynamically reduce processor corepower by lowering the frequency and voltage operating point. The operating points areautomatically calculated by the processor core itself and do not require the BIOS toprogram them as with previous generations of Intel processors. The processor core willscale the operating points such that: The voltage will be optimized according to the temperature, the core bus ratio, andnumber of cores in deep C-states. The core power and temperature are reduced while minimizing performancedegradation.A small amount of hysteresis has been included to prevent an excessive amount ofoperating point transitions when the processor temperature is near its maximumoperating temperature. Once the temperature has dropped below the maximumoperating temperature and the hysteresis timer has expired, the operating frequencyand voltage transition back to the normal system operating point. This is illustrated inFigure 5-12.58 Datasheet

Thermal ManagementFigure 5-12.Frequency and Voltage OrderingOnce a target frequency/bus ratio is resolved, the processor core will transition to thenew target automatically. On an upward operating point transition, the voltage transition precedes thefrequency transition. On a downward transition, the frequency transition precedes the voltage transition.When transitioning to a target core operating voltage, a new VID code to the voltageregulator is issued. The voltage regulator must support dynamic VID steps to supportthis method.During the voltage change: It will be necessary to transition through multiple VID steps to reach the targetoperating voltage. Each step is 12.5 mV for Intel MVP-6.5 compliant VRs. The processor continues to execute instructions. However, the processor will haltinstruction execution for frequency transitions.Datasheet 59

Thermal ManagementIf a processor load-based Enhanced Intel SpeedStep Technology/P-state transition(through MSR write) is initiated while the Adaptive Thermal Monitor is active, there aretwo possible outcomes: If the P-state target frequency is higher than the processor core optimized targetfrequency, the p-state transition will be deferred until the thermal event has beencompleted. If the P-state target frequency is lower than the processor core optimized targetfrequency, the processor will transition to the P-state operating point.5.2.1.1.2 Clock ModulationIf the frequency/voltage changes are unable to end an Adaptive Thermal Monitorevent, the Adaptive Thermal Monitor will utilize clock modulation. Clock modulation isdone by alternately turning the clocks off and on at a duty cycle (ratio between clockon time and total time) specific to the processor. The duty cycle is factory configuredto 37.5% on and 62.5% off and cannot be modified. The period of the duty cycle isconfigured to 32 microseconds when the TCC is active. Cycle times are independent ofprocessor frequency. A small amount of hysteresis has been included to preventexcessive clock modulation when the processor temperature is near its maximumoperating temperature. Once the temperature has dropped below the maximumoperating temperature, and the hysteresis timer has expired, the TCC goes inactive andclock modulation ceases. Clock modulation is automatically engaged as part of the TCCactivation when the frequency/VID targets are at their minimum settings. Processorperformance will be decreased by the same amount as the duty cycle when clockmodulation is active. Snooping and interrupt processing are performed in the normalmanner while the TCC is active.5.2.1.2 Digital Thermal SensorEach processor execution core has an on-die Digital Thermal Sensor (DTS) whichdetects the cores instantaneous temperature. The DTS is the preferred method ofmonitoring processor die temperature because It is located near the hottest portions of the die. It can accurately track the die temperature and ensure that the Adaptive ThermalMonitor is not excessively activated.Temperature values from the DTS can be retrieved through A software interface via processor Model Specific Register (MSR). A processor hardware interface as described in Platform Environment ControlInterface (PECI) on page 67.Note:When temperature is retrieved by processor MSR, it is the instantaneous temperatureof the given core. When temperature is retrieved via PECI, it is the averagetemperature of each execution cores DTS over a programmable window (defaultwindow of 256 ms.) Intel recommends using the PECI output reading for fan speed orother platform thermal control.60 Datasheet

Thermal ManagementCode execution is halted in C1-C6. Therefore temperature cannot be read via theprocessor MSR without bringing a core back into C0. However, temperature can still bemonitored through PECI in lower C-states.Unlike traditional thermal devices, the DTS outputs a temperature relative to themaximum supported operating temperature of the processor (T j,max ). It is theresponsibility of software to convert the relative temperature to an absolutetemperature. The absolute reference temperature is readable in an MSR. Thetemperature returned by the DTS is an implied negative integer indicating the relativeoffset from T j,max . The DTS does not report temperatures greater than T j,max .The DTS-relative temperature readout directly impacts the Adaptive Thermal Monitortrigger point. When a DTS indicates that the maximum processor core temperature hasbeen reached (a reading of 0x0 on any core), the TCC will activate and indicate aAdaptive Thermal Monitor event.Changes to the temperature can be detected via two programmable thresholds locatedin the processor thermal MSRs. These thresholds have the capability of generatinginterrupts via the core's local APIC. Refer to the Intel® 64 and IA-32 ArchitecturesSoftware Developer's Manuals for specific register and programming details.5.2.1.3 PROCHOT# SignalPROCHOT# (processor hot) is asserted when the processor core temperature hasreached its maximum operating temperature (T j,max ). This will activate the TCC andsignal a thermal event which is then resolved by the Adaptive Thermal Monitor. SeeFigure 5-12 (above) for a timing diagram of the PROCHOT# signal assertion relative tothe Adaptive Thermal Response. Only a single PROCHOT# pin exists at a package levelof the processor. When any core arrives at the TCC activation point, the PROCHOT#signal will be driven by the processor core. PROCHOT# assertion policies areindependent of Adaptive Thermal Monitor enabling.Note:Bus snooping and interrupt latching are active while the TCC is active.5.2.1.3.1 Bi-Directional PROCHOT#By default, the PROCHOT# signal is defined as an output only. However, the signal maybe configured as bi-directional. When configured as a bi-directional signal, PROCHOT#can be used for thermally protecting other platform components should they overheatas well. When PROCHOT# is signaled externally: The processor core will immediately reduce processor power to the minimumvoltage and frequency supported. This is contrary to the internally-generatedAdaptive Thermal Monitor response. Clock modulation is not activated.The TCC will remain active until the system deasserts PROCHOT#. The processor canbe configured to generate an interrupt upon assertion and deassertion of thePROCHOT# signal.Datasheet 61

Thermal Management5.2.1.3.2 Voltage Regulator ProtectionPROCHOT# may be used for thermal protection of voltage regulators (VR). Systemdesigners can create a circuit to monitor the VR temperature and activate the TCCwhen the temperature limit of the VR is reached. By asserting PROCHOT# (pulled-low)and activating the TCC, the VR will cool down as a result of reduced processor powerconsumption. Bi-directional PROCHOT# can allow VR thermal designs to target thermaldesign current (I TDC ) instead of maximum current. Systems should still provide propercooling for the VR and rely on bi-directional PROCHOT# only as a backup in case ofsystem cooling failure. Overall, the system thermal design should allow the powerdelivery circuitry to operate within its temperature specification even while theprocessor is operating at its TDP.5.2.1.3.3 Thermal Solution Design and PROCHOT# BehaviorWith a properly designed and characterized thermal solution, it is anticipated thatPROCHOT# will only be asserted for very short periods of time when running the mostpower intensive applications. The processor performance impact due to these briefperiods of TCC activation is expected to be so minor that it would be immeasurable.However, an under-designed thermal solution that is not able to prevent excessiveassertion of PROCHOT# in the anticipated ambient environment may: Cause a noticeable performance loss Result in prolonged operation at or above the specified maximum junctiontemperature and affect the long-term reliability of the processor May be incapable of cooling the processor even when the TCC is active continuously(in extreme situations)5.2.1.3.4 Low-Power States and PROCHOT# BehaviorIf the processor enters a low-power package idle state such as C3 or C6 withPROCHOT# asserted, PROCHOT# will remain asserted until: The processor exits the low-power state The processor junction temperature drops below the thermal trip pointNote that the PECI interface is fully operational during all C-states and it is expectedthat the platform continues to manage processor core thermals even during idle statesby regularly polling for thermal data over PECI.5.2.1.4 On-Demand ModeThe processor provides an auxiliary mechanism that allows system software to forcethe processor to reduce its power consumption via clock modulation. This mechanism isreferred to as On-Demand mode and is distinct from Adaptive Thermal Monitor and62 Datasheet

Thermal Managementbi-directional PROCHOT#. Platforms must not rely on software usage of thismechanism to limit the processor temperature. On-Demand Mode can be done viaprocessor MSR or chipset I/O emulation.On-Demand Mode may be used in conjunction with the Adaptive Thermal Monitor.However, if the system software tries to enable On-Demand mode at the same time theTCC is engaged, the factory configured duty cycle of the TCC will override the dutycycle selected by the On-Demand mode. If the I/O based and MSR-based On-Demandmodes are in conflict, the duty cycle selected by the I/O emulation-based On-Demandmode will take precedence over the MSR-based On-Demand Mode.5.2.1.4.1 MSR Based On-Demand ModeIf Bit 4 of the IA32_CLOCK_MODULATION MSR is set to a 1, the processor willimmediately reduce its power consumption via modulation of the internal core clock,independent of the processor temperature. The duty cycle of the clock modulation isprogrammable via Bits 3:1 of the same IA32_CLOCK_MODULATION MSR. In this mode,the duty cycle can be programmed from 12.5% on/87.5% off to 87.5% on/12.5% off in12.5% increments. Thermal throttling using this method will modulate each processorcores clock independently.5.2.1.4.2 I/O Emulation-Based On-Demand ModeI/O emulation-based clock modulation provides legacy support for operating systemsoftware that initiates clock modulation through I/O writes to ACPI defined processorclock control registers on the chipset (PROC_CNT). Thermal throttling using thismethod will modulate all processor cores simultaneously.5.2.1.5 THERMTRIP# SignalRegardless of enabling the automatic or on-demand modes, in the event of acatastrophic cooling failure, the processor will automatically shut down when the siliconhas reached an elevated temperature that risks physical damage to the processor. Atthis point the THERMTRIP# signal will go active. THERMTRIP# activation is independentof processor activity and does not generate any bus cycles.5.2.1.6 Critical Temperature DetectionCritical Temperature detection is performed by monitoring the processor temperatureand temperature gradient. This feature is intended for graceful shutdown before theTHERMTRIP# is activated. If the processor's Adaptive Thermal Monitor is triggered andthe temperature remains high, a critical temperature status and sticky bit are latched inthe thermal status MSR register and also generates a thermal interrupt if enabled. Theassertion of critical temperature bit indicates that processor can no longer be assumedto be working reliably.For more details on the interrupt mechanism, refer to the Intel®64 and IA-32 Architectures Software Developer's Manuals.Datasheet 63

Thermal Management5.2.2 Integrated Graphics and Memory Controller ThermalFeaturesThe integrated graphics and memory controller provides the following features formonitoring the integrated graphics and memory controller temperature and triggeringthermal management: One internal digital thermal sensor Hooks for an external thermal sensor mechanism which can either be TS-on-DIMMor TS-on-BoardThe integrated graphics and memory controller has implemented several silicon levelthermal management features that can lower both integrated graphics and memorycontroller and DDR3 power during periods of high activity. As a result, these featurescan help control temperature and help prevent thermally induced component failures.These features include: Bandwidth throttling triggered by memory loading Bandwidth throttling triggered by integrated graphics and memory controllerheating THERMTRIP# support Render Thermal Throttling5.2.2.1 Internal Digital Thermal SensorThe integrated graphics and memory controller incorporates one on-die digital thermalsensor for thermal management. The thermal sensor may be programmed to causehardware throttling and/or software interrupts. Hardware throttling includes renderthermal throttling and main memory programmable throttling thresholds. Sensor trippoints may also be programmed to generate various interrupts including SCI, SMI,INTR, and SERR. The internal thermal sensor reports six trip points: Aux0, Aux1, Aux2,Aux3, Hot, and Catastrophic trip points in order of increasing temperature.5.2.2.1.1 Aux0, Aux1, Aux2, Aux3 Temperature Trip PointsThese trip points may be set dynamically if desired and provides a configurableinterrupt mechanism to allow software to respond when a trip is crossed in eitherdirection. These auxiliary temperature trip points do not automatically cause anyhardware throttling but may be used by software to trigger interrupts.5.2.2.1.2 Hot Temperature Trip PointThis trip point is set at the temperature at which the integrated graphics and memorycontroller must start throttling. It may optionally enable integrated graphics andmemory controller throttling when the temperature is exceeded. This trip point mayprovide an interrupt to ACPI (or other software) when it is crossed in either direction.Software could optionally set this as an interrupt when the temperature exceeds thislevel setting.64 Datasheet

Thermal Management5.2.2.1.3 Catastrophic Trip PointThis trip point is set at the temperature at which the integrated graphics and memorycontroller must be shut down immediately without any software support. This trip pointmay be programmed to generate an interrupt, enable throttling, or immediately shutdown the system (via Halt or via THERMTRIP# assertion). Crossing a trip point in eitherdirection may generate several types of interrupts.5.2.2.1.4 Recommended Programming for Available Trip PointsSee the integrated graphics and memory controller BIOS Specification forrecommended Trip Point programming. Aux Trip Points (0, 1, 2, 3) should beprogrammed for software and firmware control via interrupts. HOT Trip Point should beset to throttle integrated graphics and memory controller to avoid T j,max of 100°C.Catastrophic Trip Point should be set to halt operation to avoid maximum Tj of 130°C.Note:Crossing a trip point in either direction may generate several types of interrupts. Eachtrip point has a register that can be programmed to select the type of interrupt to begenerated. Crossing a trip point is implemented as edge detection on each trip point togenerate the interrupts. Either edge (i.e., crossing the trip point in either direction)generates the interrupt.5.2.2.1.5 Thermal Sensor Accuracy (T accuracy )The error associated with DTS measurement will not exceed ±5°C within the operatingrange. Integrated graphics and memory controller may not operate above T j,max spec.This value is based on product characterization and is not guaranteed by manufacturingtest.Software has the ability to program the T cat , T hot , and T aux trip points, but these trippoints should be selected with consideration for the thermal sensor accuracy and thequality of the platform thermal solution. Overly conservative (unnecessarily low)temperature settings may unnecessarily degrade performance due to frequentthrottling, while overly aggressive (dangerously high) temperature settings may fail toprotect the part against permanent thermal damage.5.2.2.1.6 Hysteresis OperationHysteresis provides a small amount of positive feedback to the thermal sensor circuit toprevent a trip point from flipping back and forth rapidly when the temperature is rightat the trip point. The digital hysteresis offset is programmable via processor registers.5.2.2.2 Memory Thermal Throttling OptionsThe integrated graphics and memory controller has two, independent mechanisms thatcause system memory throttling:TDP Controller: The TDP Controller is the main mechanism for limiting MCH power bylimiting memory bandwidth. Utilized as a thermal throttling mechanism, this feature istriggered by the Hot temperature trip point of the Graphics and Memory ControllerDatasheet 65

Thermal Managementdigital thermal sensor (DTS) and initiates duty cycle throttling to delay memorytransactions and thereby reducing MCH power. Power reduction is memoryconfiguration and application dependant but duty cycle throttling intervals can becustomized for maximum throttling efficiency. The TDP Controller can also be used as abandwidth limiter using programmable memory read/write bandwidth thresholds. Intelsets the default thresholds that will not restrict bandwidth and performance for mostapplications but these thresholds can be modified to reduce MCH power regardless ofDTS temperature.Note:The TDP controller can be used as a closed loop thermal throttling (CLTT) mechanism oran open loop thermal throttling (OLTT) mechanism, although CLTT is recommended. DRAM Thermal Management: Ensures that the DRAM chips are operating withinthermal limits. The integrated graphics and memory controller can control theamount of integrated graphics and memory controller-initiated bandwidth per rankto a programmable limit via a weighted input averaging filter.5.2.2.3 External Thermal Sensor Interface OverviewThe integrated graphics and memory controller supports two inputs for externalthermal sensor notifications, based on which it can regulate memory accesses.Note:The thermal sensors should be capable of measuring the ambient temperature only andshould be able to assert PM_EXT_TS#[0] and/or PM_EXT_TS#[1] if the preprogrammedthermal limits/conditions are met or exceeded.An external thermal sensor with a serial interface may be placed next to a SO-DIMM (orany other appropriate platform location), or a remote Thermal Diode may be placednext to the SO-DIMM (or any other appropriate platform location) and connected to theexternal Thermal Sensor.Additional external thermal sensor's outputs, for multiple sensors, can be wire-OR'dtogether allow signaling from multiple sensors that are physically located separately.Software can, if necessary, distinguish which SO-DIMM(s) is the source of the overtempthrough the serial interface. However, since the SO-DIMM's is located on the sameMemory Bus Data lines, any integrated graphics and memory controller-based readthrottle will apply equally.Thermal sensors can either be directly routed to the integrated graphics and memorycontroller PM_EXT_TS#[0] and PM_EXT_TS#[1] pins or indirectly routed to integratedgraphics and memory controller by invoking an Embedded Controller (EC) connected inbetween the thermal sensor and integrated graphics and memory controller pins. Bothrouting methods are applicable for both thermal sensors placed on the motherboard(TS-on-Board) and/or thermal sensors located on the memory modules (TS-on-DIMM).5.2.2.4 THERMTRIP# OperationThe integrated graphics and memory controller can assert THERMTRIP# (Thermal Trip)to indicates that its junction temperature has reached a level beyond which damagemay occur. Upon assertion of THERMTRIP#, the integrated graphics and memory66 Datasheet

Thermal Managementcontroller will shut off its internal clocks (thus halting program execution) in an attemptto reduce the core junction temperature. Once activated, THERMTRIP# remains latcheduntil RSTIN# is asserted.5.2.2.5 Render Thermal ThrottlingRender Thermal Throttling of the integrated graphics and memory controller allows forthe reduction the render core engine frequency and voltage, thus reducing internalgraphics controller power and integrated graphics and memory controller thermals.Performance is degraded, but the platform thermal burden is relieved.Render Thermal Throttling using several frequency/voltage operating points that can beused to throttle the render core. If the temperature of the integrated graphics andmemory controller internal DTS exceeds the Hot-trip point, the integrated graphics willswitch to a lower frequency/voltage operating point. After a timeout, the DTS isrechecked, and if the DTS temperature is still greater than the designed hysteresis, theintegrated graphics will continue to switch to lower frequency/voltage operating points.Once the DTS reports a temperature below the hysteresis value, the render clockfrequency and voltage will be restored to its pre-thermal event state.Caution:The Render Thermal Throttling must be enabled for the product to remain withinspecification.5.2.3 Platform Environment Control Interface (PECI)The Platform Environment Control Interface (PECI) is a one-wire interface that providesa communication channel between Intel processor and chipset components to externalmonitoring devices. The processor implements a PECI interface to allow communicationof processor thermal information to other devices on the platform. The processorprovides a digital thermal sensor (DTS) for fan speed control. The DTS is calibrated atthe factory to provide a digital representation of relative processor temperature.Averaged DTS values are read via the PECI interface.The PECI physical layer is a self-clocked one-wire bus that begins each bit with adriven, rising edge from an idle level near zero volts. The duration of the signal drivenhigh depends on whether the bit value is a Logic 0 or Logic 1. PECI also includesvariable data transfer rate established with every message. The single wire interfaceprovides low board routing overhead for the multiple load connections in the congestedrouting area near the processor and chipset components. Bus speed, error checking,and low protocol overhead provides adequate link bandwidth and reliability to transfercritical device operating conditions and configuration information.5.2.3.1 Fan Speed Control with Digital Thermal SensorDigital Thermal Sensor based fan speed control (T FAN ) is a recommended feature toachieve optimal thermal performance. At the T FAN temperature, Intel recommends fullcooling capability well before the DTS reading reaches T j,max . An example of this wouldbe T FAN = T j,max - 10ºC.Datasheet 67

Thermal Management5.2.3.2 Processor Thermal Data Sample Rate and FilteringThe processor digital thermal sensor (DTS) provides an improved capability to monitordevice hot spots, which inherently leads to more varying temperature readings overshort time intervals. To reduce the sample rate requirements on PECI and improvethermal data stability vs. time the processor DTS implements an averaging algorithmthat filters the incoming data. This filter is expressed mathematically as:PECI(t) = PECI(t-1)+1/(2^^X)*[Temp - PECI(t-1)]where: PECI(t) is the new averaged temperature PECI(t-1) is the previous averaged temperature Temp is the raw temperature data from the DTS X is the Thermal Averaging Constant (TAC)The Thermal Averaging Constant is a BIOS configurable value that determines the timein milliseconds over which the DTS temperature values are averaged (the default timeis 256 ms). Short averaging times will make the averaged temperature values respondmore quickly to DTS changes. Long averaging times will result in better overall thermalsmoothing but also incur a larger time lag between fast DTS temperature changes andthe value read via PECI.Within the processor, the DTS converts an analog signal into a digital valuerepresenting the temperature relative to PROCHOT# circuit activation. The conversionsare in integers with each single number change corresponding to approximately 1°C.DTS values reported via the internal processor MSR will be in whole integers.As a result of the PECI averaging function described above, DTS values reported overPECI will include a 6-bit fractional value. Under typical operating conditions, where thetemperature is close to PROCHOT#, the fractional values may not be of interest. Butwhen the temperature approaches zero, the fractional values can be used to detect theactivation of the PROCHOT# circuit. An averaged temperature value between 0 and 1can only occur if the PROCHOT# circuit has been activated during the averagingwindow. As PROCHOT# circuit activation time increases, the fractional value willapproach zero. Fan control circuits can detect this situation and take appropriate actionas determined by the system designers. Of course, fan control chips can also monitorthe PROCHOT# pin to detect PROCHOT# circuit activation via a dedicated input pin onthe package.§68 Datasheet

Signal Description6 Signal DescriptionThis chapter describes the processor signals. They are arranged in functional groupsaccording to their associated interface or category. The following notations are used todescribe the signal type:NotationsIOI/OSignal TypeInput PinOutput PinBi-directional Input/Output PinThe signal description also includes the type of buffer used for the particular signal:Table 6-21.Signal Description Buffer TypesSignalPCI Express*FDIDMICMOSDDR3AGTLRefAsynchronous 1DescriptionPCI Express interface signals. These signals are compatible with PCIExpress 2.0 Signalling Environment AC Specifications and are AC coupled.The buffers are not 3.3-V tolerant. Refer to the PCIe specification.Intel Flexible Display interface signals. These signals are compatible withPCI Express 2.0 Signaling Environment AC Specifications, but are DCcoupled. The buffers are not 3.3-V tolerant.Direct Media Interface signals. These signals are compatible with PCIExpress 2.0 Signaling Environment AC Specifications, but are DC coupled.The buffers are not 3.3-V tolerant.CMOS buffers. 1.1-V tolerantDDR3 buffers: 1.5-V tolerantAnalog reference or output. May be used as a threshold voltage or forbuffer compensationGunning Transceiver Logic signaling technologyVoltage reference signalSignal has no timing relationship with any reference clock.NOTES:1. Qualifier for a buffer type.Datasheet 69

Signal Description6.1 System Memory InterfaceTable 6-22.Memory Channel A (Sheet 1 of 2)Signal NameSA_BS[2:0]SA_WE#SA_RAS#SA_CAS#SA_DM[7:0]SA_DQS[7:0]SA_DQS#[7:0]SA_DQ[63:0]SA_MA[15:0]SA_CK[1:0]SA_CK#[1:0]DescriptionBank Select: These signals define whichbanks are selected within each SDRAM rank.Write Enable Control Signal: Used withSA_RAS# and SA_CAS# (along withSA_CS#) to define the SDRAM Commands.RAS Control Signal: Used with SA_CAS#and SA_WE# (along with SA_CS#) to definethe SRAM Commands.CAS Control Signal: Used with SA_RAS#and SA_WE# (along with SA_CS#) to definethe SRAM Commands.Data Mask: These signals are used to maskindividual bytes of data in the case of apartial write and to interrupt burst writes.When activated during writes, thecorresponding data groups in the SDRAM aremasked. There is one SA_DM[7:0] for everydata byte lane.Data Strobes: SA_DQS[7:0] and itscomplement signal group make up adifferential strobe pair. The data is capturedat the crossing point of SA_DQS[7:0] and itsSA_DQS#[7:0] during read and writetransactionsData Strobe Complements: These are thecomplementary strobe signals.Data Bus: Channel A data signal interface tothe SDRAM data bus.Memory Address: These signals are used toprovide the multiplexed row and columnaddress to the SDRAM.SDRAM Differential Clock: Channel ASDRAM Differential clock signal pair. Thecrossing of the positive edge of SA_CK andthe negative edge of its complementSA_CK# are used to sample the commandand control signals on the SDRAM.SDRAM Inverted Differential Clock:Channel A SDRAM Differential clock signalpaircomplement.Direction/BufferTypeODDR3ODDR3ODDR3ODDR3ODDR3I/ODDR3I/ODDR3I/ODDR3ODDR3ODDR3ODDR370 Datasheet

Signal DescriptionTable 6-22.Memory Channel A (Sheet 2 of 2)Signal NameDescriptionDirection/BufferTypeSA_CKE[1:0]SA_CS#[1:0]SA_ODT[1:0]Clock Enable: (1 per rank) Used to:- Initialize the SDRAMs during power-up- Power-down SDRAM ranks- Place all SDRAM ranks into and out of selfrefreshduring STRChip Select: (1 per rank) Used to selectparticular SDRAM components during theactive state. There is one Chip Select foreach SDRAM rank.On Die Termination: Active TerminationControl.ODDR3ODDR3ODDR3Table 6-23.Memory Channel B (Sheet 1 of 2)Signal NameDescriptionDirection/Buffer TypeSB_BS[2:0]SB_WE#SB_RAS#SB_CAS#SB_DM[7:0]SB_DQS[7:0]SB_DQS#[7:0]SB_DQ[63:0]Bank Select: These signals define whichbanks are selected within each SDRAM rank.Write Enable Control Signal: Used withSB_RAS# and SB_CAS# (along withSB_CS#) to define the SDRAM Commands.RAS Control Signal: Used with SB_CAS#and SB_WE# (along with SB_CS#) to definethe SRAM Commands.CAS Control Signal: Used with SB_RAS#and SB_WE# (along with SB_CS#) to definethe SRAM Commands.Data Mask: These signals are used to maskindividual bytes of data in the case of apartial write and to interrupt burst writes.When activated during writes, thecorresponding data groups in the SDRAM aremasked. There is one SB_DM[7:0] for everydata byte lane.Data Strobes: SB_DQS[7:0] and itscomplement signal group make up adifferential strobe pair. The data is capturedat the crossing point of SB_DQS[7:0] and itsSB_DQS#[7:0] during read and writetransactions.Data Strobe Complements: These are thecomplementary strobe signals.Data Bus: Channel B data signal interface tothe SDRAM data bus.ODDR3ODDR3ODDR3ODDR3ODDR3I/ODDR3I/ODDR3I/ODDR3Datasheet 71

Signal DescriptionTable 6-23.Memory Channel B (Sheet 2 of 2)Signal NameDescriptionDirection/Buffer TypeSB_MA[15:0]SB_CK[1:0]SB_CK#[1:0]SB_CKE[1:0]SB_CS#[1:0]SB_ODT[1:0]Memory Address: These signals are used toprovide the multiplexed row and columnaddress to the SDRAM.SDRAM Differential Clock: Channel BSDRAM Differential clock signal pair. Thecrossing of the positive edge of SB_CK andthe negative edge of its complementSB_CK# are used to sample the commandand control signals on the SDRAM.SDRAM Inverted Differential Clock:Channel B SDRAM Differential clock signalpaircomplement.Clock Enable: (1 per rank) Used to:- Initialize the SDRAMs during power-up.- Power-down SDRAM ranks.- Place all SDRAM ranks into and out of selfrefreshduring STR.Chip Select: (1 per rank) Used to selectparticular SDRAM components during theactive state. There is one Chip Select foreach SDRAM rank.On Die Termination: Active TerminationControl.ODDR3ODDR3ODDR3ODDR3ODDR3ODDR36.2 Memory Reference and CompensationTable 6-24.Memory Reference and CompensationSignal NameSM_RCOMP[2:0]SA_DIMM_VREFDQSB_DIMM_VREFDQDescriptionSystem Memory ImpedanceCompensation:.Memory Channel A/B DIMM Voltage.Direction/BufferTypeIAOA72 Datasheet

Signal Description6.3 Reset and Miscellaneous SignalsTable 6-25.Reset and Miscellaneous Signals (Sheet 1 of 2)Signal NameSM_DRAMRST#PM_EXT_TS#[0]PM_EXT_TS#[1]COMP0COMP1COMP2COMP3PM_SYNCRESET_OBS#RSTIN#BPM#[7:0]DBR#DescriptionDDR3 DRAM Reset: Reset signal fromprocessor to DRAM devices. One for allchannels or SO-DIMMs.External Thermal Sensor Input: If thesystem temperature reaches a dangerouslyhigh value then this signal can be used totrigger the start of system memorythrottling.Impedance compensation must beterminated on the system board using aprecision resistor.Impedance compensation must beterminated on the system board using aprecision resistor.Impedance compensation must beterminated on the system board using aprecision resistor.Impedance compensation must beterminated on the system board using aprecision resistor.Power Management Sync: A sidebandsignal to communicate power managementstatus from the platform to the processor.This signal is an indication of the processorbeing reset.Reset In: When asserted this signal willasynchronously reset the processor logic.This signal is connected to the PLTRST#output of the PCH.Breakpoint and Performance MonitorSignals: Outputs from the processor thatindicate the status of breakpoints andprogrammable counters used for monitoringprocessor performance.Debug Reset: Used only in systems whereno debug port is implemented on the systemboard. DBR# is used by a debug portinterposer so that an in-target probe candrive system reset. This signal only routesthrough the package and does not connect tothe the processor silicon itself.Direction/BufferTypeODDR3ICMOSIAIAIAIAICMOSOAsynchronous CMOSICMOSI/OGTLODatasheet 73

Signal DescriptionTable 6-25.Reset and Miscellaneous Signals (Sheet 2 of 2)Signal NamePRDY#PREQ#RSVDRSVD_TPRSVD_NCTFDescriptionPRDY#: A processor output used by debugtools to determine processor debugreadiness.PREQ#: Used by debug tools to requestdebug operation of the processor.RESERVED. All signals that are RSVD andRSVD_NCTF must be left unconnected on theboard. However, Intel recommends that allRSVD_TP signals have via test points.Direction/BufferTypeOAsynchronous GTLIAsynchronous GTLNo ConnectTest PointNon-Critical toFunction6.4 PCI Express Graphics Interface SignalsTable 6-26.PCI Express Graphics Interface SignalsSignal NamePEG_RX[15:0]PEG_RX#[15:0]PEG_TX[15:0]PEG_TX#[15:0]PEG_ICOMPIPEG_ICOMPODescriptionPCI Express Graphics ReceiveDifferential PairPCI Express Graphics TransmitDifferential PairPCI Express Graphics Input CurrentCompensationPCI Express Graphics Output CurrentCompensationDirection/BufferTypeIPCI ExpressOPCI ExpressIAIAPEG_RCOMPOPCI Express Graphics ResistanceCompensationPEG_RBIAS PCI Express Resistor Bias Control IIAA74 Datasheet

Signal Description6.5 Embedded DisplayPort (eDP)Embedded Display Port SignalsSignal NameeDP_TX[3:0]eDP_TX#[3:0]DescriptionEmbedded DisplayPort Transmit DifferentialPair: Nominally, eDP_TX[3:0] is multiplexedwith PEG_TX[12:15] and eDP_TX#[3:0] ismultiplexed with PEG_TX#[12:15]. Whenreversed, eDP_TX[3:0] is multiplexed withPEG_TX[3:0] and eDP_TX#[3:0] is multiplexedwith PEG_TX#[3:0]ODirection/BufferTypePCI ExpresseDP_AUXeDP_AUX#Embedded DisplayPort Auxiliary DifferentialPair: Nominally, eDP_AUX is multiplexed withPEG_RX[13] and eDP_AUX# is multiplexedwith PEG_RX#[13]. When reversed, eDP_AUXis multiplexed with PEG_RX[2] and eDP_AUX#is multiplexed with PEG_RX#[2]I/OPCI ExpresseDP_HPD#eDP_ICOMPIEmbedded DisplayPort Hot Plug Detect:Nominally, eDP_HPD# is multiplexed withPEG_RX[12]. When reversed, eDP_HPD# ismultiplexed with PEG_RX[3]Embedded DisplayPort Input CurrentCompensation: Multiplexed with PEG_ICOMPIIPCI ExpressIAeDP_ICOMPOeDP_RCOMPOEmbedded DisplayPort Output Current andResistance Compensation: Multiplexed withPEG_ICOMPOEmbedded DisplayPort ResistanceCompensation: Multiplexed with PEG_RCOMPOIAIAeDP_RBIASEmbedded DisplayPort Resistor Bias Control:Multiplexed with PEG_RBIASIA6.6 Intel Flexible Display Interface SignalsTable 6-27.Intel® Flexible Display Interface (Sheet 1 of 2)Signal NameFDI_TX[3:0]FDI_TX#[3:0]FDI_FSYNC[0]FDI_LSYNC[0]DescriptionIntel® Flexible Display InterfaceTransmit Differential Pair - Pipe AIntel® Flexible Display Interface FrameSync - Pipe AIntel® Flexible Display Interface Line Sync- Pipe ADirection/BufferTypeOFDIICMOSICMOSDatasheet 75

Signal DescriptionTable 6-27.Intel® Flexible Display Interface (Sheet 2 of 2)Signal NameFDI_TX[7:4]FDI_TX#[7:4]FDI_FSYNC[1]FDI_LSYNC[1]FDI_INTDescriptionIntel® Flexible Display InterfaceTransmit Differential Pair - Pipe BIntel® Flexible Display Interface FrameSync - Pipe BIntel® Flexible Display Interface Line Sync- Pipe BIntel® Flexible Display Interface Hot PlugInterruptDirection/BufferTypeOFDIICMOSICMOSICMOS6.7 DMITable 6-28.DMI - Processor to PCH Serial InterfaceSignal NameDMI_RX[3:0]DMI_RX#[3:0]DMI_TX[3:0]DMI_TX#[3:0]DescriptionDMI Input from PCH: Direct MediaInterface receive differential pair.DMI Output to PCH: Direct MediaInterface transmit differential pair.Direction/BufferTypeIDMIODMI6.8 PLL SignalsTable 6-29.PLL SignalsSignal NameBCLKBCLK#BCLK_ITPBCLK_ITP#PEG_CLKPEG_CLK#DPLL_REF_SSCLKDPLL_REF_SSCLK#DescriptionDifferential bus clock input to the processorBuffered differential bus clock pair to ITPDifferential PCI Express BasedGraphics/DMI Clock In: These pins receivea 100-MHz Serial Reference clock from theexternal clock synthesizer. This clock is usedto generate the clocks necessary for thesupport of PCI Express. This also is thereference clock for Intel® FDI.Embedded Display Port PLL DifferentialClock In: With or without SSC -120 MHz.Direction/BufferTypeIDiff ClkODiff ClkIDiff ClkIDiff Clk76 Datasheet

Signal Description6.9 TAP SignalsTable 6-30.TAP SignalsSignal NameTCKDescriptionTCK (Test Clock): Provides the clock inputfor the processor Test Bus (also known asthe Test Access Port).Direction/BufferTypeICMOSTDITDI (Test Data In): Transfers serial testdata into the processor. TDI provides theserial input needed for JTAG specificationsupport.TDO Test Data Output OICMOSCMOSTDI_MTDO_MTMSTRST#Test Data In for the GPU/Memory core:Tie TDI_M and TDO_M together on themotherboardTest Data Output from the processorcore: Tie TDO_M and TDI_M together on themotherboard.TMS (Test Mode Select): A JTAGspecification support signal used by debugtools.TRST# (Test Reset) Boundary-Scan testreset pinICMOSOCMOSICMOSICMOSTAPPWRGOOD Power good for ITP OAsynchronous CMOSDatasheet 77

Signal Description6.10 Error and Thermal ProtectionTable 6-31.Error and Thermal ProtectionSignal NameCATERR#PECIPROCHOT#THERMTRIP#DescriptionCatastrophic Error: This signal indicates thatthe system has experienced a catastrophic errorand cannot continue to operate. The processorwill set this for non-recoverable machine checkerrors or other unrecoverable internal errors.External agents are allowed to assert this pinwhich will cause the processor to take a machinecheck exception.PECI (Platform Environment ControlInterface): A serial sideband interface to theprocessor, it is used primarily for thermal, power,and error management. Details regarding thePECI electrical specifications, protocols, andfunctions can be found in the RS - PlatformEnvironment Control Interface (PECI)Specification, Revision 2.0.Processor Hot: PROCHOT# goes active whenthe processor temperature monitoring sensor(s)detects that the processor has reached itsmaximum safe operating temperature. Thisindicates that the processor Thermal ControlCircuit (TCC) has been activated, if enabled. Thissignal can also be driven to the processor toactivate the TCC.Thermal Trip: The processor protects itself fromcatastrophic overheating by use of an internalthermal sensor. This sensor is set well above thenormal operating temperature to ensure thatthere are no false trips. The processor will stopall execution when the junction temperatureexceeds approximately 130°C. This is signaled tothe system by the THERMTRIP# pin.Direction/BufferTypeI/OGTLI/OAsynchronousI/OAsynchronous GTLOAsynchronous GTL78 Datasheet

Signal Description6.11 Power SequencingTable 6-32.Power SequencingSignal NameDescriptionDirection/BufferTypeVCCPWRGOOD_0VCCPWRGOOD_1SM_DRAMPWROKVTTPWRGOODSKTOCC#(rPGA988A only)PROC_DETECT (BGA only)VCCPWRGOOD_0 and VCCPWRGOOD_1(Power Good) Processor Input: Theprocessor requires these signals to be aclean indication that:-VCC, VCCPLL, and VTT supplies are stableand within their specifications-BCLK is stable and has been running for aminimum number of cycles.Both signals must then transitionmonotonically to a high state.VCCPWRGOOD_0 and VCCPWRGOOD_1 canbe driven inactive at any time, but BCLK andpower must again be stable before asubsequent rising edge of these signals.VCCPWRGOOD_0 and VCCPWRGOOD_1should be tied together and connected to thePROCPWRGD output signal of the PCH.SM_DRAMPWROK Processor Input:Connects to PCH DRAMPWROK.VTTPWRGOOD Processor Input: Theprocessor requires this input signal to be aclean indication that the VTT power supply isstable and within specifications. Cleanimplies that the signal will remain low(capable of sinking leakage current), withoutglitches, from the time that the powersupplies are turned on until they come withinspecification. The signal must then transitionmonotonically to a high state. Note it is notvalid for VTTPWRGOOD to be deassertedwhile VCCPWRGOOD_0 andVCCPWRGOOD_1 is asserted.SKTOCC# (Socket Occupied)/PROC_DETECT (Processor Detect): pulledto ground on the processor package. There isno connection to the processor silicon for thissignal. System board designers may use thissignal to determine if the processor ispresent.IAsynchronous CMOSIAsynchronous CMOSIAsynchronous CMOSDatasheet 79

Signal Description6.12 Processor Power SignalsTable 6-33.Processor Power Signals (Sheet 1 of 3)Signal NameDescriptionDirection/BufferTypeVCC Processor core power rail. RefVTT(VTT0 and VTT1)Processor I/O power rail (1.05 V). VTT0 andVTT1 should share the same VRVDDQ DDR3 power rail (1.5 V) RefVCCPLL Power rail for filters and PLLs (1.8 V) RefRefISENSEPROC_DPRSLPVRPSI#Current Sense from an Intel® MVP6.5Compliant Regulator to the processor core.Processor output signal to Intel MVP-6.5controller to indicate that the processor is inthe package C6 state.Processor Power Status Indicator: Thissignal is asserted when the processor corecurrent consumption is less than 15 A.Assertion of this signal is an indication thatthe VR controller does not currently need toprovide ICC above 15 A. The VR controllercan use this information to move to a moreefficient operating point. This signal will deassertat least 3.3 µs before the currentconsumption will exceed 15 A. The minimumPSI# assertion and de-assertion time is 1BCLK.IAOCMOSOAsynchronous CMOS80 Datasheet

Signal DescriptionTable 6-33.Processor Power Signals (Sheet 2 of 3)Signal NameVID[6]VID[5:3]/CSC[2:0]VID[2:0]/MSID[2:0]VTT_SELECTVCC_SENSEVSS_SENSEDescriptionVID[6:0] (Voltage ID) Pins: Used tosupport automatic selection of power supplyvoltages (VCC). These are CMOS signals thatare driven by the processor.CSC[2:0]/VID[5:3] - Current SenseConfiguration bits, for ISENSE gain setting.This value is latched on the rising edge ofVTTPWRGOOD.MSID[2:0]/VID[2:0]- Market SegmentIdentification is used to indicate themaximum platform capability to theprocessor. A processor will only boot if theMSID[2:0] pins are strapped to theappropriate setting (or higher) on theplatform (see Table 7-37 for MSIDencodings). MSID is used to help protect theplatform by preventing a higher powerprocessor from booting in a platformdesigned for lower power processors.MSID[2:0] are latched on the rising edge ofVTTPWRGOOD.NOTE: VID[5:3] and VID[2:0] are bidirectional.As an input, they are CSC[2:0]and MSID[2:0] respectively.The VTT_SELECT signal is used to select thecorrect VTT voltage level for the processor.Voltage Feedback Signals to an Intel MVP-6.5Compliant VR: Use VCC_SENSE to sensevoltage and VSS_SENSE to sense groundnear the silicon with little noise.Direction/BufferTypeOCMOSOCMOSOAVTT_SENSEVSS_SENSE_VTTIsolated low impedance connection to theprocessor VTT voltage and ground. They canbe used to sense or measure voltage nearthe silicon.VAXG Graphics core power rail. RefOAVAXG_SENSEVSSAXG_SENSEGFX_VID[6:0]GFX_VR_ENVAXG_SENSE and VSSAXG_SENSE providean isolated, low impedance connection to theVAXG voltage and ground. They can be usedto sense or measure voltage near the silicon.GFX_VID[6:0] (Voltage ID) pins are used tosupport automatic selection of nominalvoltages (VAXG). These are CMOS signalsthat are driven by the processor.GPU output signal to Intel MVP6.5 compliantVR. This signal is used as an on/off control toenable/disable the GPU VR.OAOCMOSOCMOSDatasheet 81

Signal DescriptionTable 6-33.Processor Power Signals (Sheet 3 of 3)Signal NameGFX_DPRSLPVRGFX_IMONDescriptionGPU output signal to Intel MVP6.5 compliantVR. When asserted this signal indicates thatthe GPU is in render suspend mode. Thissignal is also used to control render suspendstate exit slew rate.Current Sense from an Intel MVP6.5Compliant Regulator to the GPU.Direction/BufferTypeOCMOSIAVDDQ_CK Filtered power for VDDQ (BGA Only) RefVTT0_DDR Filtered power for VTT0 (BGA Only) RefVCAP0VCAP1VCAP2Processor Connection to On-boarddecoupling capacitors (BGA only)PWR6.13 Ground and NCTFTable 6-34.Ground and NCTFSignal NameDescriptionDirection/BufferTypeVSS Processor ground node GNDVSS_NCTFDC_TEST_xx#Non-Critical to Function: The pins are forpackage mechanical reliability.Daisy Chain Test - These pins are for solderjoint reliability and are non-critical tofunction (BGA only).NC6.14 Processor Internal Pull Up/Pull DownTable 6-35.Processor Internal Pull Up/Pull DownSignal Name Pull Up/Pull Down Rail ValueSM_DRAMPWROK Pull Down VSS 10 - 20 kVCCPWRGOOD_0 Pull Down VSS 10 - 20 kVCCPWRGOOD_1VTTPWRGOOD Pull Down VSS 10 - 20 kBPM#[7:0] Pull Up VTT 44 - 55 kTCK Pull Up VTT 44 - 55 kTDI Pull Up VTT 44 - 55 kTMS Pull Up VTT 44 - 55 kTRST# Pull Up VTT 1 - 5 k82 Datasheet

Signal DescriptionTable 6-35.Processor Internal Pull Up/Pull DownSignal Name Pull Up/Pull Down Rail ValueTDI_M Pull Up VTT 44 - 55 kPREQ# Pull Up VTT 44 - 55 kCFG[17:0] Pull Up VTT 5 - 14 k§Datasheet 83

Electrical Specifications7 Electrical Specifications7.1 Power and Ground PinsThe processor has V CC , V TT , V DDQ, V CCPLL, V AXG and V SS (ground) inputs for on-chippower distribution. All power pins must be connected to their respective processorpower planes, while all V SS pins must be connected to the system ground plane. Use ofmultiple power and ground planes is recommended to reduce I*R drop. The V CC pinsmust be supplied with the voltage determined by the processor Voltage IDentification(VID) signals. Likewise, the V AXG pins must also be supplied with the voltagedetermined by the GFX_VID signals. Table 7-36 specifies the voltage level for thevarious VIDs. The voltage levels are the same for both the processor VIDs andGFX_VIDs.7.2 Decoupling GuidelinesDue to its large number of transistors and high internal clock speeds, the processor iscapable of generating large current swings between low- and full-power states. To keepvoltages within specification, output decoupling must be properly designed.Caution:Design the board to ensure that the voltage provided to the processor remains withinthe specifications listed in Table 7-36. Failure to do so can result in timing violations orreduced lifetime of the processor.7.2.1 Voltage Rail DecouplingThe voltage regulator solution must: provide sufficient decoupling to compensate for large current swings generatedduring different power mode transitions. provide low parasitic resistance from the regulator to the socket. meet voltage and current specifications as defined in Table 7-36.7.3 Processor Clocking (BCLK, BCLK#)The processor utilizes a differential clock to generate the processor core(s) operatingfrequency, memory controller frequency, and other internal clocks. The processor corefrequency is determined by multiplying the processor core ratio by 133 MHz. Clockmultiplying within the processor is provided by an internal phase locked loop (PLL),which requires a constant frequency input, with exceptions for Spread SpectrumClocking (SSC).The processors maximum core frequency is configured during power-on reset by usingits manufacturing default value. This value is the highest core multiplier at which theprocessor can operate.84 Datasheet

Electrical Specifications7.3.1 PLL Power SupplyAn on-die PLL filter solution is implemented on the processor. Refer to Table 7-36 forDC specifications7.4 Voltage Identification (VID)The processor uses seven voltage identification pins, VID[6:0], to support automaticselection of the processor power supply voltages. VID pins for the processor are CMOSoutputs driven by the processor VID circuitry. A dedicated graphics voltage regulator isrequired to deliver voltage to the integrated graphics controller. Like the processorcore, the integrated graphics controller will use seven voltage identification pins,GFX_VID[6:0], to set the nominal operating voltage GFX_VID pins for the graphics coreare CMOS outputs driven by the graphics core VID circuitry. Table 7-36 specifies thevoltage level for VID[6:0] and GFX_VID[6:0]; 0 refers to a low-voltage levelVID signals are CMOS push/pull drivers. Refer to Table 7-45 for the DC specificationsfor these signals. The VID codes will change due to temperature, frequency, and/orpower mode load changes in order to minimize the power of the part. A voltage rangeis provided in Table 7-36. The specifications are set so that one voltage regulator canoperate with all supported frequencies.Individual processor VID values may be set during manufacturing so that two devicesat the same core frequency may have different default VID settings. This is shown inthe VID range values in Table 7-36. The processor provides the ability to operate whiletransitioning to an adjacent VID and its associated processor core voltage (V CC ). Thiswill represent a DC shift in the loadline.Note:A low-to-high or high-to-low voltage state change will result in as many VID transitionsas necessary to reach the target core voltage. Transitions above the maximum or belowthe minimum specified VID are not permitted. One VID transition occurs in 2.5 µs.The VR utilized must be capable of regulating its output to the value defined by the newVID values issued. DC specifications for dynamic VID transitions are included inTable 7-36.Several of the VID signals (VID[5:3]/CSC[2:0] and VID[2:0]/MSID[2:0]) serve a dualpurpose and are sampled during reset. Refer to the signal description table inChapter 6 for more information.Table 7-36.Voltage Identification Definition (Sheet 1 of 4)VID6 VID5 VID4 VID3 VID2 VID1 VID0 V CC (V)0 0 0 0 0 0 0 1.50000 0 0 0 0 0 1 1.48750 0 0 0 0 1 0 1.47500 0 0 0 0 1 1 1.46250 0 0 0 1 0 0 1.45000 0 0 0 1 0 1 1.43750 0 0 0 1 1 0 1.4250Datasheet 85

Electrical SpecificationsTable 7-36.Voltage Identification Definition (Sheet 2 of 4)VID6 VID5 VID4 VID3 VID2 VID1 VID0 V CC (V)0 0 0 0 1 1 1 1.41250 0 0 1 0 0 0 1.40000 0 0 1 0 0 1 1.38750 0 0 1 0 1 0 1.37500 0 0 1 0 1 1 1.36250 0 0 1 1 0 0 1.35000 0 0 1 1 0 1 1.33750 0 0 1 1 1 0 1.32500 0 0 1 1 1 1 1.31250 0 1 0 0 0 0 1.30000 0 1 0 0 0 1 1.28750 0 1 0 0 1 0 1.27500 0 1 0 0 1 1 1.26250 0 1 0 1 0 0 1.25000 0 1 0 1 0 1 1.23750 0 1 0 1 1 0 1.22500 0 1 0 1 1 1 1.21250 0 1 1 0 0 0 1.20000 0 1 1 0 0 1 1.18750 0 1 1 0 1 0 1.17500 0 1 1 0 1 1 1.16250 0 1 1 1 0 0 1.15000 0 1 1 1 0 1 1.13750 0 1 1 1 1 0 1.12500 0 1 1 1 1 1 1.11250 1 0 0 0 0 0 1.10000 1 0 0 0 0 1 1.08750 1 0 0 0 1 0 1.07500 1 0 0 0 1 1 1.06250 1 0 0 1 0 0 1.05000 1 0 0 1 0 1 1.03750 1 0 0 1 1 0 1.02500 1 0 0 1 1 1 1.01250 1 0 1 0 0 0 1.00000 1 0 1 0 0 1 0.98750 1 0 1 0 1 0 0.97500 1 0 1 0 1 1 0.96250 1 0 1 1 0 0 0.95000 1 0 1 1 0 1 0.93750 1 0 1 1 1 0 0.92500 1 0 1 1 1 1 0.91250 1 1 0 0 0 0 0.90000 1 1 0 0 0 1 0.88750 1 1 0 0 1 0 0.87500 1 1 0 0 1 1 0.86250 1 1 0 1 0 0 0.850086 Datasheet

Electrical SpecificationsTable 7-36.Voltage Identification Definition (Sheet 3 of 4)VID6 VID5 VID4 VID3 VID2 VID1 VID0 V CC (V)0 1 1 0 1 0 1 0.83750 1 1 0 1 1 0 0.82500 1 1 0 1 1 1 0.81250 1 1 1 0 0 0 0.80000 1 1 1 0 0 1 0.78750 1 1 1 0 1 0 0.77500 1 1 1 0 1 1 0.76250 1 1 1 1 0 0 0.75000 1 1 1 1 0 1 0.73750 1 1 1 1 1 0 0.72500 1 1 1 1 1 1 0.71251 0 0 0 0 0 0 0.70001 0 0 0 0 0 1 0.68751 0 0 0 0 1 0 0.67501 0 0 0 0 1 1 0.66251 0 0 0 1 0 0 0.65001 0 0 0 1 0 1 0.63751 0 0 0 1 1 0 0.62501 0 0 0 1 1 1 0.61251 0 0 1 0 0 0 0.60001 0 0 1 0 0 1 0.58751 0 0 1 0 1 0 0.57501 0 0 1 0 1 1 0.56251 0 0 1 1 0 0 0.55001 0 0 1 1 0 1 0.53751 0 0 1 1 1 0 0.52501 0 0 1 1 1 1 0.51251 0 1 0 0 0 0 0.50001 0 1 0 0 0 1 0.48751 0 1 0 0 1 0 0.47501 0 1 0 0 1 1 0.46251 0 1 0 1 0 0 0.45001 0 1 0 1 0 1 0.43751 0 1 0 1 1 0 0.42501 0 1 0 1 1 1 0.41251 0 1 1 0 0 0 0.40001 0 1 1 0 0 1 0.38751 0 1 1 0 1 0 0.37501 0 1 1 0 1 1 0.36251 0 1 1 1 0 0 0.35001 0 1 1 1 0 1 0.33751 0 1 1 1 1 0 0.32501 0 1 1 1 1 1 0.31251 1 0 0 0 0 0 0.30001 1 0 0 0 0 1 0.28751 1 0 0 0 1 0 0.2750Datasheet 87

Electrical SpecificationsTable 7-36.Voltage Identification Definition (Sheet 4 of 4)VID6 VID5 VID4 VID3 VID2 VID1 VID0 V CC (V)1 1 0 0 0 1 1 0.26251 1 0 0 1 0 0 0.25001 1 0 0 1 0 1 0.23751 1 0 0 1 1 0 0.22501 1 0 0 1 1 1 0.21251 1 0 1 0 0 0 0.20001 1 0 1 0 0 1 0.18751 1 0 1 0 1 0 0.17501 1 0 1 0 1 1 0.16251 1 0 1 1 0 0 0.15001 1 0 1 1 0 1 0.13751 1 0 1 1 1 0 0.12501 1 0 1 1 1 1 0.11251 1 1 0 0 0 0 0.10001 1 1 0 0 0 1 0.08751 1 1 0 0 1 0 0.07501 1 1 0 0 1 1 0.06251 1 1 0 1 0 0 0.05001 1 1 0 1 0 1 0.03751 1 1 0 1 1 0 0.02501 1 1 0 1 1 1 0.01251 1 1 1 0 0 0 0.00001 1 1 1 0 0 1 0.00001 1 1 1 0 1 0 0.00001 1 1 1 0 1 1 0.00001 1 1 1 1 0 0 0.00001 1 1 1 1 0 1 0.00001 1 1 1 1 1 0 0.00001 1 1 1 1 1 1 0.000088 Datasheet

Electrical SpecificationsTable 7-37.Market Segment Selection Truth Table for MSID[2:0]MSID[2] MSID[1] MSID[0] Description 1,2 Notes0 0 0 Reserved0 0 1 Reserved0 1 0 Reserved0 1 1 Reserved1 0 0 Standard Voltage (SV) 35-W Supported 31 0 1 Reserved1 1 0 Reserved1 1 1 ReservedNOTES:1. MSID[2:0] signals are provided to indicate the maximum platform capability to the processor.2. MSID is used on rPGA988A platforms only.3. Processors specified for use with a -1.9 m7.5 Reserved or Unused SignalsThe following are the general types of reserved (RSVD) signals and connectionguidelines: RSVD - these signals should not be connected RSVD_TP - these signals should be routed to a test point RSVD_NCTF - these signals are non-critical to function and may be left unconnectedArbitrary connection of these signals to V CC , V TT , V DDQ , V CCPLL , V AXG , V SS , or to anyother signal (including each other) may result in component malfunction orincompatibility with future processors. See Chapter 8 for a pin listing of the processorand the location of all reserved signals.For reliable operation, always connect unused inputs or bi-directional signals to anappropriate signal level. Unused active high inputs should be connected through aresistor to ground (V SS ). Unused outputs maybe left unconnected; however, this mayinterfere with some Test Access Port (TAP) functions, complicate debug probing, andprevent boundary scan testing. A resistor must be used when tying bi-directionalsignals to power or ground. When tying any signal to power or ground, a resistor willalso allow for system testability. Resistor values should be within ±20% of theimpedance of the baseboard trace, unless otherwise noted in the appropriate platformdesign guidelines. For details see Table 7-45.Datasheet 89

Electrical Specifications7.6 Signal GroupsSignals are grouped by buffer type and similar characteristics as listed in Table 7-38.The buffer type indicates which signaling technology and specifications apply to thesignals. All the differential signals, and selected DDR3 and Control Sideband signalshave On-Die Termination (ODT) resistors. There are some signals that do not have ODTand need to be terminated on the board.Table 7-38.Signal Groups 1 (Sheet 1 of 3)Signal GroupAlphaGroupTypeSignalsSystem Reference ClockDifferential (a) CMOS Input BCLK, BCLK#PEG_CLK, PEG_CLK#DPLL_REF_SSCLK, DPLL_REF_SSCLK#Differential (b) CMOS Output BCLK_ITP, BCLK_ITP#DDR3 Reference Clocks 2Differential (c) DDR3 Output SA_CK[1:0], SA_CK#[1:0]SB_CK[1:0], SB_CK#[1:0]DDR3 Command Signals 2Single Ended (d) DDR3 Output SA_RAS#, SB_RAS#, SA_CAS#, SB_CAS#SA_WE#, SB_WE#SA_MA[15:0], SB_MA[15:0]SA_BS[2:0], SB_BS[2:0]SA_DM[7:0], SB_DM[7:0]SM_DRAMRST#SA_CS#[1:0], SB_CS#[1:0]SA_ODT[1:0], SB_ODT[1:0]SA_CKE[1:0], SB_CKE[1:0]DDR3 Data Signals 2Single ended (e) DDR3 Bi-directional SA_DQ[63:0], SB_DQ[63:0]Differential (f) DDR3 Bi-directional SA_DQS[7:0], SA_DQS#[7:0]SB_DQS[7:0], SB_DQS#[7:0]TAP (ITP/XDP)Single Ended (g) CMOS Input TCK, TMS, TRST#Single Ended (ga) CMOS Input TDI,TDI_MSingle Ended (h) CMOS Open-DrainOutputSingle Ended (i) AsynchronousCMOS OutputTDO, TDO_MTAPPWRGOOD90 Datasheet

Electrical SpecificationsTable 7-38.Signal Groups 1 (Sheet 2 of 3)Signal GroupAlphaGroupTypeSignalsControl SidebandSingle Ended (ja) AsynchronousCMOS InputSingle Ended (jb) AsynchronousCMOS InputSingle Ended (k) AsynchronousCMOS OutputSingle Ended (l) Asynchronous GTLOutputSingle Ended (m) Asynchronous GTLInputV CCPWRGOOD_0 , V CCPWRGOOD_1 , V TTPWRGOODSM_DRAMPWROKRESET_OBS#PRDY#, THERMTRIP#PREQ#Single Ended (n) GTL Bi-directional CATERR#, BPM#[7:0]Single Ended (o) Asynchronous BidirectionalSingle Ended (p) Asynchronous GTLBi-directionalPECIPROCHOT#Single Ended (qa) CMOS Input PM_SYNC, PM_EXT_TS#[0], PM_EXT_TS#[1],CFG[17:0]Single Ended (qb) CMOS Input RSTIN#Single Ended (r) CMOS Output PROC_DPRSLPVRSingle Ended (s) CMOSBi-directionalVID[6]V TT_SELECTVID[5:3]/CSC[2:0]VID[2:0]/MSID[2:0]Single Ended (t) Analog Input COMP0, COMP1, COMP2, COMP3,SM_RCOMP[2:0], I SENSESingle Ended (ta) Analog Output SA_DIMM_VREFDQ 5 , SB_DIMM_VREFDQ 5Power/Ground/OtherSingle Ended (u) Power V CC , V TT0 , V TT1 , V CCPLL , V DDQ , V AXG , V 3 TT0_DDR ,3V DDQ_CK(v) Ground V SS , V SS_NCTF , DC_TEST_xx# 3(w)No Connect /TestPointRSVD, RSVD_TP, RSVD_NCTF(x)AsynchronousCMOS OutputPSI#(y) Sense Points V CC_SENSE , V SS_SENSE , V TT_SENSE , V SS_SENSE_VTT ,V AXG_SENSE , V SSAXG_SENSE(z) Other SKTOCC#, DBR#, PROC_DETECT 3 , VCAP0 3 ,VCAP 3 , VCAP2 3Datasheet 91

Electrical SpecificationsTable 7-38.Signal Groups 1 (Sheet 3 of 3)Signal GroupAlphaGroupTypeSignalsIntegrated GraphicsSingle Ended (aa) Analog Input GFX_IMONSingle Ended (ab) CMOS Output GFX_VID[6:0], GFX_VR_EN, GFX_DPRSLPVRPCI Express* GraphicsDifferential (ac) PCI Express Input PEG_RX[15:0], PEG_RX#[15:0]Differential (ad) PCI Express Output PEG_TX[15:0], PEG_TX#[15:0]Single Ended (ae) Analog Input PEG_ICOMP0, PEG_ICOMPI, PEG_RCOMP0,PEG_RBIASDMIDifferential (af) DMI Input DMI_RX[3:0], DMI_RX#[3:0]Differential (ag) DMI Output DMI_TX[3:0], DMI_TX#[3:0]Intel® FDISingle Ended (ah) CMOS Input FDI_FSYNC[1:0], FDI_LSYNC[1:0], FDI_INTDifferential (ai) Analog Output FDI_TX[7:0], FDI_TX#[7:0]NOTES:1. Refer to Chapter 6 for signal description details.2. SA and SB refer to DDR3 Channel A and DDR3 Channel B.3. These signals are only applicable for the BGA package4. These signals are only applicable for the rPGA988A package.All Control Sideband Asynchronous signals are required to be asserted/deasserted forat least eight BCLKs in order for the processor to recognize the proper signal state. SeeSection 7.10 for the DC specifications.7.7 Test Access Port (TAP) ConnectionDue to the voltage levels supported by other components in the Test Access Port (TAP)logic, Intel recommends the processor be first in the TAP chain, followed by any othercomponents within the system. A translation buffer should be used to connect to therest of the chain unless one of the other components is capable of accepting an input ofthe appropriate voltage. Two copies of each signal may be required with each driving adifferent voltage level.92 Datasheet

Electrical Specifications7.8 Absolute Maximum and Minimum RatingsTable 7-39 specifies absolute maximum and minimum ratings. At conditions outsidefunctional operation condition limits, but within absolute maximum and minimumratings, neither functionality nor long-term reliability can be expected. If a device isreturned to conditions within functional operation limits after having been subjected toconditions outside these limits (but within the absolute maximum and minimumratings) the device may be functional, but with its lifetime degraded depending onexposure to conditions exceeding the functional operation condition limits.At conditions exceeding absolute maximum and minimum ratings, neither functionalitynor long-term reliability can be expected. Moreover, if a device is subjected to theseconditions for any length of time it will either not function or its reliability will beseverely degraded when returned to conditions within the functional operatingcondition limits.Although the processor contains protective circuitry to resist damage from Electro-Static Discharge (ESD), precautions should always be taken to avoid high staticvoltages or electric fields.Table 7-39.Processor Absolute Minimum and Maximum RatingsSymbol Parameter Min Max Unit NotesV CC Processor Core voltage with respect to V SS -0.3 1.40 V 1, 2V TTV DDQVoltage for the memory controller and Shared Cache -0.3 1.40 Vwith respect to V SSProcessor I/O supply voltage for DDR3 with respect to -0.3 1.80 VV SSV CCPLL Processor PLL voltage with respect to V SS -0.3 1.98 VV AXGGraphics voltage with respect to V SSSVULV-0.3-0.31.551.55VNOTES:1. For functional operation, all processor electrical, signal quality, mechanical and thermal specifications mustbe satisfied.2. V CC and V AXG are VID based rails.7.9 Storage Conditions SpecificationsEnvironmental storage condition limits define the temperature and relative humidity towhich the device is exposed to while being stored in a moisture barrier bag. Thespecified storage conditions are for component level prior to board attach.Table 7-40 specifies absolute maximum and minimum storage temperature limits whichrepresent the maximum or minimum device condition beyond which damage, latent orotherwise, may occur. The table also specifies sustained storage temperature, relativehumidity, and time-duration limits. these limits specify the maximum or minimumDatasheet 93

Electrical Specificationsdevice storage conditions for a sustained period of time. At conditions outside sustainedlimits, but within absolute maximum and minimum ratings, quality and reliability maybe affected.Table 7-40.Storage Condition RatingsSymbol Parameter Min Max NotesT absolute storageT sustained storageRH sustained storageTime sustained storageThe non-operating device storage temperature.Damage (latent or otherwise) may occur whenexceeded for any length of time.The ambient storage temperature (in shippingmedia) for a sustained period of time)The maximum device storage relative humidityfor a sustained period of time.A prolonged or extended period of time; typicallyassociated with customer shelf life.-25°C 125°C 1, 2, 3, 4-5°C 40°C 5, 660% @ 24°C 6, 70 Months 6 Months 7NOTES:1. Refers to a component device that is not assembled in a board or socket and is not electrically connected toa voltage reference or I/O signal.2. Specified temperatures are not to exceed values based on data collected. Exceptions for surface mountreflow are specified by the applicable JEDEC standard. Non-adherence may affect processor reliability.3. T absolute storage applies to the unassembled component only and does not apply to the shipping media,moisture barrier bags, or desiccant.4. Component product device storage temperature qualification methods may follow JESD22-A119 (lowtemp) and JESD22-A103 (high temp) standards when applicable for volatile memory.5. Intel® branded products are specified and certified to meet the following temperature and humidity limitsthat are given as an example only (Non-Operating Temperature Limit: -40°C to 70°C and Humidity: 50%to 90%, non-condensing with a maximum wet bulb of 28°C.) Post board attach storage temperature limitsare not specified for non-Intel branded boards.6. The JEDEC J-JSTD-020 moisture level rating and associated handling practices apply to all moisturesensitive devices removed from the moisture barrier bag.7. Nominal temperature and humidity conditions and durations are given and tested within the constraintsimposed by T sustained storage and customer shelf life in applicable Intel boxes and bags.7.10 DC SpecificationsThe processor DC specifications in this section are defined at the processorpins, unless noted otherwise. See Chapter 8 for the processor pin listings andChapter 6 for signal definitions.The DC specifications for the DDR3 signals are listed in Table 7-44 Control Sidebandand Test Access Port (TAP) are listed in Table 7-45.Table 7-41 lists the DC specifications for the processor and are valid only while meetingspecifications for junction temperature, clock frequency, and input voltages. Careshould be taken to read all notes associated with each parameter.94 Datasheet

Electrical Specifications7.10.1 Voltage and Current SpecificationsTable 7-41.Processor Core (VCC) Active and Idle Mode DC Voltage and CurrentSpecificationsSymbol Parameter Segment Min Typ Max Unit NoteHFM_VIDVID Range for HighestFrequency ModeSVULV0.8000.7501.41.4V 1,2,7LFM_VIDVID Range for LowestFrequency ModeSVULV0.7750.7251.01.0V 1,2V CC V CC for processor core See Figure 7-13 and Figure 7-14 V 2, 3, 4I CCMAXMaximum ProcessorCore I CCSVULV4827A 5,7I CC_TDC Thermal Design I CC SVULVI CC_LFM I CC at LFM SVULVI C6 I CC at C6 Idle-state ULV 0.3 ATOL VID VID Tolerance See Figure 7-13 and Figure 7-14VR Step VID resolution 12.5 mVSLOPE LL Processor Loadline SVNon-VR LLcontributionULVNon-VR Loadline-0.9 mContribution for V CCNOTES:1. Unless otherwise noted, all specifications in this table are based on pre-silicon estimates and simulations orempirical data. These specifications will be updated with characterized data from silicon measurements ata later date.2. Each processor is programmed with a maximum valid voltage identification value (VID), which is set atmanufacturing and cannot be altered. Individual maximum VID values are calibrated during manufacturingsuch that two processors at the same frequency may have different settings within the VID range. Pleasenote this differs from the VID employed by the processor during a power or thermal management event(Intel Adaptive Thermal Monitor, Enhanced Intel SpeedStep Technology, or Low Power States).3. The voltage specification requirements are defined across VCC_SENSE and VSS_SENSE pins on the bottomside of the baseboard.4. Refer to Figure 7-13 and Figure 7-14 for the minimum, typical, and maximum V CC allowed for a givencurrent. The processor should not be subjected to any V CC and I CC combination wherein V CC exceedsV CC_MAX for a given current.5. Processor core VR to be designed to electrically support this current6. Processor core VR to be designed to thermally support this current indefinitely.7. This specification assumes that Intel Turbo Boost Technology with Intelligent Power Sharing is enabled.-1.9-3.03216188mA 6,7A 6Datasheet 95

Electrical SpecificationsFigure 7-13.Active V CC and I CC Loadline (PSI# Asserted)V C C [ V ]V C C m a xV C C , D Cm a xS l o p e = S L O P E L LV C C _ S E N S E , V S S _ S E N S E p in s .D i ffe r e n t ia l R e m o t e S e n s e r e q u i r e d .1 3 m V = R I P P L EV C C n o mV C C , D Cm inV C C m in± V C C T o le r a n c e= V R S t . P t . E r r o r0V C C S e t P o i n t E r r o r T o l e r a n c e i s p e r b e l o w :I C Cm a xI C C [ A ]T o l e r a n c e V C C - C O R E V I D V o l t a g e R a n g e- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -± [ V I D * 1 . 5 % - 3 m V ] V C C > 0 . 7 5 0 0 V± [ 1 1 . 5 m V - 3 m V ] 0 . 5 0 0 0 V < V C C = 0 . 7 5 0 0 VFigure 7-14.Active V CC and I CC Loadline (PSI# Not Asserted)V CC [V]V CC maxV CC, DC maxSlope = SLOPELLVCC_SENSE, VSS_SENSE pins.Differential Remote Sense required.10mV= RIPPLEVCC nomV CC, DC minV CC min± VCC Tolerance= VR St. Pt. Error0V CCSet Point Error Tolerance is per below:I CC maxI CC [A]Tolerance V CC- CORE VID Voltage Range--------------- -------------------------------------------------------± [VID*1.5%] V CC > 0.7500V± [11.5mV] 0.5000V < V CC =0.7500V96 Datasheet

Electrical SpecificationsTable 7-42.Processor Uncore I/O Buffer Supply DC Voltage and Current SpecificationsSymbol Parameter Min Typ Max Unit NoteV TTV DDQ (DC+AC)V CCPLLVoltage for the memory controller andshared cache defined at themotherboard Vtt pinfield viaVoltage for the memory controller andshared cache defined acrossVTT_SENSE and VSS_SENSE_VTTProcessor I/O supply voltage for DDR3(DC + AC specification)PLL supply voltage (DC + ACspecification)0.9975 1.05 1.1025 V 10.9765 1.05 1.1235 V 21.425 1.5 1.575 V1.710 1.8 1.890 VTOL TTV TT Tolerance defined at the socketmotherboard VTT pinfield viaV TT Tolerance defined acrossVTT_SENSE and VSS_SENSE_VTTDC: ±2%AC: ±3% including rippleDC: ±2%TOL DDQ VDDQ Tolerance DC= ±3%AC: ±5% including rippleAC= ±2%AC+DC= ±5%TOL CCPLL VCCPLL Tolerance AC+DC= ±5% %I CCMAX_VTTMax Current for V TT RailSVULVI CCMAX_VDDQ Max Current for V DDQ Rail - 3 A-1816% 1%2A 3I CCMAX_VDDQ_CK 0.2 A 4I CCMAX_VTT0_DDR 2.6 A 4I CCMAX_VCCPLL Max Current for V CCPLL Rail - 1.35 AI CCTDC_VTTI CCAVG_VDDQ(Standby)Thermal Design Current(TDC) for V TT RailSVULVAverage Current for V DDQ Rail duringStandby-1816A 3- 0.33 A 5NOTES:1. The voltage specification requirements are defined across at the socket motherboard pinfield vias on thebottom side of the baseboard.2. The voltage specification requirements are defined across VTT_SENSE and VSS_SENSE_VTT pins on thebottom side of the baseboard.3. Defined at nominal VTT voltage4. These are pre-silicon estimates and are subject to change.5. Based on junction temperature of 50°C.Datasheet 97

Electrical SpecificationsTable 7-43.Processor Graphics VID based (V AXG ) Supply DC Voltage and CurrentSpecificationsSymbol Parameter Min Typ Max Unit Note 1GFX_VIDVID Range for V AXGSVULVV AXG Graphics core voltage See Figure 7-15TOL AXG V AXG Tolerance See Figure 7-15Non-VR LLcontributionNon-VR Load Line Contribution forV AXGrPGABGALL AXG V AXG Loadline -7 mI CCMAX_VAXGI CCTDC_VAXGMax Current for IntegratedGraphics RailSVULVThermal Design Current(TDC) for Integrated Graphics RailSVULVNOTES:1. These are pre-silicon estimates and are subject to change.2. Minimum values assume Graphics Render C-state (RC6) is enabled.3. V AXG is a VID-Based rail driven by an Intel MVP6.5 compliant voltage regulator.4. This specification assumes Intel Turbo Boost Technology with Intelligent Power Sharing is enabled.0044.25Figure 7-15.V AXG /I AXG Static and Ripple Voltage Regulation--1.41.352212126mV 2,3,4A 4A 4V AXG [V]Slope = LLAXG at package VAXG_SENSE, and VSSAXG_SENSE pinsDifferential Remote Sense required.V AXG_MAX=V AXG_NOM+2.2%*GFX_VIDV AXG_NOM = GFX_VIDV AXG_MIN=V AXG_NOM-LL AXG*I CCMAX_VAXG-2.2%*GFX_VID+ /-V ID *2 .2%0VAXG Total tolerance window (GFX_DPRSLPVR de-asserted)DC (set point +LL tolerance)+ AC (ripple)for Standard and Enhanced Performance Frequency ModesI CCMAX_VAXGI AXG [A]98 Datasheet

Electrical SpecificationsTable 7-44.DDR3 Signal Group DC SpecificationsSymbolParameterAlphaGroupMin Typ Max Units Notes 1V IL Input Low Voltage (e,f) 0.43*V DDQ V 2,4V IH Input High Voltage (e,f) 0.57*V DDQ V 3V OL Output Low Voltage (c,d,e,f) (V DDQ / 2)* (R ON /(R ON +R VTT_TERM ))V OH Output High Voltage (c,d,e,f) V DDQ - ((V DDQ /2)* (R ON /(R ON +R VTT_TERM ))6V 4,6R ONR ONR ONR ONR ONR ONR ONR ONData ODTDDR3 Clock Buffer OnResistanceDDR3 Clock Buffer OnResistanceDDR3 Command BufferOn ResistanceDDR3 Command BufferOn ResistanceDDR3 Control Buffer OnResistanceDDR3 Control Buffer OnResistanceDDR3 Data Buffer OnResistanceDDR3 Data Buffer OnResistanceOn-Die Termination forData Signals21 31 521 36 516 24 520 31 521 31 520 31 521 31 521 36 5(d) 10213875169I LI Input Leakage Current ±500 ASM_RCOMP0 COMP Resistance (t) 99 100 101 8SM_RCOMP1 COMP Resistance (t) 24.7 24.9 25.1 8SM_RCOMP2 COMP Resistance (t) 128.7 130 131.3 8NOTES:1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.2. V IL is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical lowvalue.3. V IH is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical highvalue.4. V IH and V OH may experience excursions above V DDQ . However, input signal drivers must comply with thesignal quality specifications.5. This is the pull down driver resistance. Refer to processor I/O Buffer Models for I/V characteristics.6. R VTT_TERM is the termination on the DIMM and in not controlled by the Processor.7. The minimum and maximum values for these signals are programmable by BIOS to one of the two sets.8. COMP resistance must be provided on the system board with 1% resistors. COMP resistors are to V SS .Datasheet 99

Electrical SpecificationsTable 7-45.Control Sideband and TAP Signal Group DC SpecificationsSymbol Alpha Group Parameter Min Typ Max Units Notes 1,8V IL (m),(n),(p),(s) Input Low Voltage 0.64 * V TT V 2,3V IH (m),(n),(p),(s) Input High Voltage 0.76 * V TT V 2,3,5V IL (g) Input Low Voltage 0.25 * V TT V 2,3V IH (g) Input High Voltage 0.80 * V TT V 2,3,5V IL (ga) Input Low Voltage 0.4 * V TT V 2,3V IH (ga) Input High Voltage 0.75 * V TT V 2,3,5V IL (qa) Input Low Voltage 0.38 * V TT V 2,3V IH (qa) Input High Voltage 0.70 * V TT V 2,3,5V IL (ja),(qb) Input Low Voltage 0.25 * V TT V 2,3V IH (ja),(qb) Input High Voltage 0.75 * V TT V 2,3,5V IL (jb) Input Low Voltage 0.29 2,3V IH (jb) Input High Voltage 0.87 V 2,3,5V OLV OHR ON(k),(l),(n),(p),(r),(s),(ab),(h),(i)(k),(l),(n),(p),(r),(s),(ab),(i)(k),(l),(n),(p),(r),(s),(i)Output Low Voltage V TT * R ON /(R ON +R SYS_TERM )V 2,7Output High Voltage V TT V 2,5Buffer on Resistance 10 18R ON (ab) Buffer on Resistance 20-30 27-45I LI(ja),(jb),(m),(n),(p),(qa),(s),(t),(aa),(g)Input Leakage Current ±200 A 4I LI (qb) Input Leakage Current ±150 A 4COMP0 (t) COMP Resistance 49.4 49.9 50.4 6COMP1 (t) COMP Resistance 49.4 49.9 50.4 6COMP2 (t) COMP Resistance 19.8 20 20.2 6COMP3 (t) COMP Resistance 19.8 20 20.2 6NOTES:1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.2. The V TT referred to in these specifications refers to instantaneous V TT .3. Refer to the processor I/O Buffer Models for I/V characteristics.4. For V IN between 0 V and V TT . Measured when the driver is tristated.5. V IH and V OH may experience excursions above V TT . However, input signal drivers must comply with thesignal quality specifications.6. COMP resistance must be provided on the system board with 1% resistors. COMP resistors are to V SS .7. R SYS_TERM is the system termination on the signal.100 Datasheet

Electrical SpecificationsTable 7-46.PCI Express DC SpecificationsSymbolAlphaGroupParameter Min Typ Max Units Notes 1V TX-DIFF-p-p (ad) Differential Peak-to-Peak Tx VoltageSwingV TX_CM-AC-p (ad) Tx AC Peak Common Mode OutputVoltage (Gen 1 Only)Z TX-DIFF-DC (ad) DC Differential Tx Impedance(Gen 1 Only)0.8 1.2 V 320 mV 1,2,680 120 1,10Z RX-DC (ac) DC Common Mode Rx Impedance 40 60 1,8,9Z RX-DIFF-DC (ac) DC Differential Rx Impedance(Gen1 Only)V RX-DIFFp-p (ac) Differential Rx Input Peak-to-PeakVoltage (Gen 1 only)V RX_CM-AC-p (ac) Rx AC Peak Common Mode InputVoltage80 120 10.175 1.2 V 1,11150 mV 1,7PEG_ICOMPO (ae) Comp Resistance 49.5 50 50.5 4,5PEG_ICOMPI (ae) Comp Resistance 49.5 50 50.5 4,5PEG_RCOMPO (ae) Comp Resistance 49.5 50 50.5 4,5PEG_RBIAS (ae) Comp Resistance 742.5 750 757.5 4,5NOTES:1. Refer to the PCI Express Base Specification for more details.2. V TX-AC-CM-PP and V TX-AC-CM-P are defined in the PCI Express Base Specification. Measurement is made overat least 10^6 UI.3. As measured with compliance test load. Defined as 2*|V TXD+ - V TXD- |.4. COMP resistance must be provided on the system board with 1% resistors. COMP resistors are to V SS .5. PEG_ICOMPO, PEG_ICOMPI, PEG_RCOMPO are the same resistor6. RMS value.7. Measured at Rx pins into a pair of 50- terminations into ground. Common mode peak voltage is definedby the expression: max{|(Vd+ - Vd-) - V-CMDC|}.8. DC impedance limits are needed to guarantee Receiver detect.9. The Rx DC Common Mode Impedance must be present when the Receiver terminations are first enabled toensure that the Receiver Detect occurs properly. Compensation of this impedance can start immediatelyand the 15 Rx Common Mode Impedance (constrained by RLRX-CM to 50 ±20%) must be within thespecified range by the time Detect is entered.10. Low impedance defined during signaling. Parameter is captured for 5.0 GHz by RLTX-DIFF.Datasheet 101

Electrical SpecificationsTable 7-47.eDP DC SpecificationseDP_HPD#Symbol Parameter Min Typ Max Units Notes 4V IL Input Low Voltage -0.3 0.3 VV IH Input High Voltage 0.6 1.155 VeDP_AUX, eDP_AUX#V AUX-DIFFp-p (Tx)V AUX-DIFFp-p (Rx)eDP COMPsAUX Peak-to-Peak Voltage at thetransmitting deviceAUX Peak-to-Peak Voltage at thereceiving device0.39 1.38 10.32 1.36 V 1eDP_ICOMPO Comp Resistance 49.5 50 50.5 2,3eDP_ICOMPI Comp Resistance 49.5 50 50.5 2,3eDP_RCOMPO Comp Resistance 49.5 50 50.5 2,3eDP_RBIAS Comp Resistance 742.5 750 757.5 2,3NOTES:1. V AUX-DIFFp-p = 2*|V AUXP V AUXM |. Please refer to the VESA DisplayPort Standard specification for moredetails.2. COMP resistance must be provided on the system board with 1% resistors. See the applicable platformdesign guide for implementation details. COMP resistors are to V SS .3. eDP_ICOMPO, eDP_ICOMPI, eDP_RCOMPO are the same resistor.4. These are pre-silicon estimates and are subject to change.7.11 Platform Environmental Control Interface (PECI)DC SpecificationsPECI is an Intel proprietary interface that provides a communication channel betweenIntel processors and chipset components to external Adaptive Thermal Monitor devices.The processor contains a Digital Thermal Sensor (DTS) that reports a relative dietemperature as an offset from Thermal Control Circuit (TCC) activation temperature.Temperature sensors located throughout the die are implemented as analog-to-digitalconverters calibrated at the factory. PECI provides an interface for external devices toread the DTS temperature for thermal management and fan speed control. Moredetailed information may be found in the Platform Environment Control Interface(PECI) Specification.7.11.1 DC CharacteristicsThe PECI interface operates at a nominal voltage set by V TT . The set of DC electricalspecifications shown in Table 7-48 is used with devices normally operating from a V TTinterface supply. V TT nominal levels will vary between processor families. All PECIdevices will operate at the V TT level determined by the processor installed in thesystem. For specific nominal V TT levels, refer to Table 7-44.102 Datasheet

Electrical SpecificationsTable 7-48.PECI DC Electrical LimitsSymbol Definition and Conditions Min Max Units Notes 1V in Input Voltage Range -0.150 V TT VV hysteresis Hysteresis 0.1 * V TT N/A VV n Negative-edge Threshold Voltage 0.275 * V TT 0.500 * V TT VV p Positive-edge Threshold Voltage 0.550 * V TT 0.725 * V TT VI sourceI sinkI leak+I leak-High-Level Output Source(V OH = 0.75 * V TT )Low-Level Output Sink(V OL = 0.25 * V TT )High-Impedance State Leakage to V TT(V leak = V OL )High-Impedance Leakage to GND(V leak = V OH )-6.0 N/A mA0.5 1.0 mAN/A 100 µA 2N/A 100 µA 2C bus Bus Capacitance Per Node N/A 10 pFV noise Signal Noise Immunity above 300 MHz 0.1 * V TT N/A V p-pNOTES:1. V TT supplies the PECI interface. PECI behavior does not affect V TT min/max specifications.2. The leakage specification applies to powered devices on the PECI bus.7.11.2 Input Device HysteresisThe input buffers in both client and host models must use a Schmitt-triggered inputdesign for improved noise immunity. Use Figure 7-16 as a guide for input buffer design.Figure 7-16.Input Device HysteresisV TTDMaximum V PPECI High RangeMinimum V PMaximum V NMinimumHysteresisValid InputSignal RangeMinimum V NPECI Low RangePECI GroundDatasheet 103

Processor Pin and Signal Information8 Processor Pin and SignalInformation8.1 Processor Pin Assignments Provides a listing of all processor pins ordered alphabetically by pin name for therPGA988A and BGA1288 package respectively. Table 8-49 and Table 8-52 provides a listing of all processor pins orderedalphabetically by pin number for the rPGA988A and BGA1288 package respectively Figure 8-21, Figure 8-22, Figure 8-23, Figure 8-24 show the Top-Down view of therPGA988A pinmap. Figure 8-21, Figure 8-22, Figure 8-23, Figure 8-24 show the Top-Down view of theBGA1288 ballmap.104 Datasheet

Processor Pin and Signal InformationFigure 8-17.Socket-G (rPGA988A) Pinmap (Top View, Upper-Left Quadrant)VTT0SB_CK# [0]SB_CK[0]VDDQVSSSA_M A[15]SA_M A[6]SB_CK[1]VTT0 RSVD VSS SA_BS[2]VTT0 RSVD SB_M A[5] VDDQVSS RSVD_TP RSVD_TP SB_BS[2]VTT0SA_DQ[31]VSSSA_CKE[0]VTT0SA_DQS#[3]SA_DQ[30]VDDQVSSSA_DQS[3]SA_DQ[26]SA_DM [3]VTT0SA_DQ[27]VSSSA_DQ[24]VTT0VSSSA_DQ[29]SA_DQ[18]VTT1SA_DIM M_VREFVTT0 VTT0 VTT0 VTT0 VTT0 VTT0SA_DQ[23]SA_DQS#[2]SA_DQ[19]SA_DQ[22]VSSSB_DIM M_VREFRSVD_TP VSS VTT0 VSS VTT0 VSSSA_DQ[16]SA_DQS[2]VSSSA_DM [2]FDI_TX# [7]RSVDCOM P1VTT_SELECTVTT0 VTT0 VTT0 VTT0SA_DQ[21]VSSSA_DQ[17]SA_DQ[20]FDI_LSYNC[0]FDI_FSYNC[0]VSS RSVD_TP VTT0 VTT0 VTT0 VTT0 SA_DQ[9]SA_DQS[1]SA_DQS#[1]SA_DQ[11]Datasheet 105

Processor Pin and Signal InformationFigure 8-18.Socket-G (rPGA988A) Pinmap (Top View, Upper-Right Quadrant)2 3 2 2 2 1 2 0 19 18 17 16 15 14 13COM P3VSSAXG_SENSEVAXG VSS VAXG VAXG VSS VAXG PECISA_DQ[59]SA_DQS#[7]VSSVAXG_SENSEVAXG VSS VAXG VAXG VSS VAXG VSSSA_DQ[62]SA_DQS[7]GFX_VID[3] GFX_VID[1] VAXG VSS VAXG VAXG VSS VAXGPM _EXT_TS# [1]SA_DQ[63]VSSVSS GFX_VID[2] VAXG VSS VAXG VAXG VSS VAXGPM _EXT_TS# [0]VCCPWRGOOD_1SA_DM [7]GFX_VID[4] GFX_VID[0] VAXG VSS VAXG VAXG VSS VAXGVTTPWRGOODVSSSA_DQ[58]VSS RSVD VAXG VSS VAXG VAXG VSS VAXGPM _SYNCRSTIN#SA_DQ[61]BPM # [6] BPM # [1] VAXG VSS VAXG VAXG VSS VAXGTHERM TRIP#CATERR#SM _DRAM PWROKVSS BPM # [0] VAXG VSS VAXG VAXG VSS VAXG RSVD VSS RSVD_TPBPM # [7] BPM # [5] VAXG VSS VAXG VAXG VSS VAXG RSVD VTT0 VSS106 Datasheet

Processor Pin and Signal InformationFigure 8-19.Socket-G (rPGA988A) Pinmap (Top View, Lower-Left Quadrant)U V CC VCC V CC VCC VCC VC C V CC VC C VCC VC CT VSS VSS VSS VSS VSS VS S VSS VS S VSS VS SR V CC VCC V CC VCC VCC VC C V CC VC C VCC VC CP V CC VCC V CC VCC VCC VC C V CC VC C VCC VC CN VSS VSS VSS VSS VSS VS S VSS VS S VSS VS SMPE G_ TX# [1]PE G_T X[1 ]P EG_ T X# [2]PE G_T X[ 2]P EG_ T X[4 ]PE G_ TX#[3 ]P EG_ T X# [6 ]PE G_ TX[6]RS VDV CCP LLLVSSPE G_T X[0 ]P EG_ T X# [0]VSSP EG_ T X# [4 ]PE G_ TX[3]VSS RSVD VCC PLL V CCP LLKPE G_ RX# [0]VSSVSSPE G_T X#[5 ]P EG_ T X[5 ]VS SP EG_ T X# [8 ]PE G_ TX[8]VSSVT T1JPE G_ RX P EG_ RX PE G_ RX[0 ] #[1 ] # [2]VSSP EG_ T X# [7 ]VS S RS VD RSVD V TT 1 VT T1 VTT 1 VT T1 VTT 1 VT T1 VSS VT T1 VSS VT T1HVSSP EG_ RX[1 ]PE G_ RX[2 ]VSSP EG_ T X[7 ]PE G_ TX#[9 ]P EG_ T X# [1 0]VS S V TT 1 VS S VTT 1 V S SDM I_ T X# [3 ]V SS VTT 1 VT T1 VTT 1 V SSGPE G_ RX# [3]VSSPE G_ RX P EG_ RX[4 ] #[4 ]VSSPE G_ TX[9]P EG_ T X[1 0 ]VT T1 V TT 1 VT T1 R SVDDMI_ TX#[1 ]DM I_ T X FDI_ TX[ F DI_ T X[3 ] 4] # [4 ]V SSF DI_ T X[7 ]FDI_ TX#[ 7]FPE G_ RX P EG_ RX[3 ] #[5 ]PE G_ RX P EG_ RX PE G_ RX[8 ] [ 6] # [6 ]VS SP EG_ T X# [1 1]PE G_ TX[1 1]VSS VT T1 VSSDMI_ TX[1]DM I_ T X# [2 ]V SSF DI_ T X# [6 ]FDI_ TX[6 ]VSSFDI_ LSYN C[0 ]EVSSP EG_ RX[5 ]PE G_ RX# [8]VSS RS VD RSVD VSSPE G_ TX#[1 2 ]P EG_ T X[1 2 ]VT T1 VTT 1 V SSDM I_ T X[2 ]FDI_ TX#[0 ]VSSFDI_ TX[5 ]FDI_ T X#[5 ]V SSDPE G_ RX P EG_ RX# [7] [7 ]VSSP EG_ RX#[1 0 ]PE G_ RX[1 0 ]VS SP EG_ T X# [1 3]PE G_ TX[1 3]P EG_ T X#[1 4]VS SDM I_ T X[0 ]DMI_ TX#[0 ]DMI_ RX FDI_ TX[ F DI_ T X FDI_ TX[ FDI_ T X FDI_ TX[1 ] 0] # [1 ] 2 ] #[2 ] #[ 3]CRS VD _N CT FVSSPE G_ RX# [9]VSSPE G_ RX P EG_ RX# [1 2] [12 ]VSSVS SP EG_ T X[1 4 ]PE G_ TX#[1 5 ]P EG_ T X[1 5 ]V SSDMI_ RX# [1 ]V SSF DI_ T X[1 ]V SSVSSFDI_ TX[3 ]BARS VD _N CT FVSS _N CT FVSS_ N CT FRSVD _NC TFPE G_ RX P EG_ RX[9 ] #[1 1 ]RS VD _N CT FP EG_ RX[11 ]VSSP EG_ RX#[1 4 ]PE G_ RX P EG_ RX# [1 5] [15 ]PE G_ RX P EG_ RX PE G_ RC PE G_IC[1 4 ] #[1 3 ] O MP O OMP IVSSP EG_ RX[1 3]VSSPE G_ICOM POVSSDM I_R X[0]PE G_ RB DM I_R XIAS #[0 ]DMI_ RX DM I_R X[2 ] #[2 ]VSSDM I_R X DMI_ RX[3 ] # [3 ]VSS RSVD R SVD V SSRSVDR SVDDP LL_ RE F_ SSCLK3 5 34 3 3 32 3 1 30 29 28 27 2 6 25 2 4 23 2 2 21 2 0 19 1 8Datasheet 107

Processor Pin and Signal InformationFigure 8-20.Socket-G (rPGA988A) Pinmap (Top View, Lower-Right Quadrant)VTT0 RSVD VSSSA_BS[2]SA_MA[9]SB_MA[0]VSSSA_MA[12]VSS VDDQ UVTT0 RSVD SB_MA[5]VDDQVSSSB_MA[2]VDDQSA_MA[14]SA_MA[11]SA_MA[7]TVSSRS VD_TPRSVD_TPSB_BS[2]SB_MA[7]SB_MA[9]SB_MA[8]SB_MA[12]SB_MA[6]SB_MA[4]RVTT0SA_DQ[31]VSSSA_CKE[0]SA_CKE[1]SB_MA[14]VSSSB_MA[11]VSS VDDQ PVTT0SA_DQS#[3]SA_DQ[30]VDDQVSSSB_DQ[31]VDDQRSVD_TPRSVD_TPSB_MA[15]NVSSSA_DQS[3]SA_DQ[26]SA_DM[ SA_DQ[ SB_DQ3] 25] S[3]SB_DQ[ SB_CKE SB_CKE SB_DQ[30] [0] [1] 27]MVTT0SA_DQ[27]VSSSA_DQ[ SA_DQ[24] 28]VSSSB_DQS#[3]SB_DQ[26]VSS VDDQ LVTT0VSSSA_DQ[ SA_DQ[29] 18]VSSSB_DQ[28]SB_DQ[29]VSSSB_DQ[ SB_DM[25] 3]KSA_DIMM_VREFVTT0 VTT0 VTT0 VTT0 VTT0 VTT0SA_DQ[23]SA_DQS#[2]SA_DQ[19]SA_DQ[22]SB_DQ[ SB_DQ[ SB_DQ18] 24] S#[2]SB_DQ[ SB_DQ[ SB_DQ[19] 22] 23]JSB_DIM RSVD_TM_VREF PVSS VTT0 VSS VTT0 VSSSA_DQ[16]SA_DQS[2]VSSSA_DM[ SB_DQ[2] 16]VSSSB_DQS[2]SB_DM[2]VSS VDDQ HRSVD COMP1 VTT_SELECTVTT0 VTT0 VTT0 VTT0SA_DQ[21]VSSSA_DQ[ SA_DQ[17] 20]VSSSB_DQ[ SB_DQ[21] 15]VSSSB_DQ[17]SB_DQ[20]GFDI_FSYNC[0]VSSRSVD_TPVTT0 VTT0 VTT0 VTT0SA_DQ[9]SA_DQS[1]SA_DQS#[1]SA_DQ[11]SM_DRSB_DQ[ SB_DQAMRST13] S#[1]#SB_DQ[ SB_DQ[ SB_DQ[14] 10] 11]FFDI_FS PEG_CL RSVD_TYNC[1] K PVTT0 VSS VTT0 VSSSA_DQ[ SA_DQ[6] 12]VSSSA_DQ[ SA_DQ[14] 10]VSSSB_DQ[4]SB_DQS[1]VSSSB_DM[1]EFDI_LS PEG_CLYNC[1] K#RSVD VTT0 VTT0 VTT0 VTT0SA_DQ[5]VSSSA_DQ[ SA_DM[8] 1]VSSSB_DQS#[0]SB_DM[0]VSSSB_DQ[9]SB_DQ[8]DFDI_INTVSS RSVD VTT0 VTT0 VTT0 VTT0SA_DQ[1]SA_DQS#[0]SA_DQS[0]SA_DQ[ SA_DQ[ SB_DQ SB_DQ[2] 15] S[0] 7]SB_DQ[ SB_DQ[ RSVD_2] 12] NCTFCVSS BCLK# VTT_SENSEVTT0 VSS VTT0 VSSSA_DQ[ SA_DM[4] 0]VSSSA_DQ[13]VSSSB_DQ[0]VSSSB_DQ[3]VSS_NC VSS_NCTF TFBDPLL_REF _SSCLK#BCLKVSS_SENSE_VTTVTT0 VTT0 VTT0 VTT0SA_DQ[0]VSSSA_DQ[7]SA_DQ[3]SB_DQ[ SB_DQ[ SB_DQ[ RSVD_5] 1] 6] NCTFKEYA17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1108 Datasheet

Processor Pin and Signal InformationTable 8-49.rPGA988A Processor PinList by Pin NumberPinNumberA2A3KEYPin NameRSVD_NCTFBufferTypeDir.A4 SB_DQ[6] DDR3 I/OA5 SB_DQ[1] DDR3 I/OA6 SB_DQ[5] DDR3 I/OA7 SA_DQ[3] DDR3 I/OA8 SA_DQ[7] DDR3 I/OA9 VSS GNDA10 SA_DQ[0] DDR3 I/OA11 VTT0 REFA12 VTT0 REFA13 VTT0 REFA14 VTT0 REFA15VSS_SENSE_VTTAnalogA16 BCLK DIFFCLKA17A18A19A20DPLL_REF_SSCLK#DPLL_REF_SSCLKRSVDRSVDDIFFCLKDIFFCLKA21 DMI_RX#[3] DMI IA22 DMI_RX[3] DMI IA23 VSS GNDA24 DMI_RX#[0] DMI IA25 PEG_RBIAS Analog IA26 PEG_ICOMPO Analog IA27 VSS GNDA28 PEG_RX[13] PCIe IA29 VSS GNDA30 PEG_RX[15] PCIe IA31 PEG_RX#[15] PCIe IA32 PEG_RX[11] PCIe IA33RSVD_NCTFOIIITable 8-49.rPGA988A Processor PinList by Pin NumberPinNumberA34A35AA1AA2RSVD_NCTFVSS_NCTFRSVD_TPRSVD_TPAA3 SA_MA[3] DDR3 OAA4AA5RSVD_TPRSVD_TPAA6 SA_CK[0] DDR3 OAA7 SA_CK#[0] DDR3 OAA8 SA_MA[2] DDR3 OAA9 SA_MA[5] DDR3 OAA10 VSS GNDAA26 VCC REFAA27 VCC REFAA28 VCC REFAA29 VCC REFAA30 VCC REFAA31 VCC REFAA32 VCC REFAA33 VCC REFAA34 VCC REFAA35 VCC REFAB1 SB_BS[0] DDR3 OAB2 SA_BS[1] DDR3 OAB3 SA_RAS# DDR3 OAB4 VDDQ REFAB5 SB_MA[10] DDR3 OAB6 VSS GNDAB7 VDDQ REFAB8 SB_CS#[0] DDR3 OAB9Pin NameRSVDBufferTypeAB10 VTT0 REFAB26 VSS GNDAB27 VSS GNDAB28 VSS GNDAB29 VSS GNDDir.Datasheet 109

Processor Pin and Signal InformationTable 8-49.rPGA988A Processor PinList by Pin NumberTable 8-49.rPGA988A Processor PinList by Pin NumberPinNumberPin NameBufferTypeDir.PinNumberPin NameBufferTypeDir.AB30 VSS GNDAB31 VSS GNDAB32 VSS GNDAB33 VSS GNDAB34 VSS GNDAB35 VSS GNDAC1 VDDQ REFAC2 VSS GNDAC3 SA_BS[0] DDR3 OAC4 VSS GNDAC5 SB_CAS# DDR3 OAC6 SB_WE# DDR3 OAC7 SB_ODT[0] DDR3 OAC8 VSS GNDAC9 RSVDAC10 VTT0 REFAC26 VCC REFAC27 VCC REFAC28 VCC REFAC29 VCC REFAC30 VCC REFAC31 VCC REFAC32 VCC REFAC33 VCC REFAC34 VCC REFAC35 VCC REFAD1 SB_ODT[1] DDR3 OAD2 RSVD_TPAD3 RSVD_TPAD4 SA_MA[10] DDR3 OAD5 RSVD_TPAD6 SB_CS#[1] DDR3 OAD7 RSVD_TPAD8 SA_ODT[0] DDR3 OAD9 RSVD_TPAD10 VSS GNDAD26 VCC REFAD27 VCC REFAD28 VCC REFAD29 VCC REFAD30 VCC REFAD31 VCC REFAD32 VCC REFAD33 VCC REFAD34 VCC REFAD35 VCC REFAE1 SA_CAS# DDR3 OAE2 SA_CS#[0] DDR3 OAE3 RSVD_TPAE4 VDDQ REFAE5 RSVD_TPAE6 VSS GNDAE7 VDDQ REFAE8 SA_CS#[1] DDR3 OAE9 SA_WE# DDR3 OAE10 VTT0 REFAE26 VSS GNDAE27 VSS GNDAE28 VSS GNDAE29 VSS GNDAE30 VSS GNDAE31 VSS GNDAE32 VSS GNDAE33 VSS GNDAE34 VSS GNDAE35 VSS GNDAF1 VDDQ REFAF2 VSS GNDAF3 SB_DQ[32] DDR3 I/OAF4 VSS GNDAF5 SA_DQ[33] DDR3 I/OAF6 SA_DQ[36] DDR3 I/O110 Datasheet

Processor Pin and Signal InformationTable 8-49.rPGA988A Processor PinList by Pin NumberTable 8-49.rPGA988A Processor PinList by Pin NumberPinNumberPin NameBufferTypeDir.PinNumberPin NameBufferTypeDir.AF7 SB_MA[13] DDR3 OAF8 VSS GNDAF9 SA_ODT[1] DDR3 OAF10 VTT0 REFAF26 VCC REFAF27 VCC REFAF28 VCC REFAF29 VCC REFAF30 VCC REFAF31 VCC REFAF32 VCC REFAF33 VCC REFAF34 VCC REFAF35 VCC REFAG1 SB_DQ[33] DDR3 I/OAG2 SB_DQS[4] DDR3 I/OAG3 SB_DQ[37] DDR3 I/OAG4 SB_DQ[36] DDR3 I/OAG5 SA_DQ[37] DDR3 I/OAG6 SA_DM[4] DDR3 OAG7 RSVD_TPAG8 SA_MA[13] DDR3 OAG9 RSVDAG10 VSS GNDAG26 VCC REFAG27 VCC REFAG28 VCC REFAG29 VCC REFAG30 VCC REFAG31 VCC REFAG32 VCC REFAG33 VCC REFAG34 VCC REFAG35 VCC REFAH1 SB_DM[4] DDR3 OAH2 SB_DQS#[4] DDR3 I/OAH3 VSS GNDAH4 SB_DQ[39] DDR3 I/OAH5 SA_DQ[32] DDR3 I/OAH6 VSS GNDAH7 SA_DQS#[4] DDR3 I/OAH8 SA_DQS[4] DDR3 I/OAH9 VSS GNDAH10 VTT0 REFAH11 VTT0 REFAH12 VTT0 REFAH13 VSS GNDAH14 VTT0 REFAH15 RSVDAH16 VAXG REFAH17 VSS GNDAH18 VAXG REFAH19 VAXG REFAH20 VSS GNDAH21 VAXG REFAH22 BPM#[5] GTL I/OAH23 BPM#[7] GTL I/OAH24 SKTOCC#AH25 RSVDAH26 VSS GNDAH27 VSS GNDAH28 VSS GNDAH29 VSS GNDAH30 VSS GNDAH31 VSS GNDAH32 VSS GNDAH33 VSS GNDAH34 VSS GNDAH35 VSS GNDAJ1 VDDQ REFAJ2 VSS GNDAJ3 SB_DQ[34] DDR3 I/ODatasheet 111

Processor Pin and Signal InformationTable 8-49.rPGA988A Processor PinList by Pin NumberTable 8-49.rPGA988A Processor PinList by Pin NumberPinNumberPin NameBufferTypeDir.PinNumberPin NameBufferTypeDir.AJ4 SB_DQ[38] DDR3 I/OAJ5 VSS GNDAJ6 SA_DQ[39] DDR3 I/OAJ7 SA_DQ[38] DDR3 I/OAJ8 VSS GNDAJ9 SA_DQ[41] DDR3 I/OAJ10 SA_DQ[40] DDR3 I/OAJ11 VSS GNDAJ12 RSVD_TPAJ13 RSVD_TPAJ14 VSS GNDAJ15 RSVDAJ16 VAXG REFAJ17 VSS GNDAJ18 VAXG REFAJ19 VAXG REFAJ20 VSS GNDAJ21 VAXG REFAJ22 BPM#[0] GTL I/OAJ23 VSS GNDAJ24 BPM#[3] GTL I/OAJ25 BPM#[4] GTL I/OAJ26 RSVDAJ27 RSVDAJ28 CFG[11] CMOS IAJ29 CFG[15] CMOS IAJ30 CFG[16] CMOS IAJ31 VSS GNDAJ32 CFG[14] CMOS IAJ33 RSVDAJ34 VCC_SENSE Analog OAJ35 VSS_SENSE Analog OAK1 SB_DQ[35] DDR3 I/OAK2 SB_DQ[45] DDR3 I/OAK3 SB_DQ[40] DDR3 I/OAK4 SB_DQ[41] DDR3 I/OAK5 SB_DQ[44] DDR3 I/OAK6 SA_DQ[34] DDR3 I/OAK7 SA_DQ[35] DDR3 I/OAK8 SA_DQ[44] DDR3 I/OAK9 SA_DQS#[5] DDR3 I/OAK10 SA_DQS[5] DDR3 I/OAK11 SA_DQ[46] DDR3 I/OAK12 SA_DQ[43] DDR3 I/OAK13SM_DRAMPWROKDDR3AK14 CATERR# GTL I/OAK15 THERMTRIP# AsyncGTLAK16 VAXG REFAK17 VSS GNDAK18 VAXG REFAK19 VAXG REFAK20 VSS GNDAK21 VAXG REFAK22 BPM#[1] GTL I/OAK23 BPM#[6] GTL I/OAK24 BPM#[2] GTL I/OAK25 VSS GNDAK26RSVD_TPAK27 VSS GNDAK28 CFG[10] CMOS IAK29 VSS GNDAK30 CFG[17] CMOS IAK31 CFG[9] CMOS IAK32 CFG[8] CMOS IAK33 VID[1] CMOS OAK34 VID[2] CMOS OAK35 VID[0] CMOS OAL1 SM_RCOMP[0] Analog IAL2 SB_DM[5] DDR3 OAL3 VSS GNDAL4 SB_DQS#[5] DDR3 I/OOO112 Datasheet

Processor Pin and Signal InformationTable 8-49.rPGA988A Processor PinList by Pin NumberTable 8-49.rPGA988A Processor PinList by Pin NumberPinNumberPin NameBufferTypeDir.PinNumberPin NameBufferTypeDir.AL5 SB_DQS[5] DDR3 I/OAL6 VSS GNDAL7 SA_DQ[45] DDR3 I/OAL8 SA_DQ[47] DDR3 I/OAL9 VSS GNDAL10 SA_DQ[42] DDR3 I/OAL11 SA_DQ[51] DDR3 I/OAL12 VSS GNDAL13 SA_DQ[61] DDR3 I/OAL14 RSTIN# CMOS IAL15 PM_SYNC CMOS IAL16 VAXG REFAL17 VSS GNDAL18 VAXG REFAL19 VAXG REFAL20 VSS GNDAL21 VAXG REFAL22 RSVDAL23 VSS GNDAL24 RSVDAL25 RSVDAL26 RSVD_TPAL27 RSVDAL28 RSVDAL29 RSVDAL30 CFG[4] CMOS IAL31 VSS GNDAL32 CFG[3] CMOS IAL33 CSC[1]/VID[4] CMOS I/OAL34 VSS GNDAL35 CSC[0]/VID[3] CMOS I/OAM1 SM_RCOMP[1] Analog IAM2 VSS GNDAM3 SB_DQ[47] DDR3 I/OAM4 SB_DQ[46] DDR3 I/OAM5 VSS GNDAM6 SB_DQ[42] DDR3 I/OAM7 SA_DM[5] DDR3 OAM8 VSS GNDAM9 SA_DQ[52] DDR3 I/OAM10 SA_DQ[49] DDR3 I/OAM11 VSS GNDAM12 SA_DQ[56] DDR3 I/OAM13 SA_DQ[58] DDR3 I/OAM14 VSS GNDAM15 VTTPWRGOOD AsyncCMOSAM16 VAXG REFAM17 VSS GNDAM18 VAXG REFAM19 VAXG REFAM20 VSS GNDAM21 VAXG REFAM22 GFX_VID[0] CMOS OAM23 GFX_VID[4] CMOS OAM24 GFX_IMON Analog IAM25 VSS GNDAM26 TAPPWRGOOD AsyncCMOSAM27 VSS GNDAM28 CFG[1] CMOS IAM29 VSS GNDAM30 CFG[0] CMOS IAM31 CFG[5] CMOS IAM32 CFG[7] CMOS IAM33 CSC[2]/VID[5] CMOS I/OAM34PROC_DPRSLPVRCMOSAM35 VID[6] CMOS OAN1 SM_RCOMP[2] Analog IAN2 SB_DQ[43] DDR3 I/OAN3 SB_DQ[53] DDR3 I/OAN4 SB_DQ[52] DDR3 I/OIOO113 Datasheet

Processor Pin and Signal InformationTable 8-49.rPGA988A Processor PinList by Pin NumberTable 8-49.rPGA988A Processor PinList by Pin NumberPinNumberPin NameBufferTypeDir.PinNumberPin NameBufferTypeDir.AN5 SB_DQ[49] DDR3 I/OAN6 SB_DQ[51] DDR3 I/OAN7 SB_DQ[56] DDR3 I/OAN8 SA_DQ[48] DDR3 I/OAN9 SA_DQ[53] DDR3 I/OAN10 SA_DM[6] DDR3 OAN11 SA_DQS[6] DDR3 I/OAN12 SA_DQ[57] DDR3 I/OAN13 SA_DM[7] DDR3 OAN14AN15VCCPWRGOOD_1PM_EXT_TS#[0]AsyncCMOSCMOSAN16 VAXG REFAN17 VSS GNDAN18 VAXG REFAN19 VAXG REFAN20 VSS GNDAN21 VAXG REFAN22 GFX_VID[2] CMOS OAN23 VSS GNDAN24 GFX_VID[6] CMOS OAN25 DBR# OAN26 PROCHOT# AsyncGTLAN27VCCPWRGOOD_0AsyncCMOSAN28 TCK CMOS IAN29 CFG[6] CMOS IAN30 CFG[12] CMOS IAN31 VSS GNDAN32 CFG[13] CMOS IAN33 PSI# AsyncCMOSAN34 VSS GNDAN35 ISENSE Analog IAP1RSVD_NCTFAP2 VSS GNDIII/OIOAP3 SB_DQ[48] DDR3 I/OAP4 VSS GNDAP4 VSS GNDAP5 SB_DQS[6] DDR3 I/OAP6 SB_DQ[57] DDR3 I/OAP7 VSS GNDAP8 SB_DQ[58] DDR3 I/OAP9 SB_DQ[61] DDR3 I/OAP10 VSS GNDAP11 SA_DQS#[6] DDR3 I/OAP12 SA_DQ[55] DDR3 I/OAP13 VSS GNDAP14 SA_DQ[63] DDR3 I/OAP15PM_EXT_TS#[1]CMOSAP16 VAXG REFAP17 VSS GNDAP18 VAXG REFAP19 VAXG REFAP20 VSS GNDAP21 VAXG REFAP22 GFX_VID[1] CMOS OAP23 GFX_VID[3] CMOS OAP24 GFX_VID[5] CMOS OAP25RSVDAP26 RESET_OBS# AsyncCMOSAP27 PREQ# AsyncGTLAP28 TMS CMOS IAP29 TDO_M CMOS OAP30RSVDAP31 CFG[2] CMOS IAP32AP33RSVDRSVDAP34 VSS GNDAP35RSVD_NCTFIOIDatasheet 114

Processor Pin and Signal InformationTable 8-49.rPGA988A Processor PinList by Pin NumberTable 8-49.rPGA988A Processor PinList by Pin NumberPinNumberPin NameBufferTypeDir.PinNumberPin NameBufferTypeDir.AR1AR2RSVD_NCTFRSVD_NCTFAR3 VSS GNDAR4 SB_DM[6] DDR3 OAR5 SB_DQS#[6] DDR3 I/OAR6 VSS GNDAR7 SB_DQS[7] DDR3 I/OAR8 SB_DQS#[7] DDR3 I/OAR9 VSS GNDAR10 SB_DQ[62] DDR3 I/OAR11 SA_DQ[50] DDR3 I/OAR12 VSS GNDAR13 SA_DQS[7] DDR3 I/OAR14 SA_DQ[62] DDR3 I/OAR15 VSS GNDAR16 VAXG REFAR17 VSS GNDAR18 VAXG REFAR19 VAXG REFAR20 VSS GNDAR21 VAXG REFAR22 VAXG_SENSE Analog OAR23 VSS GNDAR24 VSS GNDAR25 GFX_VR_EN CMOS OAR26 VSS GNDAR27 TDO CMOS OAR28 VSS GNDAR29 TDI_M CMOS IAR30 BCLK_ITP DIFFCLKAR31 VSS GNDAR32AR33AR34AR35AT1RSVDRSVDVSS_NCTFRSVD_NCTFVSS_NCTFOAT2AT3RSVD_TPRSVD_NCTFAT4 SB_DQ[50] DDR3 I/OAT5 SB_DQ[54] DDR3 I/OAT6 SB_DQ[55] DDR3 I/OAT7 SB_DQ[60] DDR3 I/OAT8 SB_DM[7] DDR3 OAT9 SB_DQ[59] DDR3 I/OAT10 SB_DQ[63] DDR3 I/OAT11 SA_DQ[54] DDR3 I/OAT12 SA_DQ[60] DDR3 I/OAT13 SA_DQS#[7] DDR3 I/OAT14 SA_DQ[59] DDR3 I/OAT15 PECI Async I/OAT16 VAXG REFAT17 VSS GNDAT18 VAXG REFAT19 VAXG REFAT20 VSS GNDAT21 VAXG REFAT22VSSAXG_SENSEAnalogAT23 COMP3 Analog IAT24 COMP2 Analog IAT25 GFX_DPRSLPVR CMOS OAT26 COMP0 Analog IAT27 TRST# CMOS IAT28 PRDY# AsyncGTLAT29 TDI CMOS IAT30 BCLK_ITP# DIFFCLKAT31AT32AT33AT34AT35RSVDRSVDRSVD_NCTFRSVD_NCTFVSS_NCTFOOO115 Datasheet

Processor Pin and Signal InformationTable 8-49.rPGA988A Processor PinList by Pin NumberTable 8-49.rPGA988A Processor PinList by Pin NumberPinNumberPin NameBufferTypeDir.PinNumberPin NameBufferTypeDir.B1B2VSS_NCTFVSS_NCTFB3 SB_DQ[3] DDR3 I/OB4 VSS GNDB5 SB_DQ[0] DDR3 I/OB6 VSS GNDB7 SA_DQ[13] DDR3 I/OB8 VSS GNDB9 SA_DM[0] DDR3 OB10 SA_DQ[4] DDR3 I/OB11 VSS GNDB12 VTT0 REFB13 VSS GNDB14 VTT0 REFB15 VTT_SENSE Analog OB16 BCLK# DIFFCLKB17 VSS GNDB18 VSS GNDB19B20RSVDRSVDB21 VSS GNDB22 DMI_RX#[2] DMI IB23 DMI_RX[2] DMI IB24 DMI_RX[0] DMI IB25 VSS GNDB26 PEG_ICOMPI Analog IB27 PEG_RCOMPO Analog IB28 PEG_RX#[13] PCIe IB29 PEG_RX[14] PCIe IB30 PEG_RX#[14] PCIe IB31 VSS GNDB32 PEG_RX#[11] PCIe IB33 PEG_RX[9] PCIe IB34B35C1VSS_NCTFRSVD_NCTFRSVD_NCTFIC2 SB_DQ[12] DDR3 I/OC3 SB_DQ[2] DDR3 I/OC4 SB_DQ[7] DDR3 I/OC5 SB_DQS[0] DDR3 I/OC6 SA_DQ[15] DDR3 I/OC7 SA_DQ[2] DDR3 I/OC8 SA_DQS[0] DDR3 I/OC9 SA_DQS#[0] DDR3 I/OC10 SA_DQ[1] DDR3 I/OC11 VTT0 REFC12 VTT0 REFC13 VTT0 REFC14 VTT0 REFC15 RSVDC16 VSS GNDC17 FDI_INT CMOS IC18 FDI_TX[3] FDI OC19 VSS GNDC20 VSS GNDC21 FDI_TX[1] FDI OC22 VSS GNDC23 DMI_RX#[1] DMI IC24 VSS GNDC25 PEG_TX[15] PCIe OC26 PEG_TX#[15] PCIe OC27 PEG_TX[14] PCIe OC28 VSS GNDC29 VSS GNDC30 PEG_RX[12] PCIe IC31 PEG_RX#[12] PCIe IC32 VSS GNDC33 PEG_RX#[9] PCIe IC34 VSS GNDC35 RSVD_NCTFD1 SB_DQ[8] DDR3 I/OD2 SB_DQ[9] DDR3 I/ODatasheet 116

Processor Pin and Signal InformationTable 8-49.rPGA988A Processor PinList by Pin NumberTable 8-49.rPGA988A Processor PinList by Pin NumberPinNumberPin NameBufferTypeDir.PinNumberPin NameBufferTypeDir.D3 VSS GNDD4 SB_DM[0] DDR3 OD5 SB_DQS#[0] DDR3 I/OD6 VSS GNDD7 SA_DM[1] DDR3 OD8 SA_DQ[8] DDR3 I/OD9 VSS GNDD10 SA_DQ[5] DDR3 I/OD11 VTT0 REFD12 VTT0 REFD13 VTT0 REFD14 VTT0 REFD15RSVDD16 PEG_CLK# DIFFCLKD17 FDI_LSYNC[1] CMOS ID18 FDI_TX#[3] FDI OD19 FDI_TX#[2] FDI OD20 FDI_TX[2] FDI OD21 FDI_TX#[1] FDI OD22 FDI_TX[0] FDI OD23 DMI_RX[1] DMI ID24 DMI_TX#[0] DMI OD25 DMI_TX[0] DMI OD26 VSS GNDD27 PEG_TX#[14] PCIe OD28 PEG_TX[13] PCIe OD29 PEG_TX#[13] PCIe OD30 VSS GNDD31 PEG_RX[10] PCIe ID32 PEG_RX#[10] PCIe ID33 VSS GNDD34 PEG_RX[7] PCIe ID35 PEG_RX#[7] PCIe IE1 SB_DM[1] DDR3 OE2 VSS GNDE3 SB_DQS[1] DDR3 I/OIE4 SB_DQ[4] DDR3 I/OE5 VSS GNDE6 SA_DQ[10] DDR3 I/OE7 SA_DQ[14] DDR3 I/OE8 VSS GNDE9 SA_DQ[12] DDR3 I/OE10 SA_DQ[6] DDR3 I/OE11 VSS GNDE12 VTT0 REFE13 VSS GNDE14 VTT0 REFE15RSVD_TPE16 PEG_CLK DIFFCLKE17 FDI_FSYNC[1] CMOS IE18 VSS GNDE19 FDI_TX#[5] FDI OE20 FDI_TX[5] FDI OE21 VSS GNDE22 FDI_TX#[0] FDI OE23 DMI_TX[2] DMI OE24 VSS GNDE25 VTT1 REFE26 VTT1 REFE27 PEG_TX[12] PCIe OE28 PEG_TX#[12] PCIe OE29 VSS GNDE30E31RSVDRSVDE32 VSS GNDE33 PEG_RX#[8] PCIe IE34 PEG_RX[5] PCIe IE35 VSS GNDF1 SB_DQ[11] DDR3 I/OF2 SB_DQ[10] DDR3 I/OF3 SB_DQ[14] DDR3 I/OF4 SB_DQS#[1] DDR3 I/OI117 Datasheet

Processor Pin and Signal InformationTable 8-49.rPGA988A Processor PinList by Pin NumberTable 8-49.rPGA988A Processor PinList by Pin NumberPinNumberPin NameBufferTypeDir.PinNumberPin NameBufferTypeDir.F5 SB_DQ[13] DDR3 I/OF6 SM_DRAMRST# DDR3 OF7 SA_DQ[11] DDR3 I/OF8 SA_DQS#[1] DDR3 I/OF9 SA_DQS[1] DDR3 I/OF10 SA_DQ[9] DDR3 I/OF11 VTT0 REFF12 VTT0 REFF13 VTT0 REFF14 VTT0 REFF15 RSVD_TPF16 VSS GNDF17 FDI_FSYNC[0] CMOS IF18 FDI_LSYNC[0] CMOS IF19 VSS GNDF20 FDI_TX[6] FDI OF21 FDI_TX#[6] FDI OF22 VSS GNDF23 DMI_TX#[2] DMI OF24 DMI_TX[1] DMI OF25 VSS GNDF26 VTT1 REFF27 VSS GNDF28 PEG_TX[11] PCIe OF29 PEG_TX#[11] PCIe OF30 VSS GNDF31 PEG_RX#[6] PCIe IF32 PEG_RX[6] PCIe IF33 PEG_RX[8] PCIe IF34 PEG_RX#[5] PCIe IF35 PEG_RX[3] PCIe IG1 SB_DQ[20] DDR3 I/OG2 SB_DQ[17] DDR3 I/OG3 VSS GNDG4 SB_DQ[15] DDR3 I/OG5 SB_DQ[21] DDR3 I/OG6 VSS GNDG7 SA_DQ[20] DDR3 I/OG8 SA_DQ[17] DDR3 I/OG9 VSS GNDG10 SA_DQ[21] DDR3 I/OG11 VTT0 REFG12 VTT0 REFG13 VTT0 REFG14 VTT0 REFG15 VTT_SELECT CMOS OG16 COMP1 Analog IG17 RSVDG18 FDI_TX#[7] FDI OG19 FDI_TX[7] FDI OG20 VSS GNDG21 FDI_TX#[4] FDI OG22 FDI_TX[4] FDI OG23 DMI_TX[3] DMI OG24 DMI_TX#[1] DMI OG25 RSVDG26 VTT1 REFG27 VTT1 REFG28 VTT1 REFG29 PEG_TX[10] PCIe OG30 PEG_TX[9] PCIe OG31 VSS GNDG32 PEG_RX#[4] PCIe IG33 PEG_RX[4] PCIe IG34 VSS GNDG35 PEG_RX#[3] PCIe IH1 VDDQ REFH2 VSS GNDH3 SB_DM[2] DDR3 OH4 SB_DQS[2] DDR3 I/OH5 VSS GNDH6 SB_DQ[16] DDR3 I/O118 Datasheet

Processor Pin and Signal InformationTable 8-49.rPGA988A Processor PinList by Pin NumberTable 8-49.rPGA988A Processor PinList by Pin NumberPinNumberPin NameBufferTypeDir.PinNumberPin NameBufferTypeDir.H7 SA_DM[2] DDR3 OH8 VSS GNDH9 SA_DQS[2] DDR3 I/OH10 SA_DQ[16] DDR3 I/OH11 VSS GNDH12 VTT0 REFH13 VSS GNDH14 VTT0 REFH15 VSS GNDH16 RSVD_TPH17 RSVDH18 VSS GNDH19 VTT1 REFH20 VTT1 REFH21 VTT1 REFH22 VSS GNDH23 DMI_TX#[3] DMI OH24 VSS GNDH25 VTT1 REFH26 VSS GNDH27 VTT1 REFH28 VSS GNDH29 PEG_TX#[10] PCIe OH30 PEG_TX#[9] PCIe OH31 PEG_TX[7] PCIe OH32 VSS GNDH33 PEG_RX[2] PCIe IH34 PEG_RX[1] PCIe IH35 VSS GNDJ1 SB_DQ[23] DDR3 I/OJ2 SB_DQ[22] DDR3 I/OJ3 SB_DQ[19] DDR3 I/OJ4 SB_DQS#[2] DDR3 I/OJ5 SB_DQ[24] DDR3 I/OJ6 SB_DQ[18] DDR3 I/OJ7 SA_DQ[22] DDR3 I/OJ8 SA_DQ[19] DDR3 I/OJ9 SA_DQS#[2] DDR3 I/OJ10 SA_DQ[23] DDR3 I/OJ11 VTT0 REFJ12 VTT0 REFJ13 VTT0 REFJ14 VTT0 REFJ15 VTT0 REFJ16 VTT0 REFJ17 RSVDJ18 VTT1 REFJ19 VSS GNDJ20 VTT1 REFJ21 VSS GNDJ22 VTT1 REFJ23 VTT1 REFJ24 VTT1 REFJ25 VTT1 REFJ26 VTT1 REFJ27 VTT1 REFJ28 RSVDJ29 RSVDJ30 VSS GNDJ31 PEG_TX#[7] PCIe OJ32 VSS GNDJ33 PEG_RX#[2] PCIe IJ34 PEG_RX#[1] PCIe IJ35 PEG_RX[0] PCIe IK1 SB_DM[3] DDR3 OK2 SB_DQ[25] DDR3 I/OK3 VSS GNDK4 SB_DQ[29] DDR3 I/OK5 SB_DQ[28] DDR3 I/OK6 VSS GNDK7 SA_DQ[18] DDR3 I/OK8 SA_DQ[29] DDR3 I/ODatasheet 119

Processor Pin and Signal InformationTable 8-49.rPGA988A Processor PinList by Pin NumberTable 8-49.rPGA988A Processor PinList by Pin NumberPinNumberPin NameBufferTypeDir.PinNumberPin NameBufferTypeDir.K9 VSS GNDK10 VTT0 REFK26 VTT1 REFK27 VSS GNDK28 PEG_TX[8] PCIe OK29 PEG_TX#[8] PCIe OK30 VSS GNDK31 PEG_TX[5] PCIe OK32 PEG_TX#[5] PCIe OK33 VSS GNDK34 VSS GNDK35 PEG_RX#[0] PCIe IL1 VDDQ REFL2 VSS GNDL3 SB_DQ[26] DDR3 I/OL4 SB_DQS#[3] DDR3 I/OL5 VSS GNDL6 SA_DQ[28] DDR3 I/OL7 SA_DQ[24] DDR3 I/OL8 VSS GNDL9 SA_DQ[27] DDR3 I/OL10 VTT0 REFL26 VCCPLL REFL27 VCCPLL REFL28 RSVDL29 VSS GNDL30 PEG_TX[3] PCIe OL31 PEG_TX#[4] PCIe OL32 VSS GNDL33 PEG_TX#[0] PCIe OL34 PEG_TX[0] PCIe OL35 VSS GNDM1 SB_DQ[27] DDR3 I/OM2 SB_CKE[1] DDR3 OM3 SB_CKE[0] DDR3 OM4 SB_DQ[30] DDR3 I/OM5 SB_DQS[3] DDR3 I/OM6 SA_DQ[25] DDR3 I/OM7 SA_DM[3] DDR3 OM8 SA_DQ[26] DDR3 I/OM9 SA_DQS[3] DDR3 I/OM10 VSS GNDM26 VCCPLL REFM27 RSVDM28 PEG_TX[6] PCIe OM29 PEG_TX#[6] PCIe OM30 PEG_TX#[3] PCIe OM31 PEG_TX[4] PCIe OM32 PEG_TX[2] PCIe OM33 PEG_TX#[2] PCIe OM34 PEG_TX[1] PCIe OM35 PEG_TX#[1] PCIe ON1 SB_MA[15] DDR3 ON2 RSVD_TPN3 RSVD_TPN4 VDDQ REFN5 SB_DQ[31] DDR3 I/ON6 VSS GNDN7 VDDQ REFN8 SA_DQ[30] DDR3 I/ON9 SA_DQS#[3] DDR3 I/ON10 VTT0 REFN26 VSS GNDN27 VSS GNDN28 VSS GNDN29 VSS GNDN30 VSS GNDN31 VSS GNDN32 VSS GNDN33 VSS GNDN34 VSS GNDN35 VSS GND120 Datasheet

Processor Pin and Signal InformationTable 8-49.rPGA988A Processor PinList by Pin NumberTable 8-49.rPGA988A Processor PinList by Pin NumberPinNumberPin NameBufferTypeDir.PinNumberPin NameBufferTypeDir.P1 VDDQ REFP2 VSS GNDP3 SB_MA[11] DDR3 OP4 VSS GNDP5 SB_MA[14] DDR3 OP6 SA_CKE[1] DDR3 OP7 SA_CKE[0] DDR3 OP8 VSS GNDP9 SA_DQ[31] DDR3 I/OP10 VTT0 REFP26 VCC REFP27 VCC REFP28 VCC REFP29 VCC REFP30 VCC REFP31 VCC REFP32 VCC REFP33 VCC REFP34 VCC REFP35 VCC REFR1 SB_MA[4] DDR3 OR2 SB_MA[6] DDR3 OR3 SB_MA[12] DDR3 OR4 SB_MA[8] DDR3 OR5 SB_MA[9] DDR3 OR6 SB_MA[7] DDR3 OR7 SB_BS[2] DDR3 OR8 RSVD_TPR9 RSVD_TPR10 VSS GNDR26 VCC REFR27 VCC REFR28 VCC REFR29 VCC REFR30 VCC REFR31 VCC REFR32 VCC REFR33 VCC REFR34 VCC REFR35 VCC REFT1 SA_MA[7] DDR3 OT2 SA_MA[11] DDR3 OT3 SA_MA[14] DDR3 OT4 VDDQ REFT5 SB_MA[2] DDR3 OT6 VSS GNDT7 VDDQ REFT8 SB_MA[5] DDR3 OT9 RSVDT10 VTT0 REFT26 VSS GNDT27 VSS GNDT28 VSS GNDT29 VSS GNDT30 VSS GNDT31 VSS GNDT32 VSS GNDT33 VSS GNDT34 VSS GNDT35 VSS GNDU1 VDDQ REFU2 VSS GNDU3 SA_MA[12] DDR3 OU4 VSS GNDU5 SB_MA[0] DDR3 OU6 SA_MA[9] DDR3 OU7 SA_BS[2] DDR3 OU8 VSS GNDU9 RSVDU10 VTT0 REFU26 VCC REFU27 VCC REFDatasheet 121

Processor Pin and Signal InformationTable 8-49.rPGA988A Processor PinList by Pin NumberTable 8-49.rPGA988A Processor PinList by Pin NumberPinNumberPin NameBufferTypeDir.PinNumberPin NameBufferTypeDir.U28 VCC REFU29 VCC REFU30 VCC REFU31 VCC REFU32 VCC REFU33 VCC REFU34 VCC REFU35 VCC REFV1 SA_MA[4] DDR3 OV2 SB_MA[1] DDR3 OV3 SB_MA[3] DDR3 OV4 RSVD_TPV5 RSVD_TPV6 SB_CK#[1] DDR3 OV7 SB_CK[1] DDR3 OV8 SA_MA[6] DDR3 OV9 SA_MA[15] DDR3 OV10 VSS GNDV26 VCC REFV27 VCC REFV28 VCC REFV29 VCC REFV30 VCC REFV31 VCC REFV32 VCC REFV33 VCC REFV34 VCC REFV35 VCC REFW1 SA_MA[1] DDR3 OW2 RSVD_TPW3 RSVD_TPW4 VDDQ REFW5 SB_BS[1] DDR3 OW6 VSS GNDW7 VDDQ REFW8 SB_CK[0] DDR3 OW9 SB_CK#[0] DDR3 OW10 VTT0 REFW26 VSS GNDW27 VSS GNDW28 VSS GNDW29 VSS GNDW30 VSS GNDW31 VSS GNDW32 VSS GNDW33 VSS GNDW34 VSS GNDW35 VSS GNDY1 VDDQ REFY2 VSS GNDY3 SA_MA[0] DDR3 OY4 VSS GNDY5 SA_CK#[1] DDR3 OY6 SA_CK[1] DDR3 OY7 SB_RAS# DDR3 OY8 VSS GNDY9 SA_MA[8] DDR3 OY10 VTT0 REFY26 VCC REFY27 VCC REFY28 VCC REFY29 VCC REFY30 VCC REFY31 VCC REFY32 VCC REFY33 VCC REFY34 VCC REFY35 VCC REF122 Datasheet

Processor Pin and Signal InformationTable 8-50.rPGA988A Processor PinList by Pin NameTable 8-50.rPGA988A Processor PinList by Pin NamePin NamePinNumberBufferTypeDir.Pin NamePinNumberBufferTypeDir.BCLK A16 DIFF CLK IBCLK_ITP AR30 DIFF CLK OBCLK_ITP# AT30 DIFF CLK OBCLK# B16 DIFF CLK IBPM#[0] AJ22 GTL I/OBPM#[1] AK22 GTL I/OBPM#[2] AK24 GTL I/OBPM#[3] AJ24 GTL I/OBPM#[4] AJ25 GTL I/OBPM#[5] AH22 GTL I/OBPM#[6] AK23 GTL I/OBPM#[7] AH23 GTL I/OCATERR# AK14 GTL I/OCFG[0] AM30 CMOS ICFG[1] AM28 CMOS ICFG[2] AP31 CMOS ICFG[3] AL32 CMOS ICFG[4] AL30 CMOS ICFG[5] AM31 CMOS ICFG[6] AN29 CMOS ICFG[7] AM32 CMOS ICFG[8] AK32 CMOS ICFG[9] AK31 CMOS ICFG[10] AK28 CMOS ICFG[11] AJ28 CMOS ICFG[12] AN30 CMOS ICFG[13] AN32 CMOS ICFG[14] AJ32 CMOS ICFG[15] AJ29 CMOS ICFG[16] AJ30 CMOS ICFG[17] AK30 CMOS ICOMP0 AT26 Analog ICOMP1 G16 Analog ICOMP2 AT24 Analog ICOMP3 AT23 Analog IDBR# AN25 ODMI_RX[0] B24 DMI IDMI_RX[1] D23 DMI IDMI_RX[2] B23 DMI IDMI_RX[3] A22 DMI IDMI_RX#[0] A24 DMI IDMI_RX#[1] C23 DMI IDMI_RX#[2] B22 DMI IDMI_RX#[3] A21 DMI IDMI_TX[0] D25 DMI ODMI_TX[1] F24 DMI ODMI_TX[2] E23 DMI ODMI_TX[3] G23 DMI ODMI_TX#[0] D24 DMI ODMI_TX#[1] G24 DMI ODMI_TX#[2] F23 DMI ODMI_TX#[3] H23 DMI ODPLL_REF_SSCLKDPLL_REF_SSCLK#A18 DIFF CLK IA17 DIFF CLK IFDI_FSYNC[0] F17 CMOS IFDI_FSYNC[1] E17 CMOS IFDI_INT C17 CMOS IFDI_LSYNC[0] F18 CMOS IFDI_LSYNC[1] D17 CMOS IFDI_TX[0] D22 FDI OFDI_TX[1] C21 FDI OFDI_TX[2] D20 FDI OFDI_TX[3] C18 FDI OFDI_TX[4] G22 FDI OFDI_TX[5] E20 FDI OFDI_TX[6] F20 FDI OFDI_TX[7] G19 FDI OFDI_TX#[0] E22 FDI OFDI_TX#[1] D21 FDI OFDI_TX#[2] D19 FDI OFDI_TX#[3] D18 FDI ODatasheet 123

Processor Pin and Signal InformationTable 8-50.rPGA988A Processor PinList by Pin NameTable 8-50.rPGA988A Processor PinList by Pin NamePin NamePinNumberBufferTypeDir.Pin NamePinNumberBufferTypeDir.FDI_TX#[4] G21 FDI OFDI_TX#[5] E19 FDI OFDI_TX#[6] F21 FDI OFDI_TX#[7] G18 FDI OGFX_DPRSLPVR AT25 CMOS OGFX_IMON AM24 Analog IGFX_VID[0] AM22 CMOS OGFX_VID[1] AP22 CMOS OGFX_VID[2] AN22 CMOS OGFX_VID[3] AP23 CMOS OGFX_VID[4] AM23 CMOS OGFX_VID[5] AP24 CMOS OGFX_VID[6] AN24 CMOS OGFX_VR_EN AR25 CMOS OISENSE AN35 Analog IKEYA2PECI AT15 Async I/OPEG_CLK E16 DIFF CLK IPEG_CLK# D16 DIFF CLK IPEG_ICOMPI B26 Analog IPEG_ICOMPO A26 Analog IPEG_RBIAS A25 Analog IPEG_RCOMPO B27 Analog IPEG_RX[0] J35 PCIe IPEG_RX[1] H34 PCIe IPEG_RX[2] H33 PCIe IPEG_RX[3] F35 PCIe IPEG_RX[4] G33 PCIe IPEG_RX[5] E34 PCIe IPEG_RX[6] F32 PCIe IPEG_RX[7] D34 PCIe IPEG_RX[8] F33 PCIe IPEG_RX[9] B33 PCIe IPEG_RX[10] D31 PCIe IPEG_RX[11] A32 PCIe IPEG_RX[12] C30 PCIe IPEG_RX[13] A28 PCIe IPEG_RX[14] B29 PCIe IPEG_RX[15] A30 PCIe IPEG_RX#[0] K35 PCIe IPEG_RX#[1] J34 PCIe IPEG_RX#[2] J33 PCIe IPEG_RX#[3] G35 PCIe IPEG_RX#[4] G32 PCIe IPEG_RX#[5] F34 PCIe IPEG_RX#[6] F31 PCIe IPEG_RX#[7] D35 PCIe IPEG_RX#[8] E33 PCIe IPEG_RX#[9] C33 PCIe IPEG_RX#[10] D32 PCIe IPEG_RX#[11] B32 PCIe IPEG_RX#[12] C31 PCIe IPEG_RX#[13] B28 PCIe IPEG_RX#[14] B30 PCIe IPEG_RX#[15] A31 PCIe IPEG_TX[0] L34 PCIe OPEG_TX[1] M34 PCIe OPEG_TX[2] M32 PCIe OPEG_TX[3] L30 PCIe OPEG_TX[4] M31 PCIe OPEG_TX[5] K31 PCIe OPEG_TX[6] M28 PCIe OPEG_TX[7] H31 PCIe OPEG_TX[8] K28 PCIe OPEG_TX[9] G30 PCIe OPEG_TX[10] G29 PCIe OPEG_TX[11] F28 PCIe OPEG_TX[12] E27 PCIe OPEG_TX[13] D28 PCIe OPEG_TX[14] C27 PCIe OPEG_TX[15] C25 PCIe OPEG_TX#[0] L33 PCIe O124 Datasheet

Processor Pin and Signal InformationTable 8-50.rPGA988A Processor PinList by Pin NameTable 8-50.rPGA988A Processor PinList by Pin NamePin NamePinNumberBufferTypeDir.Pin NamePinNumberBufferTypeDir.PEG_TX#[1] M35 PCIe OPEG_TX#[2] M33 PCIe OPEG_TX#[3] M30 PCIe OPEG_TX#[4] L31 PCIe OPEG_TX#[5] K32 PCIe OPEG_TX#[6] M29 PCIe OPEG_TX#[7] J31 PCIe OPEG_TX#[8] K29 PCIe OPEG_TX#[9] H30 PCIe OPEG_TX#[10] H29 PCIe OPEG_TX#[11] F29 PCIe OPEG_TX#[12] E28 PCIe OPEG_TX#[13] D29 PCIe OPEG_TX#[14] D27 PCIe OPEG_TX#[15] C26 PCIe OPM_EXT_TS#[0] AN15 CMOS IPM_EXT_TS#[1] AP15 CMOS IPM_SYNC AL15 CMOS IPRDY# AT28 AsyncGTLPREQ# AP27 AsyncGTLPROC_DPRSLPVROAM34 CMOS OPROCHOT# AN26 AsyncGTLPSI# AN33 AsyncCMOSRESET_OBS# AP26 AsyncCMOSRSTIN# AL14 CMOS IRSVDRSVDRSVDRSVDRSVDRSVDRSVDA19A20AB9AC9AG9AH15AH25II/OOORSVDRSVDRSVDRSVDRSVDRSVDRSVDRSVDRSVDRSVDRSVDRSVDRSVDRSVDRSVDRSVDRSVDRSVDRSVDRSVDRSVDRSVDRSVDRSVDRSVDRSVDRSVDRSVDRSVDRSVDRSVDRSVDRSVDRSVDRSVD_NCTFRSVD_NCTFAJ15AJ26AJ27AJ33AL22AL24AL25AL27AL28AL29AP25AP30AP32AP33AR32AR33AT31AT32B19B20C15D15E30E31G17G25H17J17J28J29L28M27T9U9A3A33Datasheet 125

Processor Pin and Signal InformationTable 8-50.rPGA988A Processor PinList by Pin NameTable 8-50.rPGA988A Processor PinList by Pin NamePin NamePinNumberBufferTypeDir.Pin NamePinNumberBufferTypeDir.RSVD_NCTFRSVD_NCTFRSVD_NCTFRSVD_NCTFRSVD_NCTFRSVD_NCTFRSVD_NCTFRSVD_NCTFRSVD_NCTFRSVD_NCTFRSVD_NCTFRSVD_NCTFRSVD_TPRSVD_TPRSVD_TPRSVD_TPRSVD_TPRSVD_TPRSVD_TPRSVD_TPRSVD_TPRSVD_TPRSVD_TPRSVD_TPRSVD_TPRSVD_TPRSVD_TPRSVD_TPRSVD_TPRSVD_TPRSVD_TPRSVD_TPRSVD_TPRSVD_TPRSVD_TPRSVD_TPA34AP1AP35AR1AR2AR35AT3AT33AT34B35C1C35AA1AA2AA4AA5AD2AD3AD5AD7AD9AE3AE5AG7AJ12AJ13AK26AL26AT2E15F15H16N2N3R8R9RSVD_TPV4RSVD_TPV5RSVD_TPW2RSVD_TPW3SA_BS[0] AC3 DDR3 OSA_BS[1] AB2 DDR3 OSA_BS[2] U7 DDR3 OSA_CAS# AE1 DDR3 OSA_CK[0] AA6 DDR3 OSA_CK[1] Y6 DDR3 OSA_CK#[0] AA7 DDR3 OSA_CK#[1] Y5 DDR3 OSA_CKE[0] P7 DDR3 OSA_CKE[1] P6 DDR3 OSA_CS#[0] AE2 DDR3 OSA_CS#[1] AE8 DDR3 OSA_DM[0] B9 DDR3 OSA_DM[1] D7 DDR3 OSA_DM[2] H7 DDR3 OSA_DM[3] M7 DDR3 OSA_DM[4] AG6 DDR3 OSA_DM[5] AM7 DDR3 OSA_DM[6] AN10 DDR3 OSA_DM[7] AN13 DDR3 OSA_DQ[0] A10 DDR3 I/OSA_DQ[1] C10 DDR3 I/OSA_DQ[2] C7 DDR3 I/OSA_DQ[3] A7 DDR3 I/OSA_DQ[4] B10 DDR3 I/OSA_DQ[5] D10 DDR3 I/OSA_DQ[6] E10 DDR3 I/OSA_DQ[7] A8 DDR3 I/OSA_DQ[8] D8 DDR3 I/OSA_DQ[9] F10 DDR3 I/OSA_DQ[10] E6 DDR3 I/OSA_DQ[11] F7 DDR3 I/O126 Datasheet

Processor Pin and Signal InformationTable 8-50.rPGA988A Processor PinList by Pin NameTable 8-50.rPGA988A Processor PinList by Pin NamePin NamePinNumberBufferTypeDir.Pin NamePinNumberBufferTypeDir.SA_DQ[12] E9 DDR3 I/OSA_DQ[13] B7 DDR3 I/OSA_DQ[14] E7 DDR3 I/OSA_DQ[15] C6 DDR3 I/OSA_DQ[16] H10 DDR3 I/OSA_DQ[17] G8 DDR3 I/OSA_DQ[18] K7 DDR3 I/OSA_DQ[19] J8 DDR3 I/OSA_DQ[20] G7 DDR3 I/OSA_DQ[21] G10 DDR3 I/OSA_DQ[22] J7 DDR3 I/OSA_DQ[23] J10 DDR3 I/OSA_DQ[24] L7 DDR3 I/OSA_DQ[25] M6 DDR3 I/OSA_DQ[26] M8 DDR3 I/OSA_DQ[27] L9 DDR3 I/OSA_DQ[28] L6 DDR3 I/OSA_DQ[29] K8 DDR3 I/OSA_DQ[30] N8 DDR3 I/OSA_DQ[31] P9 DDR3 I/OSA_DQ[32] AH5 DDR3 I/OSA_DQ[33] AF5 DDR3 I/OSA_DQ[34] AK6 DDR3 I/OSA_DQ[35] AK7 DDR3 I/OSA_DQ[36] AF6 DDR3 I/OSA_DQ[37] AG5 DDR3 I/OSA_DQ[38] AJ7 DDR3 I/OSA_DQ[39] AJ6 DDR3 I/OSA_DQ[40] AJ10 DDR3 I/OSA_DQ[41] AJ9 DDR3 I/OSA_DQ[42] AL10 DDR3 I/OSA_DQ[43] AK12 DDR3 I/OSA_DQ[44] AK8 DDR3 I/OSA_DQ[45] AL7 DDR3 I/OSA_DQ[46] AK11 DDR3 I/OSA_DQ[47] AL8 DDR3 I/OSA_DQ[48] AN8 DDR3 I/OSA_DQ[49] AM10 DDR3 I/OSA_DQ[50] AR11 DDR3 I/OSA_DQ[51] AL11 DDR3 I/OSA_DQ[52] AM9 DDR3 I/OSA_DQ[53] AN9 DDR3 I/OSA_DQ[54] AT11 DDR3 I/OSA_DQ[55] AP12 DDR3 I/OSA_DQ[56] AM12 DDR3 I/OSA_DQ[57] AN12 DDR3 I/OSA_DQ[58] AM13 DDR3 I/OSA_DQ[59] AT14 DDR3 I/OSA_DQ[60] AT12 DDR3 I/OSA_DQ[61] AL13 DDR3 I/OSA_DQ[62] AR14 DDR3 I/OSA_DQ[63] AP14 DDR3 I/OSA_DQS[0] C8 DDR3 I/OSA_DQS[1] F9 DDR3 I/OSA_DQS[2] H9 DDR3 I/OSA_DQS[3] M9 DDR3 I/OSA_DQS[4] AH8 DDR3 I/OSA_DQS[5] AK10 DDR3 I/OSA_DQS[6] AN11 DDR3 I/OSA_DQS[7] AR13 DDR3 I/OSA_DQS#[0] C9 DDR3 I/OSA_DQS#[1] F8 DDR3 I/OSA_DQS#[2] J9 DDR3 I/OSA_DQS#[3] N9 DDR3 I/OSA_DQS#[4] AH7 DDR3 I/OSA_DQS#[5] AK9 DDR3 I/OSA_DQS#[6] AP11 DDR3 I/OSA_DQS#[7] AT13 DDR3 I/OSA_MA[0] Y3 DDR3 OSA_MA[1] W1 DDR3 OSA_MA[2] AA8 DDR3 OSA_MA[3] AA3 DDR3 ODatasheet 127

Processor Pin and Signal InformationTable 8-50.rPGA988A Processor PinList by Pin NameTable 8-50.rPGA988A Processor PinList by Pin NamePin NamePinNumberBufferTypeDir.Pin NamePinNumberBufferTypeDir.SA_MA[4] V1 DDR3 OSA_MA[5] AA9 DDR3 OSA_MA[6] V8 DDR3 OSA_MA[7] T1 DDR3 OSA_MA[8] Y9 DDR3 OSA_MA[9] U6 DDR3 OSA_MA[10] AD4 DDR3 OSA_MA[11] T2 DDR3 OSA_MA[12] U3 DDR3 OSA_MA[13] AG8 DDR3 OSA_MA[14] T3 DDR3 OSA_MA[15] V9 DDR3 OSA_ODT[0] AD8 DDR3 OSA_ODT[1] AF9 DDR3 OSA_RAS# AB3 DDR3 OSA_WE# AE9 DDR3 OSB_BS[0] AB1 DDR3 OSB_BS[1] W5 DDR3 OSB_BS[2] R7 DDR3 OSB_CAS# AC5 DDR3 OSB_CK[0] W8 DDR3 OSB_CK[1] V7 DDR3 OSB_CK#[0] W9 DDR3 OSB_CK#[1] V6 DDR3 OSB_CKE[0] M3 DDR3 OSB_CKE[1] M2 DDR3 OSB_CS#[0] AB8 DDR3 OSB_CS#[1] AD6 DDR3 OSB_DM[0] D4 DDR3 OSB_DM[1] E1 DDR3 OSB_DM[2] H3 DDR3 OSB_DM[3] K1 DDR3 OSB_DM[4] AH1 DDR3 OSB_DM[5] AL2 DDR3 OSB_DM[6] AR4 DDR3 OSB_DM[7] AT8 DDR3 OSB_DQ[0] B5 DDR3 I/OSB_DQ[1] A5 DDR3 I/OSB_DQ[2] C3 DDR3 I/OSB_DQ[3] B3 DDR3 I/OSB_DQ[4] E4 DDR3 I/OSB_DQ[5] A6 DDR3 I/OSB_DQ[6] A4 DDR3 I/OSB_DQ[7] C4 DDR3 I/OSB_DQ[8] D1 DDR3 I/OSB_DQ[9] D2 DDR3 I/OSB_DQ[10] F2 DDR3 I/OSB_DQ[11] F1 DDR3 I/OSB_DQ[12] C2 DDR3 I/OSB_DQ[13] F5 DDR3 I/OSB_DQ[14] F3 DDR3 I/OSB_DQ[15] G4 DDR3 I/OSB_DQ[16] H6 DDR3 I/OSB_DQ[17] G2 DDR3 I/OSB_DQ[18] J6 DDR3 I/OSB_DQ[19] J3 DDR3 I/OSB_DQ[20] G1 DDR3 I/OSB_DQ[21] G5 DDR3 I/OSB_DQ[22] J2 DDR3 I/OSB_DQ[23] J1 DDR3 I/OSB_DQ[24] J5 DDR3 I/OSB_DQ[25] K2 DDR3 I/OSB_DQ[26] L3 DDR3 I/OSB_DQ[27] M1 DDR3 I/OSB_DQ[28] K5 DDR3 I/OSB_DQ[29] K4 DDR3 I/OSB_DQ[30] M4 DDR3 I/OSB_DQ[31] N5 DDR3 I/OSB_DQ[32] AF3 DDR3 I/OSB_DQ[33] AG1 DDR3 I/OSB_DQ[34] AJ3 DDR3 I/OSB_DQ[35] AK1 DDR3 I/O128 Datasheet

Processor Pin and Signal InformationTable 8-50.rPGA988A Processor PinList by Pin NameTable 8-50.rPGA988A Processor PinList by Pin NamePin NamePinNumberBufferTypeDir.Pin NamePinNumberBufferTypeDir.SB_DQ[36] AG4 DDR3 I/OSB_DQ[37] AG3 DDR3 I/OSB_DQ[38] AJ4 DDR3 I/OSB_DQ[39] AH4 DDR3 I/OSB_DQ[40] AK3 DDR3 I/OSB_DQ[41] AK4 DDR3 I/OSB_DQ[42] AM6 DDR3 I/OSB_DQ[43] AN2 DDR3 I/OSB_DQ[44] AK5 DDR3 I/OSB_DQ[45] AK2 DDR3 I/OSB_DQ[46] AM4 DDR3 I/OSB_DQ[47] AM3 DDR3 I/OSB_DQ[48] AP3 DDR3 I/OSB_DQ[49] AN5 DDR3 I/OSB_DQ[50] AT4 DDR3 I/OSB_DQ[51] AN6 DDR3 I/OSB_DQ[52] AN4 DDR3 I/OSB_DQ[53] AN3 DDR3 I/OSB_DQ[54] AT5 DDR3 I/OSB_DQ[55] AT6 DDR3 I/OSB_DQ[56] AN7 DDR3 I/OSB_DQ[57] AP6 DDR3 I/OSB_DQ[58] AP8 DDR3 I/OSB_DQ[59] AT9 DDR3 I/OSB_DQ[60] AT7 DDR3 I/OSB_DQ[61] AP9 DDR3 I/OSB_DQ[62] AR10 DDR3 I/OSB_DQ[63] AT10 DDR3 I/OSB_DQS[0] C5 DDR3 I/OSB_DQS[1] E3 DDR3 I/OSB_DQS[2] H4 DDR3 I/OSB_DQS[3] M5 DDR3 I/OSB_DQS[4] AG2 DDR3 I/OSB_DQS[5] AL5 DDR3 I/OSB_DQS[6] AP5 DDR3 I/OSB_DQS[7] AR7 DDR3 I/OSB_DQS#[0] D5 DDR3 I/OSB_DQS#[1] F4 DDR3 I/OSB_DQS#[2] J4 DDR3 I/OSB_DQS#[3] L4 DDR3 I/OSB_DQS#[4] AH2 DDR3 I/OSB_DQS#[5] AL4 DDR3 I/OSB_DQS#[6] AR5 DDR3 I/OSB_DQS#[7] AR8 DDR3 I/OSB_MA[0] U5 DDR3 OSB_MA[1] V2 DDR3 OSB_MA[2] T5 DDR3 OSB_MA[3] V3 DDR3 OSB_MA[4] R1 DDR3 OSB_MA[5] T8 DDR3 OSB_MA[6] R2 DDR3 OSB_MA[7] R6 DDR3 OSB_MA[8] R4 DDR3 OSB_MA[9] R5 DDR3 OSB_MA[10] AB5 DDR3 OSB_MA[11] P3 DDR3 OSB_MA[12] R3 DDR3 OSB_MA[13] AF7 DDR3 OSB_MA[14] P5 DDR3 OSB_MA[15] N1 DDR3 OSB_ODT[0] AC7 DDR3 OSB_ODT[1] AD1 DDR3 OSB_RAS# Y7 DDR3 OSB_WE# AC6 DDR3 OSKTOCC#SM_DRAMPWROKAH24AK13 DDR3 OSM_DRAMRST# F6 DDR3 OSM_RCOMP[0] AL1 Analog ISM_RCOMP[1] AM1 Analog ISM_RCOMP[2] AN1 Analog ITAPPWRGOOD AM26 AsyncCMOSODatasheet 129

Processor Pin and Signal InformationTable 8-50.rPGA988A Processor PinList by Pin NameTable 8-50.rPGA988A Processor PinList by Pin NamePin NamePinNumberBufferTypeDir.Pin NamePinNumberBufferTypeDir.TCK AN28 CMOS ITDI AT29 CMOS ITDI_M AR29 CMOS ITDO AR27 CMOS OTDO_M AP29 CMOS OTHERMTRIP# AK15 AsyncGTLTMS AP28 CMOS ITRST# AT27 CMOS IVAXG AH16 REFVAXG AH18 REFVAXG AH19 REFVAXG AH21 REFVAXG AJ16 REFVAXG AJ18 REFVAXG AJ19 REFVAXG AJ21 REFVAXG AK16 REFVAXG AK18 REFVAXG AK19 REFVAXG AK21 REFVAXG AL16 REFVAXG AL18 REFVAXG AL19 REFVAXG AL21 REFVAXG AM16 REFVAXG AM18 REFVAXG AM19 REFVAXG AM21 REFVAXG AN16 REFVAXG AN18 REFVAXG AN19 REFVAXG AN21 REFVAXG AP16 REFVAXG AP18 REFVAXG AP19 REFVAXG AP21 REFOVAXG AR16 REFVAXG AR18 REFVAXG AR19 REFVAXG AR21 REFVAXG AT16 REFVAXG AT18 REFVAXG AT19 REFVAXG AT21 REFVAXG_SENSE AR22 Analog OVCC AA26 REFVCC AA27 REFVCC AA28 REFVCC AA29 REFVCC AA30 REFVCC AA31 REFVCC AA32 REFVCC AA33 REFVCC AA34 REFVCC AA35 REFVCC AC26 REFVCC AC27 REFVCC AC28 REFVCC AC29 REFVCC AC30 REFVCC AC31 REFVCC AC32 REFVCC AC33 REFVCC AC34 REFVCC AC35 REFVCC AD26 REFVCC AD27 REFVCC AD28 REFVCC AD29 REFVCC AD30 REFVCC AD31 REFVCC AD32 REF130 Datasheet

Processor Pin and Signal InformationTable 8-50.rPGA988A Processor PinList by Pin NameTable 8-50.rPGA988A Processor PinList by Pin NamePin NamePinNumberBufferTypeDir.Pin NamePinNumberBufferTypeDir.VCC AD33 REFVCC AD34 REFVCC AD35 REFVCC AF26 REFVCC AF27 REFVCC AF28 REFVCC AF29 REFVCC AF30 REFVCC AF31 REFVCC AF32 REFVCC AF33 REFVCC AF34 REFVCC AF35 REFVCC AG26 REFVCC AG27 REFVCC AG28 REFVCC AG29 REFVCC AG30 REFVCC AG31 REFVCC AG32 REFVCC AG33 REFVCC AG34 REFVCC AG35 REFVCC P26 REFVCC P27 REFVCC P28 REFVCC P29 REFVCC P30 REFVCC P31 REFVCC P32 REFVCC P33 REFVCC P34 REFVCC P35 REFVCC R26 REFVCC R27 REFVCC R28 REFVCC R29 REFVCC R30 REFVCC R31 REFVCC R32 REFVCC R33 REFVCC R34 REFVCC R35 REFVCC U26 REFVCC U27 REFVCC U28 REFVCC U29 REFVCC U30 REFVCC U31 REFVCC U32 REFVCC U33 REFVCC U34 REFVCC U35 REFVCC V26 REFVCC V27 REFVCC V28 REFVCC V29 REFVCC V30 REFVCC V31 REFVCC V32 REFVCC V33 REFVCC V34 REFVCC V35 REFVCC Y26 REFVCC Y27 REFVCC Y28 REFVCC Y29 REFVCC Y30 REFVCC Y31 REFVCC Y32 REFVCC Y33 REFVCC Y34 REFDatasheet 131

Processor Pin and Signal InformationTable 8-50.rPGA988A Processor PinList by Pin NameTable 8-50.rPGA988A Processor PinList by Pin NamePin NamePinNumberBufferTypeDir.Pin NamePinNumberBufferTypeDir.VCC Y35 REFVCC_SENSE AJ34 Analog OVCCPLL L26 REFVCCPLL L27 REFVCCPLL M26 REFVCCPWRGOOD_0VCCPWRGOOD_1AN27AN14AsyncCMOSAsyncCMOSVDDQ AB4 REFVDDQ AB7 REFVDDQ AC1 REFVDDQ AE4 REFVDDQ AE7 REFVDDQ AF1 REFVDDQ AJ1 REFVDDQ H1 REFVDDQ L1 REFVDDQ N4 REFVDDQ N7 REFVDDQ P1 REFVDDQ T4 REFVDDQ T7 REFVDDQ U1 REFVDDQ W4 REFVDDQ W7 REFVDDQ Y1 REFVID[0] AK35 CMOS OVID[1] AK33 CMOS OVID[2] AK34 CMOS OCSC[0]/VID[3] AL35 CMOS I/OCSC[1]/VID[4] AL33 CMOS I/OCSC[2]/VID[5] AM33 CMOS I/OVID[6] AM35 CMOS OVSS A23 GNDVSS A27 GNDVSS A29 GNDIIVSS A9 GNDVSS AA10 GNDVSS AB26 GNDVSS AB27 GNDVSS AB28 GNDVSS AB29 GNDVSS AB30 GNDVSS AB31 GNDVSS AB32 GNDVSS AB33 GNDVSS AB34 GNDVSS AB35 GNDVSS AB6 GNDVSS AC2 GNDVSS AC4 GNDVSS AC8 GNDVSS AD10 GNDVSS AE26 GNDVSS AE27 GNDVSS AE28 GNDVSS AE29 GNDVSS AE30 GNDVSS AE31 GNDVSS AE32 GNDVSS AE33 GNDVSS AE34 GNDVSS AE35 GNDVSS AE6 GNDVSS AF2 GNDVSS AF4 GNDVSS AF8 GNDVSS AG10 GNDVSS AH13 GNDVSS AH17 GNDVSS AH20 GNDVSS AH26 GND132 Datasheet

Processor Pin and Signal InformationTable 8-50.rPGA988A Processor PinList by Pin NameTable 8-50.rPGA988A Processor PinList by Pin NamePin NamePinNumberBufferTypeDir.Pin NamePinNumberBufferTypeDir.VSS AH27 GNDVSS AH28 GNDVSS AH29 GNDVSS AH3 GNDVSS AH30 GNDVSS AH31 GNDVSS AH32 GNDVSS AH33 GNDVSS AH34 GNDVSS AH35 GNDVSS AH6 GNDVSS AH9 GNDVSS AJ11 GNDVSS AJ14 GNDVSS AJ17 GNDVSS AJ2 GNDVSS AJ20 GNDVSS AJ23 GNDVSS AJ31 GNDVSS AJ5 GNDVSS AJ8 GNDVSS AK17 GNDVSS AK20 GNDVSS AK25 GNDVSS AK27 GNDVSS AK29 GNDVSS AL12 GNDVSS AL17 GNDVSS AL20 GNDVSS AL23 GNDVSS AL3 GNDVSS AL31 GNDVSS AL34 GNDVSS AL6 GNDVSS AL9 GNDVSS AM11 GNDVSS AM14 GNDVSS AM17 GNDVSS AM2 GNDVSS AM20 GNDVSS AM25 GNDVSS AM27 GNDVSS AM29 GNDVSS AM5 GNDVSS AM8 GNDVSS AN17 GNDVSS AN20 GNDVSS AN23 GNDVSS AN31 GNDVSS AN34 GNDVSS AP10 GNDVSS AP13 GNDVSS AP17 GNDVSS AP2 GNDVSS AP20 GNDVSS AP34 GNDVSS AP4 GNDVSS AP7 GNDVSS AR12 GNDVSS AR15 GNDVSS AR17 GNDVSS AR20 GNDVSS AR23 GNDVSS AR24 GNDVSS AR26 GNDVSS AR28 GNDVSS AR3 GNDVSS AR31 GNDVSS AR6 GNDVSS AR9 GNDVSS AT17 GNDVSS AT20 GNDDatasheet 133

Processor Pin and Signal InformationTable 8-50.rPGA988A Processor PinList by Pin NameTable 8-50.rPGA988A Processor PinList by Pin NamePin NamePinNumberBufferTypeDir.Pin NamePinNumberBufferTypeDir.VSS B11 GNDVSS B13 GNDVSS B17 GNDVSS B18 GNDVSS B21 GNDVSS B25 GNDVSS B31 GNDVSS B4 GNDVSS B6 GNDVSS B8 GNDVSS C16 GNDVSS C19 GNDVSS C20 GNDVSS C22 GNDVSS C24 GNDVSS C28 GNDVSS C29 GNDVSS C32 GNDVSS C34 GNDVSS D26 GNDVSS D3 GNDVSS D30 GNDVSS D33 GNDVSS D6 GNDVSS D9 GNDVSS E11 GNDVSS E13 GNDVSS E18 GNDVSS E2 GNDVSS E21 GNDVSS E24 GNDVSS E29 GNDVSS E32 GNDVSS E35 GNDVSS E5 GNDVSS E8 GNDVSS F16 GNDVSS F19 GNDVSS F22 GNDVSS F25 GNDVSS F27 GNDVSS F30 GNDVSS G20 GNDVSS G3 GNDVSS G31 GNDVSS G34 GNDVSS G6 GNDVSS G9 GNDVSS H11 GNDVSS H13 GNDVSS H15 GNDVSS H18 GNDVSS H2 GNDVSS H22 GNDVSS H24 GNDVSS H26 GNDVSS H28 GNDVSS H32 GNDVSS H35 GNDVSS H5 GNDVSS H8 GNDVSS J19 GNDVSS J21 GNDVSS J30 GNDVSS J32 GNDVSS K27 GNDVSS K3 GNDVSS K30 GNDVSS K33 GNDVSS K34 GNDVSS K6 GNDVSS K9 GND134 Datasheet

Processor Pin and Signal InformationTable 8-50.rPGA988A Processor PinList by Pin NameTable 8-50.rPGA988A Processor PinList by Pin NamePin NamePinNumberBufferTypeDir.Pin NamePinNumberBufferTypeDir.VSS L2 GNDVSS L29 GNDVSS L32 GNDVSS L35 GNDVSS L5 GNDVSS L8 GNDVSS M10 GNDVSS N26 GNDVSS N27 GNDVSS N28 GNDVSS N29 GNDVSS N30 GNDVSS N31 GNDVSS N32 GNDVSS N33 GNDVSS N34 GNDVSS N35 GNDVSS N6 GNDVSS P2 GNDVSS P4 GNDVSS P8 GNDVSS R10 GNDVSS T26 GNDVSS T27 GNDVSS T28 GNDVSS T29 GNDVSS T30 GNDVSS T31 GNDVSS T32 GNDVSS T33 GNDVSS T34 GNDVSS T35 GNDVSS T6 GNDVSS U2 GNDVSS U4 GNDVSS U8 GNDVSS V10 GNDVSS W26 GNDVSS W27 GNDVSS W28 GNDVSS W29 GNDVSS W30 GNDVSS W31 GNDVSS W32 GNDVSS W33 GNDVSS W34 GNDVSS W35 GNDVSS W6 GNDVSS Y2 GNDVSS Y4 GNDVSS Y8 GNDVSS_NCTFVSS_NCTFVSS_NCTFVSS_NCTFVSS_NCTFVSS_NCTFVSS_NCTFA35AR34AT1AT35B1B2B34VSS_SENSE AJ35 Analog OVSS_SENSE_VTTA15 Analog OVSSAXG_SENSE AT22 Analog OVTT_SELECT G15 CMOS OVTT_SENSE B15 Analog OVTT0 A11 REFVTT0 A12 REFVTT0 A13 REFVTT0 A14 REFVTT0 AB10 REFVTT0 AC10 REFVTT0 AE10 REFVTT0 AF10 REFVTT0 AH10 REFDatasheet 135

Processor Pin and Signal InformationTable 8-50.rPGA988A Processor PinList by Pin NameTable 8-50.rPGA988A Processor PinList by Pin NamePin NamePinNumberBufferTypeDir.Pin NamePinNumberBufferTypeDir.VTT0 AH11 REFVTT0 AH12 REFVTT0 AH14 REFVTT0 B12 REFVTT0 B14 REFVTT0 C11 REFVTT0 C12 REFVTT0 C13 REFVTT0 C14 REFVTT0 D11 REFVTT0 D12 REFVTT0 D13 REFVTT0 D14 REFVTT0 E12 REFVTT0 E14 REFVTT0 F11 REFVTT0 F12 REFVTT0 F13 REFVTT0 F14 REFVTT0 G11 REFVTT0 G12 REFVTT0 G13 REFVTT0 G14 REFVTT0 H12 REFVTT0 H14 REFVTT0 J11 REFVTT0 J12 REFVTT0 J13 REFVTT0 J14 REFVTT0 J15 REFVTT0 J16 REFVTT0 K10 REFVTT0 L10 REFVTT0 N10 REFVTT0 P10 REFVTT0 T10 REFVTT0 U10 REFVTT0 W10 REFVTT0 Y10 REFVTT1 E25 REFVTT1 E26 REFVTT1 F26 REFVTT1 G26 REFVTT1 G27 REFVTT1 G28 REFVTT1 H19 REFVTT1 H20 REFVTT1 H21 REFVTT1 H25 REFVTT1 H27 REFVTT1 J18 REFVTT1 J20 REFVTT1 J22 REFVTT1 J23 REFVTT1 J24 REFVTT1 J25 REFVTT1 J26 REFVTT1 J27 REFVTT1 K26 REFVTTPWRGOOD AM15 AsyncCMOSI136 Datasheet

Processor Pin and Signal InformationFigure 8-21.BGA1288 Ballmap (Top View, Upper-Left Quadrant)Datasheet 137

Processor Pin and Signal InformationFigure 8-22.BGA1288 Ballmap (Top View, Upper-Right Quadrant)138 Datasheet

Processor Pin and Signal InformationFigure 8-23.BGA1288 Ballmap (Top View, Lower-Left Quadrant)Datasheet 139

Processor Pin and Signal InformationFigure 8-24.BGA1288 Ballmap (Top View, Lower-Right Quadrant)140 Datasheet

Processor Pin and Signal InformationTable 8-51.BGA1288 Processor BallList by Ball Name(Sheet 1 of 37)Pin Name Pin # BufferTypeBCLKAC71 AK7 DIFFCLKBCLK # AK8 DIFFCLKBCLK_ITP K71 DIFFCLKBCLK_ITP # J70 DIFFCLKDirBPM#[0] J69 GTL I/OBPM#[1] J67 GTL I/OBPM#[2] J62 GTL I/OBPM#[3] K65 GTL I/OBPM#[4] K62 GTL I/OBPM#[5] J64 GTL I/OBPM#[6] K69 GTL I/OBPM#[7] M69 GTL I/OCATERR# N61 GTL I/OCFG[0] AL4 CMOS ICFG[1] AM2 CMOS ICFG[2] AK1 CMOS ICFG[3] AK2 CMOS ICFG[4] AK4 CMOS ICFG[5] AJ2 CMOS ICFG[6] AT2 CMOS ICFG[7] AG7 CMOS ICFG[8] AF4 CMOS ICFG[9] AG2 CMOS ICFG[10] AH1 CMOS ICFG[11] AC2 CMOS ICFG[12] AC4 CMOS ICFG[13] AE2 CMOS ICFG[14] AD1 CMOS ICFG[15] AF8 CMOS ICFG[16] AF6 CMOS ICFG[17] AB7 CMOS ICOMP0 AE66 Analog IIIOOTable 8-51.BGA1288 Processor BallList by Ball Name(Sheet 2 of 37)Pin Name Pin # BufferTypeCOMP1 AD69 Analog ICOMP2 AC70 Analog ICOMP3 AD71 Analog IDBR# W71 ODC_TEST_A5DC_TEST_A68DC_TEST_A69DC_TEST_A71DC_TEST_BR1DC_TEST_BR71DC_TEST_BT1DC_TEST_BT3DC_TEST_BT69DC_TEST_BT71DC_TEST_BV1DC_TEST_BV3DC_TEST_BV5DC_TEST_BV68DC_TEST_BV69DC_TEST_BV71DC_TEST_C3DC_TEST_C69DC_TEST_C71DC_TEST_E1DC_TEST_E71A5A68A69A71BR1BR71BT1BT3BT69BT71BV1BV3BV5BV68BV69BV71C3C69C71E1E71DirDMI_RX[0] F9 DMI IDMI_RX[1] J6 DMI IDMI_RX[2] K9 DMI IDMI_RX[3] J2 DMI IDMI_RX#[0] F7 DMI IDMI_RX#[1] J8 DMI IDMI_RX#[2] K8 DMI IDMI_RX#[3] J4 DMI IDMI_TX[0] G17 DMI ODMI_TX[1] M15 DMI ODMI_TX[2] G13 DMI ODatasheet 141

Processor Pin and Signal InformationTable 8-51.BGA1288 Processor BallList by Ball Name(Sheet 3 of 37)Table 8-51.BGA1288 Processor BallList by Ball Name(Sheet 4 of 37)Pin Name Pin # BufferTypeDirPin Name Pin # BufferTypeDirDMI_TX[3] J11 DMI ODMI_TX#[0] H17 DMI ODMI_TX#[1] K15 DMI ODMI_TX#[2] J13 DMI ODMI_TX#[3] F10 DMI ODPLL_REF_SSCLK Y2 DIFFCLKDPLL_REF_SSCLK# W4 DIFFCLKFDI_FSYNC[0] AC7 CMOS IFDI_FSYNC[1] AC9 CMOS IFDI_INT AB5 CMOS IFDI_LSYNC[0] AA1 CMOS IFDI_LSYNC[1] AB2 CMOS IFDI_TX[0] K1 FDI OFDI_TX[1] N5 FDI OFDI_TX[2] N2 FDI OFDI_TX[3] R2 FDI OFDI_TX[4] N9 FDI OFDI_TX[5] R8 FDI OFDI_TX[6] U6 FDI OFDI_TX[7] W10 FDI OFDI_TX#[0] L2 FDI OFDI_TX#[1] N7 FDI OFDI_TX#[2] M4 FDI OFDI_TX#[3] P1 FDI OFDI_TX#[4] N10 FDI OFDI_TX#[5] R7 FDI OFDI_TX#[6] U7 FDI OFDI_TX#[7] W8 FDI OGFX_DPRSLPVR AL71 CMOS OGFX_IMON AL69 CMOS OGFX_VID[0] AF71 CMOS OGFX_VID[1] AG67 CMOS OGFX_VID[2] AG70 CMOS OGFX_VID[3] AH71 CMOS OIIGFX_VID[4] AN71 CMOS OGFX_VID[5] AM67 CMOS OGFX_VID[6] AM70 CMOS OGFX_VR_EN AH69 CMOS OISENSE A41 Analog IPECI N19 Async I/OPEG_CLK L21 Diff CLK IPEG_CLK# J21 DIFFCLKPEG_ICOMPI B12 Analog IPEG_ICOMPO A13 Analog IPEG_RBIAS B11 Analog IPEG_RCOMPO D12 Analog IPEG_RX[0] F40 PCIe IPEG_RX[1] J38 PCIe IPEG_RX[2] G34 PCIe IPEG_RX[3] M34 PCIe IPEG_RX[4] J28 PCIe IPEG_RX[5] G25 PCIe IPEG_RX[6] K24 PCIe IPEG_RX[7] B28 PCIe IPEG_RX[8] A27 PCIe IPEG_RX[9] B25 PCIe IPEG_RX[10] A24 PCIe IPEG_RX[11] B21 PCIe IPEG_RX[12] B19 PCIe IPEG_RX[13] B18 PCIe IPEG_RX[14] B16 PCIe IPEG_RX[15] D15 PCIe IPEG_RX#[0] G40 PCIe IPEG_RX#[1] G38 PCIe IPEG_RX#[2] H34 PCIe IPEG_RX#[3] P34 PCIe IPEG_RX#[4] G28 PCIe IPEG_RX#[5] H25 PCIe IPEG_RX#[6] H24 PCIe II142 Datasheet

Processor Pin and Signal InformationTable 8-51.BGA1288 Processor BallList by Ball Name(Sheet 5 of 37)Table 8-51.BGA1288 Processor BallList by Ball Name(Sheet 6 of 37)Pin Name Pin # BufferTypeDirPin Name Pin # BufferTypeDirPEG_RX#[7] D29 PCIe IPEG_RX#[8] B26 PCIe IPEG_RX#[9] D26 PCIe IPEG_RX#[10] B23 PCIe IPEG_RX#[11] D22 PCIe IPEG_RX#[12] A20 PCIe IPEG_RX#[13] D19 PCIe IPEG_RX#[14] A17 PCIe IPEG_RX#[15] B14 PCIe IPEG_TX[0] L40 PCIe OPEG_TX[1] N38 PCIe OPEG_TX[2] N32 PCIe OPEG_TX[3] B39 PCIe OPEG_TX[4] B37 PCIe OPEG_TX[5] H32 PCIe OPEG_TX[6] A34 PCIe OPEG_TX[7] D36 PCIe OPEG_TX[8] J30 PCIe OPEG_TX[9] B30 PCIe OPEG_TX[10] D33 PCIe OPEG_TX[11] N28 PCIe OPEG_TX[12] M25 PCIe OPEG_TX[13] N24 PCIe OPEG_TX[14] F21 PCIe OPEG_TX[15] L20 PCIe OPEG_TX#[0] N40 PCIe OPEG_TX#[1] L38 PCIe OPEG_TX#[2] M32 PCIe OPEG_TX#[3] D40 PCIe OPEG_TX#[4] A38 PCIe OPEG_TX#[5] G32 PCIe OPEG_TX#[6] B33 PCIe OPEG_TX#[7] B35 PCIe OPEG_TX#[8] L30 PCIe OPEG_TX#[9] A31 PCIe OPEG_TX#[10] B32 PCIe OPEG_TX#[11] L28 PCIe OPEG_TX#[12] N26 PCIe OPEG_TX#[13] M24 PCIe OPEG_TX#[14] G21 PCIe OPEG_TX#[15] J20 PCIe OPM_EXT_TS#[0] AV66 CMOS I/OPM_EXT_TS#[1] AV64 CMOS I/OPM_SYNC M17 CMOS IPRDY# U71 AsyncGTLPREQ# U69 AsyncGTLPROC_DETECTM71PROC_DPRSLPVR F66 CMOS OPROCHOT# N67 AsyncGTLPSI# F68 AsyncCMOSRESET_OBS# N70 AsyncCMOSRSTIN# G3 CMOS IRSVDRSVDRSVDRSVDBE71BE69BB69AY69OII/ORSVD AW70 I/ORSVDRSVDRSVD_TPRSVDRSVD_TPRSVDRSVDRSVDRSVDRSVDRSVDA10AA69AA71AC69AC71AH66AK66AK69AK71AM66AN69OODatasheet 143

Processor Pin and Signal InformationTable 8-51.BGA1288 Processor BallList by Ball Name(Sheet 7 of 37)Table 8-51.BGA1288 Processor BallList by Ball Name(Sheet 8 of 37)Pin Name Pin # BufferTypeDirPin Name Pin # BufferTypeDirRSVDAP66RSVDAR69RSVDAR71RSVDAT67RSVDAT70RSVDAU2RSVDAU69RSVDAU71RSVDAV4RSVDAV69RSVDAV71RSVDB7RSVDB9RSVDD8RSVDR64RSVDR66RSVDT2RSVDT4RSVDU1RSVDV2VCAP0_VSS_SENSE W64VCAP0_SENSE W66RSVD_NCTFA6RSVD_TPBR5RSVD_NCTFBT5RSVD_NCTFBV6RSVD_NCTFBV8RSVD_NCTFC5RSVD_NCTFE3RSVD_NCTFF1RSVD_TPAN7RSVD_TPAP2RSVD_TPAU1SA_BS[0] BT38 DDR3 OSA_BS[1] BH38 DDR3 OSA_BS[2] BF21 DDR3 OSA_CAS# BK43 DDR3 OSA_CK[0] BM34 DDR3 OSA_CK[1] BK36 DDR3 OSA_CK#[0] BP35 DDR3 OSA_CK#[1] BH36 DDR3 OSA_CKE[0] BF20 DDR3 OSA_CKE[1] BK24 DDR3 OSA_CS#[0] BH40 DDR3 OSA_CS#[1] BJ47 DDR3 I/OSA_DM[0] BB10 DDR3 OSA_DM[1] BJ10 DDR3 I/OSA_DM[2] BM15 DDR3 OSA_DM[3] BN24 DDR3 OSA_DM[4] BG44 DDR3 OSA_DM[5] BG53 DDR3 OSA_DM[6] BN62 DDR3 OSA_DM[7] BH59 DDR3 I/OSA_DQ[0] AT8 DDR3 I/OSA_DQ[1] AT6 DDR3 I/OSA_DQ[2] BB5 DDR3 I/OSA_DQ[3] BB9 DDR3 I/OSA_DQ[4] AV7 DDR3 I/OSA_DQ[5] AV6 DDR3 I/OSA_DQ[6] BE6 DDR3 I/OSA_DQ[7] BE8 DDR3 I/OSA_DQ[8] BF11 DDR3 I/OSA_DQ[9] BE11 DDR3 I/OSA_DQ[10] BK5 DDR3 I/OSA_DQ[11] BH13 DDR3 I/OSA_DQ[12] BF9 DDR3 I/OSA_DQ[13] BF6 DDR3 I/OSA_DQ[14] BK7 DDR3 I/OSA_DQ[15] BN8 DDR3 I/OSA_DQ[16] BN11 DDR3 I/OSA_DQ[17] BN9 DDR3 I/OSA_DQ[18] BG17 DDR3 I/O144 Datasheet

Processor Pin and Signal InformationTable 8-51.BGA1288 Processor BallList by Ball Name(Sheet 9 of 37)Table 8-51.BGA1288 Processor BallList by Ball Name(Sheet 10 of 37)Pin Name Pin # BufferTypeDirPin Name Pin # BufferTypeDirSA_DQ[19] BK15 DDR3 I/OSA_DQ[20] BK9 DDR3 I/OSA_DQ[21] BG15 DDR3 I/OSA_DQ[22] BH17 DDR3 I/OSA_DQ[23] BK17 DDR3 I/OSA_DQ[24] BN20 DDR3 I/OSA_DQ[25] BN17 DDR3 I/OSA_DQ[26] BK25 DDR3 I/OSA_DQ[27] BH25 DDR3 I/OSA_DQ[28] BJ20 DDR3 I/OSA_DQ[29] BH21 DDR3 I/OSA_DQ[30] BG24 DDR3 I/OSA_DQ[31] BG25 DDR3 I/OSA_DQ[32] BJ40 DDR3 I/OSA_DQ[33] BM43 DDR3 I/OSA_DQ[34] BF47 DDR3 I/OSA_DQ[35] BF48 DDR3 I/OSA_DQ[36] BN40 DDR3 I/OSA_DQ[37] BH43 DDR3 I/OSA_DQ[38] BN44 DDR3 I/OSA_DQ[39] BN47 DDR3 I/OSA_DQ[40] BN48 DDR3 I/OSA_DQ[41] BN51 DDR3 I/OSA_DQ[42] BH53 DDR3 I/OSA_DQ[43] BJ55 DDR3 I/OSA_DQ[44] BH48 DDR3 I/OSA_DQ[45] BJ48 DDR3 I/OSA_DQ[46] BM53 DDR3 I/OSA_DQ[47] BN55 DDR3 I/OSA_DQ[48] BF55 DDR3 I/OSA_DQ[49] BN57 DDR3 I/OSA_DQ[50] BN65 DDR3 I/OSA_DQ[51] BJ61 DDR3 I/OSA_DQ[52] BF57 DDR3 I/OSA_DQ[53] BJ57 DDR3 I/OSA_DQ[54] BK64 DDR3 I/OSA_DQ[55] BK61 DDR3 I/OSA_DQ[56] BJ63 DDR3 I/OSA_DQ[57] BF64 DDR3 I/OSA_DQ[58] BB64 DDR3 I/OSA_DQ[59] BB66 DDR3 I/OSA_DQ[60] BJ66 DDR3 I/OSA_DQ[61] BF65 DDR3 I/OSA_DQ[62] AY64 DDR3 I/OSA_DQ[63] BC70 DDR3 I/OSA_DQS[0] AY7 DDR3 I/OSA_DQS[1] BJ5 DDR3 I/OSA_DQS[2] BL13 DDR3 I/OSA_DQS[3] BN21 DDR3 I/OSA_DQS[4] BK44 DDR3 I/OSA_DQS[5] BH51 DDR3 I/OSA_DQS[6] BM60 DDR3 I/OSA_DQS[7] BE64 DDR3 I/OSA_DQS#[0] AY5 DDR3 I/OSA_DQS#[1] BJ7 DDR3 I/OSA_DQS#[2] BN13 DDR3 I/OSA_DQS#[3] BL21 DDR3 I/OSA_DQS#[4] BH44 DDR3 I/OSA_DQS#[5] BK51 DDR3 I/OSA_DQS#[6] BP58 DDR3 I/OSA_DQS#[7] BE62 DDR3 I/OSA_MA[0] BT36 DDR3 OSA_MA[1] BP33 DDR3 OSA_MA[2] BV36 DDR3 OSA_MA[3] BG34 DDR3 OSA_MA[4] BG32 DDR3 OSA_MA[5] BN32 DDR3 OSA_MA[6] BK32 DDR3 OSA_MA[7] BJ30 DDR3 OSA_MA[8] BN30 DDR3 OSA_MA[9] BF28 DDR3 OSA_MA[10] BH34 DDR3 ODatasheet 145

Processor Pin and Signal InformationTable 8-51.BGA1288 Processor BallList by Ball Name(Sheet 11 of 37)Table 8-51.BGA1288 Processor BallList by Ball Name(Sheet 12 of 37)Pin Name Pin # BufferTypeDirPin Name Pin # BufferTypeDirSA_MA[11] BH30 DDR3 OSA_MA[12] BJ28 DDR3 OSA_MA[13] BF40 DDR3 OSA_MA[14] BN28 DDR3 OSA_MA[15] BN25 DDR3 OSA_ODT[0] BF43 DDR3 OSA_ODT[1] BL47 DDR3 OSA_RAS# BL38 DDR3 OSA_WE# BF38 DDR3 OSB_BS[0] BV43 DDR3 OSB_BS[1] BV41 DDR3 OSB_BS[2] BV24 DDR3 OSB_CAS# BU46 DDR3 OSB_CK[0] BU33 DDR3 OSB_CK[1] BV38 DDR3 OSB_CK#[0] BV34 DDR3 OSB_CK#[1] BU39 DDR3 OSB_CKE[0] BT26 DDR3 OSB_CKE[1] BT24 DDR3 OSB_CS#[0] BP46 DDR3 OSB_CS#[1] BT43 DDR3 OSB_DM[0] BB4 DDR3 OSB_DM[1] BL4 DDR3 OSB_DM[2] BT13 DDR3 OSB_DM[3] BP22 DDR3 OSB_DM[4] BV47 DDR3 OSB_DM[5] BV57 DDR3 OSB_DM[6] BU65 DDR3 OSB_DM[7] BF67 DDR3 OSB_DQ[0] BA2 DDR3 I/OSB_DQ[1] AW2 DDR3 I/OSB_DQ[2] BD1 DDR3 I/OSB_DQ[3] BE4 DDR3 I/OSB_DQ[4] AY1 DDR3 I/OSB_DQ[5] BC2 DDR3 I/OSB_DQ[6] BF2 DDR3 I/OSB_DQ[7] BH2 DDR3 I/OSB_DQ[8] BG4 DDR3 I/OSB_DQ[9] BG1 DDR3 I/OSB_DQ[10] BR6 DDR3 I/OSB_DQ[11] BR8 DDR3 I/OSB_DQ[12] BJ4 DDR3 I/OSB_DQ[13] BK2 DDR3 I/OSB_DQ[14] BU9 DDR3 I/OSB_DQ[15] BV10 DDR3 I/OSB_DQ[16] BR10 DDR3 I/OSB_DQ[17] BT12 DDR3 I/OSB_DQ[18] BT15 DDR3 I/OSB_DQ[19] BV15 DDR3 I/OSB_DQ[20] BV12 DDR3 I/OSB_DQ[21] BP12 DDR3 I/OSB_DQ[22] BV17 DDR3 I/OSB_DQ[23] BU16 DDR3 I/OSB_DQ[24] BP15 DDR3 I/OSB_DQ[25] BU19 DDR3 I/OSB_DQ[26] BV22 DDR3 I/OSB_DQ[27] BT22 DDR3 I/OSB_DQ[28] BP19 DDR3 I/OSB_DQ[29] BV19 DDR3 I/OSB_DQ[30] BV20 DDR3 I/OSB_DQ[31] BT20 DDR3 I/OSB_DQ[32] BT48 DDR3 I/OSB_DQ[33] BV48 DDR3 I/OSB_DQ[34] BV50 DDR3 I/OSB_DQ[35] BP49 DDR3 I/OSB_DQ[36] BT47 DDR3 I/OSB_DQ[37] BV52 DDR3 I/OSB_DQ[38] BV54 DDR3 I/OSB_DQ[39] BT54 DDR3 I/OSB_DQ[40] BP53 DDR3 I/OSB_DQ[41] BU53 DDR3 I/OSB_DQ[42] BT59 DDR3 I/O146 Datasheet

Processor Pin and Signal InformationTable 8-51.BGA1288 Processor BallList by Ball Name(Sheet 13 of 37)Table 8-51.BGA1288 Processor BallList by Ball Name(Sheet 14 of 37)Pin Name Pin # BufferTypeDirPin Name Pin # BufferTypeDirSB_DQ[43] BT57 DDR3 I/OSB_DQ[44] BP56 DDR3 I/OSB_DQ[45] BT55 DDR3 I/OSB_DQ[46] BU60 DDR3 I/OSB_DQ[47] BV59 DDR3 I/OSB_DQ[48] BV61 DDR3 I/OSB_DQ[49] BP60 DDR3 I/OSB_DQ[50] BR66 DDR3 I/OSB_DQ[51] BR64 DDR3 I/OSB_DQ[52] BR62 DDR3 I/OSB_DQ[53] BT61 DDR3 I/OSB_DQ[54] BN68 DDR3 I/OSB_DQ[55] BL69 DDR3 I/OSB_DQ[56] BJ71 DDR3 I/OSB_DQ[57] BF70 DDR3 I/OSB_DQ[58] BG71 DDR3 I/OSB_DQ[59] BC67 DDR3 I/OSB_DQ[60] BK70 DDR3 I/OSB_DQ[61] BK67 DDR3 I/OSB_DQ[62] BD71 DDR3 I/OSB_DQ[63] BD69 DDR3 I/OSB_DQS[0] BD4 DDR3 I/OSB_DQS[1] BN4 DDR3 I/OSB_DQS[2] BV13 DDR3 I/OSB_DQS[3] BT17 DDR3 I/OSB_DQS[4] BT50 DDR3 I/OSB_DQS[5] BU56 DDR3 I/OSB_DQS[6] BV62 DDR3 I/OSB_DQS[7] BJ69 DDR3 I/OSB_DQS#[0] BE2 DDR3 I/OSB_DQS#[1] BM3 DDR3 I/OSB_DQS#[2] BU12 DDR3 I/OSB_DQS#[3] BT19 DDR3 I/OSB_DQS#[4] BT52 DDR3 I/OSB_DQS#[5] BV55 DDR3 I/OSB_DQS#[6] BU63 DDR3 I/OSB_DQS#[7] BG69 DDR3 I/OSB_MA[0] BT34 DDR3 OSB_MA[1] BP30 DDR3 OSB_MA[2] BV29 DDR3 OSB_MA[3] BU30 DDR3 OSB_MA[4] BV31 DDR3 OSB_MA[5] BT33 DDR3 OSB_MA[6] BT31 DDR3 OSB_MA[7] BP26 DDR3 OSB_MA[8] BV27 DDR3 OSB_MA[9] BT27 DDR3 OSB_MA[10] BU42 DDR3 OSB_MA[11] BU26 DDR3 OSB_MA[12] BT29 DDR3 OSB_MA[13] BT45 DDR3 OSB_MA[14] BV26 DDR3 OSB_MA[15] BU23 DDR3 OSB_ODT[0] BV45 DDR3 OSB_ODT[1] BU49 DDR3 OSB_RAS# BT40 DDR3 OSB_WE# BT41 DDR3 OSM_DRAMPWROK AM5 AsyncCMOSSM_DRAMRST# BJ12 DDR3 OSM_RCOMP[0] BV33 Analog ISM_RCOMP[1] BP39 AnalogSM_RCOMP[2] BV40 Analog ITAPPWRGOOD Y70 AsyncCMOSTCK T67 CMOS ITDI T69 CMOS ITDI_M P71 CMOS ITDO T71 CMOS OTDO_M T70 CMOS OTHERMTRIP# N17 AsyncGTLTMS N65 CMOS IIOODatasheet 147

Processor Pin and Signal InformationTable 8-51.BGA1288 Processor BallList by Ball Name(Sheet 15 of 37)Table 8-51.BGA1288 Processor BallList by Ball Name(Sheet 16 of 37)Pin Name Pin # BufferTypeDirPin Name Pin # BufferTypeDirTRST# P69 CMOS IVAXG AD17 REFVAXG AD19 REFVAXG AD21 REFVAXG AD23 REFVAXG AD24 REFVAXG AD26 REFVAXG AD28 REFVAXG AF14 REFVAXG AF15 REFVAXG AF17 REFVAXG AF19 REFVAXG AF21 REFVAXG AF23 REFVAXG AF24 REFVAXG AF26 REFVAXG AF28 REFVAXG AH12 REFVAXG AH14 REFVAXG AJ10 REFVAXG AK12 REFVAXG AK14 REFVAXG AL19 REFVAXG AL21 REFVAXG AL23 REFVAXG AL24 REFVAXG AL26 REFVAXG AL28 REFVAXG AL30 REFVAXG AL32 REFVAXG AN19 REFVAXG AN21 REFVAXG AN23 REFVAXG AN24 REFVAXG AN26 REFVAXG AN28 REFVAXG AN30 REFVAXG AN32 REFVAXG_SENSE AF12 Analog OVCAP0 AK50 PWRVCAP0 AK53 PWRVCAP0 AK57 PWRVCAP0 AL50 PWRVCAP0 AL53 PWRVCAP0 AL57 PWRVCAP0 AN50 PWRVCAP0 AN53 PWRVCAP0 AN57 PWRVCAP0 AR48 PWRVCAP0 AR51 PWRVCAP0 AR55 PWRVCAP0 AU48 PWRVCAP0 AU51 PWRVCAP0 AU55 PWRVCAP0 AW50 PWRVCAP0 AW53 PWRVCAP0 AW57 PWRVCAP0 AY50 PWRVCAP0 AY53 PWRVCAP0 AY57 PWRVCAP0 BB48 PWRVCAP0 BB51 PWRVCAP0 BB55 PWRVCAP0 BD48 PWRVCAP0 BD51 PWRVCAP0 BD55 PWRVCAP1 AK39 PWRVCAP1 AK42 PWRVCAP1 AK46 PWRVCAP1 AL39 PWRVCAP1 AL42 PWRVCAP1 AL46 PWR148 Datasheet

Processor Pin and Signal InformationTable 8-51.BGA1288 Processor BallList by Ball Name(Sheet 17 of 37)Table 8-51.BGA1288 Processor BallList by Ball Name(Sheet 18 of 37)Pin Name Pin # BufferTypeDirPin Name Pin # BufferTypeDirVCAP1 AN39 PWRVCAP2 U59 PWRVCAP1 AN42 PWRVCAP2 U60 PWRVCAP1 AN46 PWRVCAP2 W59 PWRVCAP1 AR37 PWRVCAP2 W60 PWRVCAP1 AR41 PWRVCC A43 REFVCAP1 AR44 PWRVCC A47 REFVCAP1 AU37 PWRVCC A50 REFVCAP1 AU41 PWRVCC A54 REFVCAP1 AU44 PWRVCC A57 REFVCAP1 AW39 PWRVCC AA41 REFVCAP1 AW42 PWRVCC AA44 REFVCAP1 AW46 PWRVCC AA48 REFVCAP1 AY39 PWRVCC AA51 REFVCAP1 AY42 PWRVCC AA55 REFVCAP1 AY46 PWRVCC AB41 REFVCAP1 BB37 PWRVCC AB44 REFVCAP1 BB41 PWRVCC AB48 REFVCAP1 BB44 PWRVCC AB51 REFVCAP1 BD37 PWRVCC AB55 REFVCAP1 BD41 PWRVCC AD41 REFVCAP1 BD44 PWRVCC AD44 REFVCAP2 AA59 PWRVCC AD48 REFVCAP2 AA60 PWRVCC AD51 REFVCAP2 AB59 PWRVCC AD55 REFVCAP2 AB60 PWRVCC AF41 REFVCAP2 AD59 PWRVCC AF42 REFVCAP2 AD60 PWRVCC AF44 REFVCAP2 AF59 PWRVCC AF46 REFVCAP2 AF60 PWRVCC AF48 REFVCAP2 AH59 PWRVCC AF50 REFVCAP2 AH60 PWRVCC AF51 REFVCAP2 AK59 PWRVCC AF53 REFVCAP2 AK60 PWRVCC AF55 REFVCAP2 AK62 PWRVCC AF57 REFVCAP2 R59 PWRVCC B42 REFVCAP2 R60 PWRVCC B46 REFDatasheet 149

Processor Pin and Signal InformationTable 8-51.BGA1288 Processor BallList by Ball Name(Sheet 19 of 37)Table 8-51.BGA1288 Processor BallList by Ball Name(Sheet 20 of 37)Pin Name Pin # BufferTypeDirPin Name Pin # BufferTypeDirVCC B49 REFVCC B53 REFVCC B56 REFVCC B60 REFVCC D43 REFVCC D45 REFVCC D47 REFVCC D48 REFVCC D50 REFVCC D52 REFVCC D54 REFVCC D55 REFVCC D57 REFVCC D59 REFVCC E42 REFVCC E46 REFVCC E50 REFVCC E53 REFVCC E57 REFVCC E60 REFVCC F55 REFVCC G44 REFVCC G51 REFVCC G55 REFVCC G60 REFVCC H44 REFVCC H51 REFVCC H60 REFVCC J55 REFVCC K44 REFVCC K51 REFVCC K60 REFVCC L55 REFVCC M44 REFVCC M51 REFVCC M60 REFVCC N42 REFVCC N44 REFVCC N48 REFVCC N51 REFVCC N55 REFVCC P60 REFVCC R41 REFVCC R44 REFVCC R48 REFVCC R51 REFVCC R55 REFVCC U41 REFVCC U44 REFVCC U48 REFVCC U51 REFVCC U55 REFVCC W41 REFVCC W44 REFVCC W48 REFVCC W51 REFVCC W55 REFVCC_SENSE F64 Analog OVCCPLL R37 REFVCCPLL R39 REFVCCPLL U37 REFVCCPLL W37 REFVCCPLL W39 REFVCCPWRGOOD_0 Y67 AsyncCMOSVCCPWRGOOD_1 AM7 AsyncCMOSVDDQ BB15 REFVDDQ BB17 REFVDDQ BB19 REFVDDQ BB21 REFVDDQ BB23 REFII150 Datasheet

Processor Pin and Signal InformationTable 8-51.BGA1288 Processor BallList by Ball Name(Sheet 21 of 37)Table 8-51.BGA1288 Processor BallList by Ball Name(Sheet 22 of 37)Pin Name Pin # BufferTypeDirPin Name Pin # BufferTypeDirVDDQ BB24 REFVDDQ BB26 REFVDDQ BB28 REFVDDQ BB30 REFVDDQ BB32 REFVDDQ BB33 REFVDDQ BB35 REFVDDQ BD15 REFVDDQ BD17 REFVDDQ BD19 REFVDDQ BD21 REFVDDQ BD23 REFVDDQ BD24 REFVDDQ BD26 REFVDDQ BD28 REFVDDQ BD30 REFVDDQ BD32 REFVDDQ BD33 REFVDDQ BD35 REFVDDQ BF15 REFVDDQ BF16 REFVDDQ BG43 REFVDDQ BH28 REFVDDQ BH32 REFVDDQ BJ38 REFVDDQ BL30 REFVDDQ BM25 REFVDDQ BN38 REFVDDQ BU28 REFVDDQ BU35 REFVDDQ BU40 REFVDDQ_CK BB12 REFVDDQ_CK BB14 REFVID[0] A61 CMOS OVID[1] D61 CMOS OVID[2] D62 CMOS OCSC[0]/VID[3] A62 CMOS I/OCSC[1]VID[4] B63 CMOS I/OCSC[2]VID[5] D64 CMOS I/OVID[6] D66 CMOS OVSS A12 GNDVSS A15 GNDVSS A19 GNDVSS A22 GNDVSS A26 GNDVSS A29 GNDVSS A33 GNDVSS A36 GNDVSS A40 GNDVSS A45 GNDVSS A48 GNDVSS A52 GNDVSS A55 GNDVSS A59 GNDVSS A64 GNDVSS A66 GNDVSS A8 GNDVSS AA14 GNDVSS AA15 GNDVSS AA17 GNDVSS AA19 GNDVSS AA21 GNDVSS AA23 GNDVSS AA24 GNDVSS AA26 GNDVSS AA28 GNDVSS AA30 GNDVSS AA32 GNDVSS AA33 GNDVSS AA35 GNDVSS AA37 GNDVSS AA39 GNDDatasheet 151

Processor Pin and Signal InformationTable 8-51.BGA1288 Processor BallList by Ball Name(Sheet 23 of 37)Table 8-51.BGA1288 Processor BallList by Ball Name(Sheet 24 of 37)Pin Name Pin # BufferTypeDirPin Name Pin # BufferTypeDirVSS AA4 GNDVSS AC67 GNDVSS AA42 GNDVSS AD4 GNDVSS AA46 GNDVSS AD42 GNDVSS AA50 GNDVSS AD46 GNDVSS AA53 GNDVSS AD50 GNDVSS AA57 GNDVSS AD53 GNDVSS AA62 GNDVSS AD57 GNDVSS AA64 GNDVSS AD62 GNDVSS AA66 GNDVSS AE64 GNDVSS AB14 GNDVSS AE70 GNDVSS AB15 GNDVSS AF1 GNDVSS AB17 GNDVSS AF62 GNDVSS AB19 GNDVSS AF69 GNDVSS AB21 GNDVSS AG6 GNDVSS AB23 GNDVSS AG64 GNDVSS AB24 GNDVSS AG9 GNDVSS AB26 GNDVSS AH15 GNDVSS AB28 GNDVSS AH17 GNDVSS AB30 GNDVSS AH19 GNDVSS AB32 GNDVSS AH21 GNDVSS AB33 GNDVSS AH23 GNDVSS AB35 GNDVSS AH24 GNDVSS AB37 GNDVSS AH26 GNDVSS AB39 GNDVSS AH28 GNDVSS AB42 GNDVSS AH30 GNDVSS AB46 GNDVSS AH32 GNDVSS AB50 GNDVSS AH33 GNDVSS AB53 GNDVSS AH35 GNDVSS AB57 GNDVSS AH37 GNDVSS AB62 GNDVSS AH39 GNDVSS AB70 GNDVSS AH4 GNDVSS AB9 GNDVSS AH41 GNDVSS AC1 GNDVSS AH42 GNDVSS AC10 GNDVSS AH44 GNDVSS AC5 GNDVSS AH46 GNDVSS AC64 GNDVSS AH48 GND152 Datasheet

Processor Pin and Signal InformationTable 8-51.BGA1288 Processor BallList by Ball Name(Sheet 25 of 37)Table 8-51.BGA1288 Processor BallList by Ball Name(Sheet 26 of 37)Pin Name Pin # BufferTypeDirPin Name Pin # BufferTypeDirVSS AH50 GNDVSS AM8 GNDVSS AH51 GNDVSS AN37 GNDVSS AH53 GNDVSS AN4 GNDVSS AH55 GNDVSS AN41 GNDVSS AH57 GNDVSS AN44 GNDVSS AH62 GNDVSS AN48 GNDVSS AJ70 GNDVSS AN5 GNDVSS AK15 GNDVSS AN51 GNDVSS AK17 GNDVSS AN55 GNDVSS AK19 GNDVSS AN62 GNDVSS AK21 GNDVSS AP64 GNDVSS AK23 GNDVSS AP70 GNDVSS AK24 GNDVSS AR1 GNDVSS AK26 GNDVSS AR14 GNDVSS AK28 GNDVSS AR15 GNDVSS AK30 GNDVSS AR17 GNDVSS AK32 GNDVSS AR19 GNDVSS AK37 GNDVSS AR21 GNDVSS AK41 GNDVSS AR23 GNDVSS AK44 GNDVSS AR24 GNDVSS AK48 GNDVSS AR26 GNDVSS AK51 GNDVSS AR28 GNDVSS AK55 GNDVSS AR30 GNDVSS AK64 GNDVSS AR32 GNDVSS AK70 GNDVSS AR33 GNDVSS AL1 GNDVSS AR35 GNDVSS AL33 GNDVSS AR39 GNDVSS AL35 GNDVSS AR4 GNDVSS AL37 GNDVSS AR42 GNDVSS AL41 GNDVSS AR46 GNDVSS AL44 GNDVSS AR50 GNDVSS AL48 GNDVSS AR53 GNDVSS AL51 GNDVSS AR57 GNDVSS AL55 GNDVSS AR62 GNDVSS AL62 GNDVSS AT10 GNDVSS AM64 GNDVSS AT64 GNDDatasheet 153

Processor Pin and Signal InformationTable 8-51.BGA1288 Processor BallList by Ball Name(Sheet 27 of 37)Table 8-51.BGA1288 Processor BallList by Ball Name(Sheet 28 of 37)Pin Name Pin # BufferTypeDirPin Name Pin # BufferTypeDirVSS AU14 GNDVSS AY17 GNDVSS AU15 GNDVSS AY19 GNDVSS AU17 GNDVSS AY21 GNDVSS AU19 GNDVSS AY23 GNDVSS AU21 GNDVSS AY24 GNDVSS AU23 GNDVSS AY26 GNDVSS AU24 GNDVSS AY28 GNDVSS AU26 GNDVSS AY30 GNDVSS AU28 GNDVSS AY32 GNDVSS AU30 GNDVSS AY33 GNDVSS AU32 GNDVSS AY35 GNDVSS AU33 GNDVSS AY37 GNDVSS AU35 GNDVSS AY4 GNDVSS AU39 GNDVSS AY41 GNDVSS AU4 GNDVSS AY44 GNDVSS AU42 GNDVSS AY48 GNDVSS AU46 GNDVSS AY51 GNDVSS AU50 GNDVSS AY55 GNDVSS AU53 GNDVSS AY59 GNDVSS AU57 GNDVSS AY62 GNDVSS AU62 GNDVSS AY66 GNDVSS AU70 GNDVSS AY71 GNDVSS AV1 GNDVSS AY8 GNDVSS AV9 GNDVSS B40 GNDVSS AW37 GNDVSS B44 GNDVSS AW41 GNDVSS B48 GNDVSS AW44 GNDVSS B51 GNDVSS AW48 GNDVSS B55 GNDVSS AW51 GNDVSS B58 GNDVSS AW55 GNDVSS B62 GNDVSS AW59 GNDVSS B65 GNDVSS AW62 GNDVSS BA70 GNDVSS AW67 GNDVSS BB1 GNDVSS AY12 GNDVSS BB39 GNDVSS AY14 GNDVSS BB42 GNDVSS AY15 GNDVSS BB46 GND154 Datasheet

Processor Pin and Signal InformationTable 8-51.BGA1288 Processor BallList by Ball Name(Sheet 29 of 37)Table 8-51.BGA1288 Processor BallList by Ball Name(Sheet 30 of 37)Pin Name Pin # BufferTypeDirPin Name Pin # BufferTypeDirVSS BB50 GNDVSS BK53 GNDVSS BB53 GNDVSS BK60 GNDVSS BB57 GNDVSS BK63 GNDVSS BB62 GNDVSS BL1 GNDVSS BB7 GNDVSS BL20 GNDVSS BB71 GNDVSS BL28 GNDVSS BD14 GNDVSS BL40 GNDVSS BD39 GNDVSS BL48 GNDVSS BD42 GNDVSS BL55 GNDVSS BD46 GNDVSS BL57 GNDVSS BD50 GNDVSS BL71 GNDVSS BD53 GNDVSS BM17 GNDVSS BD57 GNDVSS BM24 GNDVSS BE1 GNDVSS BM32 GNDVSS BE65 GNDVSS BM44 GNDVSS BE70 GNDVSS BM51 GNDVSS BE9 GNDVSS BM70 GNDVSS BF13 GNDVSS BN1 GNDVSS BF30 GNDVSS BN6 GNDVSS BF62 GNDVSS BN64 GNDVSS BF8 GNDVSS BN71 GNDVSS BG36 GNDVSS BP42 GNDVSS BG51 GNDVSS BR3 GNDVSS BH15 GNDVSS BR68 GNDVSS BH20 GNDVSS BR69 GNDVSS BH24 GNDVSS BT68 GNDVSS BH47 GNDVSS BU11 GNDVSS BH55 GNDVSS BU14 GNDVSS BH57 GNDVSS BU18 GNDVSS BH70 GNDVSS BU21 GNDVSS BJ1 GNDVSS BU25 GNDVSS BJ21 GNDVSS BU32 GNDVSS BJ64 GNDVSS BU37 GNDVSS BJ9 GNDVSS BU44 GNDVSS BK10 GNDVSS BU48 GNDVSS BK34 GNDVSS BU51 GNDDatasheet 155

Processor Pin and Signal InformationTable 8-51.BGA1288 Processor BallList by Ball Name(Sheet 31 of 37)Table 8-51.BGA1288 Processor BallList by Ball Name(Sheet 32 of 37)Pin Name Pin # BufferTypeDirPin Name Pin # BufferTypeDirVSS BU55 GNDVSS G30 GNDVSS BU58 GNDVSS G43 GNDVSS BU62 GNDVSS G47 GNDVSS BU7 GNDVSS G48 GNDVSS BV64 GNDVSS G53 GNDVSS BV66 GNDVSS G57 GNDVSS C68 GNDVSS G70 GNDVSS D10 GNDVSS H1 GNDVSS D13 GNDVSS H36 GNDVSS D17 GNDVSS H43 GNDVSS D20 GNDVSS H53 GNDVSS D24 GNDVSS H71 GNDVSS D27 GNDVSS J40 GNDVSS D31 GNDVSS J47 GNDVSS D34 GNDVSS J48 GNDVSS D38 GNDVSS J57 GNDVSS D41 GNDVSS J65 GNDVSS D6 GNDVSS J9 GNDVSS E12 GNDVSS K11 GNDVSS E16 GNDVSS K17 GNDVSS E30 GNDVSS K25 GNDVSS E33 GNDVSS K32 GNDVSS E37 GNDVSS K34 GNDVSS E5 GNDVSS K36 GNDVSS E68 GNDVSS K4 GNDVSS E69 GNDVSS K43 GNDVSS F20 GNDVSS K53 GNDVSS F28 GNDVSS K6 GNDVSS F4 GNDVSS K64 GNDVSS F47 GNDVSS L13 GNDVSS F48 GNDVSS L47 GNDVSS F61 GNDVSS L48 GNDVSS F71 GNDVSS L57 GNDVSS G15 GNDVSS L70 GNDVSS G20 GNDVSS M1 GNDVSS G24 GNDVSS M36 GND156 Datasheet

Processor Pin and Signal InformationTable 8-51.BGA1288 Processor BallList by Ball Name(Sheet 33 of 37)Table 8-51.BGA1288 Processor BallList by Ball Name(Sheet 34 of 37)Pin Name Pin # BufferTypeDirPin Name Pin # BufferTypeDirVSS M42 GNDVSS M53 GNDVSS N15 GNDVSS N21 GNDVSS N30 GNDVSS N46 GNDVSS N50 GNDVSS N53 GNDVSS N57 GNDVSS N63 GNDVSS P4 GNDVSS R14 GNDVSS R42 GNDVSS R46 GNDVSS R5 GNDVSS R50 GNDVSS R53 GNDVSS R57 GNDVSS R62 GNDVSS R70 GNDVSS T1 GNDVSS U39 GNDVSS U4 GNDVSS U42 GNDVSS U46 GNDVSS U50 GNDVSS U53 GNDVSS U57 GNDVSS U62 GNDVSS U64 GNDVSS U9 GNDVSS V70 GNDVSS W1 GNDVSS W42 GNDVSS W46 GNDVSS W50 GNDVSS W53 GNDVSS W57 GNDVSS W6 GNDVSS W62 GNDVSS W69 GNDVSS_SENSE F63 Analog OVSS_SENSE_VTT R12 Analog OVSSAXG_SENSE AF10 Analog OVTT_SELECT AN1 CMOS OVTT_SENSE N13 Analog OVTT0 AD30 REFVTT0 AD32 REFVTT0 AD33 REFVTT0 AD35 REFVTT0 AD37 REFVTT0 AD39 REFVTT0 AF30 REFVTT0 AF32 REFVTT0 AF33 REFVTT0 AF35 REFVTT0 AF37 REFVTT0 AF39 REFVTT0 AK33 REFVTT0 AK35 REFVTT0 AL12 REFVTT0 AL14 REFVTT0 AL15 REFVTT0 AL17 REFVTT0 AL59 REFVTT0 AL60 REFVTT0 AM10 REFVTT0 AN12 REFVTT0 AN14 REFVTT0 AN15 REFVTT0 AN17 REFVTT0 AN33 REFDatasheet 157

Processor Pin and Signal InformationTable 8-51.BGA1288 Processor BallList by Ball Name(Sheet 35 of 37)Table 8-51.BGA1288 Processor BallList by Ball Name(Sheet 36 of 37)Pin Name Pin # BufferTypeDirPin Name Pin # BufferTypeDirVTT0 AN35 REFVTT0 U32 REFVTT0 AN59 REFVTT0 U33 REFVTT0 AN60 REFVTT0 U35 REFVTT0 AN9 REFVTT0 W23 REFVTT0 AR12 REFVTT0 W24 REFVTT0 AR59 REFVTT0 W26 REFVTT0 AR60 REFVTT0 W28 REFVTT0 AU12 REFVTT0 W30 REFVTT0 AU59 REFVTT0 W32 REFVTT0 AU60 REFVTT0 W33 REFVTT0 AW12 REFVTT0 W35 REFVTT0 AW14 REFVTT0_DDR AW15 REFVTT0 AW33 REFVTT0_DDR AW17 REFVTT0 AW35 REFVTT0_DDR AW19 REFVTT0 AW60 REFVTT0_DDR AW21 REFVTT0 AY10 REFVTT0_DDR AW23 REFVTT0 AY60 REFVTT0_DDR AW24 REFVTT0 BB59 REFVTT0_DDR AW26 REFVTT0 BB60 REFVTT0_DDR AW28 REFVTT0 BD59 REFVTT0_DDR AW30 REFVTT0 BD60 REFVTT0_DDR AW32 REFVTT0 BF59 REFVTT1 AA12 REFVTT0 BF60 REFVTT1 AB12 REFVTT0 R23 REFVTT1 AD12 REFVTT0 R24 REFVTT1 AD14 REFVTT0 R26 REFVTT1 AD15 REFVTT0 R28 REFVTT1 R15 REFVTT0 R30 REFVTT1 R17 REFVTT0 R32 REFVTT1 R19 REFVTT0 R33 REFVTT1 R21 REFVTT0 R35 REFVTT1 U12 REFVTT0 U23 REFVTT1 U14 REFVTT0 U24 REFVTT1 U15 REFVTT0 U26 REFVTT1 U17 REFVTT0 U28 REFVTT1 U19 REFVTT0 U30 REFVTT1 U21 REF158 Datasheet

Processor Pin and Signal InformationTable 8-51.BGA1288 Processor BallList by Ball Name(Sheet 37 of 37)Table 8-52.BGA1288 Processor BallList by Ball Number(Sheet 2 of 37)Pin Name Pin # BufferTypeDirPin #Pin NameBufferTypeDirVTT1 W12 REFVTT1 W14 REFVTT1 W15 REFVTT1 W17 REFVTT1 W19 REFVTT1 W21 REFVTTPWRGOOD H15 AsyncCMOSTable 8-52.BGA1288 Processor BallList by Ball Number(Sheet 1 of 37)Pin #A5A6Pin NameDC_TEST_A5RSVD_NCTFBufferTypeA8 VSS GNDA10RSVDA12 VSS GNDA13 PEG_ICOMPO Analog IA15 VSS GNDA17 PEG_RX#[14] PCIe IA19 VSS GNDA20 PEG_RX#[12] PCIe IA22 VSS GNDA24 PEG_RX[10] PCIe IA26 VSS GNDA27 PEG_RX[8] PCIe IA29 VSS GNDIDirA31 PEG_TX#[9] PCIe OA33 VSS GNDA34 PEG_TX[6] PCIe OA36 VSS GNDA38 PEG_TX#[4] PCIe OA40 VSS GNDA41 ISENSE Analog IA43 VCC REFA45 VSS GNDA47 VCC REFA48 VSS GNDA50 VCC REFA52 VSS GNDA54 VCC REFA55 VSS GNDA57 VCC REFA59 VSS GNDA61 VID[0] CMOS OA62 CSC[0]/VID[3] CMOS I/OA64 VSS GNDA66 VSS GNDA68 DC_TEST_A68A69 DC_TEST_A69A71 DC_TEST_A71AA1 FDI_LSYNC[0] CMOS IAA4 VSS GNDAA12 VTT1 REFAA14 VSS GNDAA15 VSS GNDAA17 VSS GNDAA19 VSS GNDAA21 VSS GNDAA23 VSS GNDAA24 VSS GNDAA26 VSS GNDAA28 VSS GNDAA30 VSS GNDAA32 VSS GNDAA33 VSS GNDAA35 VSS GNDAA37 VSS GNDAA39 VSS GNDAA41 VCC REFDatasheet 159

Processor Pin and Signal InformationTable 8-52.BGA1288 Processor BallList by Ball Number(Sheet 3 of 37)Table 8-52.BGA1288 Processor BallList by Ball Number(Sheet 4 of 37)Pin #Pin NameBufferTypeDirPin #Pin NameBufferTypeDirAA42 VSS GNDAA44 VCC REFAA46 VSS GNDAA48 VCC REFAA50 VSS GNDAA51 VCC REFAA53 VSS GNDAA55 VCC REFAA57 VSS GNDAA59 VCAP2 PWRAA60 VCAP2 PWRAA62 VSS GNDAA64 VSS GNDAA66 VSS GNDAA69 RSVDAA71 RSVD_TPAB2 FDI_LSYNC[1] CMOS IAB5 FDI_INT CMOS IAB7 CFG[17] CMOS IAB9 VSS GNDAB12 VTT1 REFAB14 VSS GNDAB15 VSS GNDAB17 VSS GNDAB19 VSS GNDAB21 VSS GNDAB23 VSS GNDAB24 VSS GNDAB26 VSS GNDAB28 VSS GNDAB30 VSS GNDAB32 VSS GNDAB33 VSS GNDAB35 VSS GNDAB37 VSS GNDAB39 VSS GNDAB41 VCC REFAB42 VSS GNDAB44 VCC REFAB46 VSS GNDAB48 VCC REFAB50 VSS GNDAB51 VCC REFAB53 VSS GNDAB55 VCC REFAB57 VSS GNDAB59 VCAP2 PWRAB60 VCAP2 PWRAB62 VSS GNDAB70 VSS GNDAC1 VSS GNDAC2 CFG[11] CMOS IAC4 CFG[12] CMOS IAC5 VSS GNDAC7 FDI_FSYNC[0] CMOS IAC9 FDI_FSYNC[1] CMOS IAC10 VSS GNDAC64 VSS GNDAC67 VSS GNDAC69 RSVDAC70 COMP2 Analog IAC71 RSVD_TPAD1 CFG[14] CMOS IAD4 VSS GNDAD12 VTT1 REFAD14 VTT1 REFAD15 VTT1 REFAD17 VAXG REFAD19 VAXG REFAD21 VAXG REFAD23 VAXG REFAD24 VAXG REF160 Datasheet

Processor Pin and Signal InformationTable 8-52.BGA1288 Processor BallList by Ball Number(Sheet 5 of 37)Table 8-52.BGA1288 Processor BallList by Ball Number(Sheet 6 of 37)Pin #Pin NameBufferTypeDirPin #Pin NameBufferTypeDirAD26 VAXG REFAD28 VAXG REFAD30 VTT0 REFAD32 VTT0 REFAD33 VTT0 REFAD35 VTT0 REFAD37 VTT0 REFAD39 VTT0 REFAD41 VCC REFAD42 VSS GNDAD44 VCC REFAD46 VSS GNDAD48 VCC REFAD50 VSS GNDAD51 VCC REFAD53 VSS GNDAD55 VCC REFAD57 VSS GNDAD59 VCAP2 PWRAD60 VCAP2 PWRAD62 VSS GNDAD69 COMP1 Analog IAD71 COMP3 Analog IAE2 CFG[13] CMOS IAE64 VSS GNDAE66 COMP0 Analog IAE70 VSS GNDAF1 VSS GNDAF4 CFG[8] CMOS IAF10 VSSAXG_SENSE Analog OAF12 VAXG_SENSE Analog OAF14 VAXG REFAF15 VAXG REFAF17 VAXG REFAF19 VAXG REFAF21 VAXG REFAF23 VAXG REFAF24 VAXG REFAF26 VAXG REFAF28 VAXG REFAF30 VTT0 REFAF32 VTT0 REFAF33 VTT0 REFAF35 VTT0 REFAF37 VTT0 REFAF39 VTT0 REFAF41 VCC REFAF42 VCC REFAF44 VCC REFAF46 VCC REFAF48 VCC REFAF50 VCC REFAF51 VCC REFAF53 VCC REFAF55 VCC REFAF57 VCC REFAF59 VCAP2 PWRAF6 CFG[16] CMOS IAF60 VCAP2 PWRAF62 VSS GNDAF69 VSS GNDAF71 GFX_VID[0] CMOS OAF8 CFG[15] CMOS IAG2 CFG[9] CMOS IAG6 VSS GNDAG7 CFG[7] CMOS IAG9 VSS GNDAG64 VSS GNDAG67 GFX_VID[1] CMOS OAG70 GFX_VID[2] CMOS OAH1 CFG[10] CMOS IAH4 VSS GNDDatasheet 161

Processor Pin and Signal InformationTable 8-52.BGA1288 Processor BallList by Ball Number(Sheet 7 of 37)Table 8-52.BGA1288 Processor BallList by Ball Number(Sheet 8 of 37)Pin #Pin NameBufferTypeDirPin #Pin NameBufferTypeDirAH12 VAXG REFAH14 VAXG REFAH15 VSS GNDAH17 VSS GNDAH19 VSS GNDAH21 VSS GNDAH23 VSS GNDAH24 VSS GNDAH26 VSS GNDAH28 VSS GNDAH30 VSS GNDAH32 VSS GNDAH33 VSS GNDAH35 VSS GNDAH37 VSS GNDAH39 VSS GNDAH41 VSS GNDAH42 VSS GNDAH44 VSS GNDAH46 VSS GNDAH48 VSS GNDAH50 VSS GNDAH51 VSS GNDAH53 VSS GNDAH55 VSS GNDAH57 VSS GNDAH59 VCAP2 PWRAH60 VCAP2 PWRAH62 VSS GNDAH66 RSVDAH69 GFX_VR_EN CMOS OAH71 GFX_VID[3] CMOS OAJ10 VAXG REFAJ2 CFG[5] CMOS IAJ70 VSS GNDAK1 CFG[2] CMOS IAK2 CFG[3] CMOS IAK4 CFG[4] CMOS IAK7 BCLK DIFFCLKAK8 BCLK # DIFFCLKAK12 VAXG REFAK14 VAXG REFAK15 VSS GNDAK17 VSS GNDAK19 VSS GNDAK21 VSS GNDAK23 VSS GNDAK24 VSS GNDAK26 VSS GNDAK28 VSS GNDAK30 VSS GNDAK32 VSS GNDAK33 VTT0 REFAK35 VTT0 REFAK37 VSS GNDAK39 VCAP1 PWRAK41 VSS GNDAK42 VCAP1 PWRAK44 VSS GNDAK46 VCAP1 PWRAK48 VSS GNDAK50 VCAP0 PWRAK51 VSS GNDAK53 VCAP0 PWRAK55 VSS GNDAK57 VCAP0 PWRAK59 VCAP2 PWRAK60 VCAP2 PWRAK62 VCAP2 PWRAK64 VSS GNDII162 Datasheet

Processor Pin and Signal InformationTable 8-52.BGA1288 Processor BallList by Ball Number(Sheet 9 of 37)Table 8-52.BGA1288 Processor BallList by Ball Number(Sheet 10 of 37)Pin #Pin NameBufferTypeDirPin #Pin NameBufferTypeDirAK66 RSVDAK69 RSVDAK70 VSS GNDAK71 RSVDAL1 VSS GNDAL4 CFG[0] CMOS IAL12 VTT0 REFAL14 VTT0 REFAL15 VTT0 REFAL17 VTT0 REFAL19 VAXG REFAL21 VAXG REFAL23 VAXG REFAL24 VAXG REFAL26 VAXG REFAL28 VAXG REFAL30 VAXG REFAL32 VAXG REFAL33 VSS GNDAL35 VSS GNDAL37 VSS GNDAL39 VCAP1 PWRAL41 VSS GNDAL42 VCAP1 PWRAL44 VSS GNDAL46 VCAP1 PWRAL48 VSS GNDAL50 VCAP0 PWRAL51 VSS GNDAL53 VCAP0 PWRAL55 VSS GNDAL57 VCAP0 PWRAL59 VTT0 REFAL60 VTT0 REFAL62 VSS GNDAL69 GFX_IMON CMOS OAL71 GFX_DPRSLPVR CMOS OAM10 VTT0 REFAM2 CFG[1] CMOS IAM5 SM_DRAMPWROK AsyncCMOSAM7 VCCPWRGOOD_1 AsyncCMOSAM8 VSS GNDAM64 VSS GNDAM66RSVDAM67 GFX_VID[5] CMOS OAM70 GFX_VID[6] CMOS OAN1 VTT_SELECT CMOS OAN4 VSS GNDAN5 VSS GNDAN7RSVD_TPAN9 VTT0 REFAN12 VTT0 REFAN14 VTT0 REFAN15 VTT0 REFAN17 VTT0 REFAN19 VAXG REFAN21 VAXG REFAN23 VAXG REFAN24 VAXG REFAN26 VAXG REFAN28 VAXG REFAN30 VAXG REFAN32 VAXG REFAN33 VTT0 REFAN35 VTT0 REFAN37 VSS GNDAN39 VCAP1 PWRAN41 VSS GNDAN42 VCAP1 PWRAN44 VSS GNDIIDatasheet 163

Processor Pin and Signal InformationTable 8-52.BGA1288 Processor BallList by Ball Number(Sheet 11 of 37)Table 8-52.BGA1288 Processor BallList by Ball Number(Sheet 12 of 37)Pin #Pin NameBufferTypeDirPin #Pin NameBufferTypeDirAN46 VCAP1 PWRAN48 VSS GNDAN50 VCAP0 PWRAN51 VSS GNDAN53 VCAP0 PWRAN55 VSS GNDAN57 VCAP0 PWRAN59 VTT0 REFAN60 VTT0 REFAN62 VSS GNDAN69 RSVDAN71 GFX_VID[4] CMOS OAP2 RSVD_TPAP64 VSS GNDAP66 RSVDAP70 VSS GNDAR1 VSS GNDAR4 VSS GNDAR12 VTT0 REFAR14 VSS GNDAR15 VSS GNDAR17 VSS GNDAR19 VSS GNDAR21 VSS GNDAR23 VSS GNDAR24 VSS GNDAR26 VSS GNDAR28 VSS GNDAR30 VSS GNDAR32 VSS GNDAR33 VSS GNDAR35 VSS GNDAR37 VCAP1 PWRAR39 VSS GNDAR41 VCAP1 PWRAR42 VSS GNDAR44 VCAP1 PWRAR46 VSS GNDAR48 VCAP0 PWRAR50 VSS GNDAR51 VCAP0 PWRAR53 VSS GNDAR55 VCAP0 PWRAR57 VSS GNDAR59 VTT0 REFAR60 VTT0 REFAR62 VSS GNDAR69 RSVDAR71 RSVDAT2 CFG[6] CMOS IAT6 SA_DQ[1] DDR3 I/OAT8 SA_DQ[0] DDR3 I/OAT10 VSS GNDAT64 VSS GNDAT67 RSVDAT70 RSVDAU1 RSVD_TPAU2 RSVDAU4 VSS GNDAU12 VTT0 REFAU14 VSS GNDAU15 VSS GNDAU17 VSS GNDAU19 VSS GNDAU21 VSS GNDAU23 VSS GNDAU24 VSS GNDAU26 VSS GNDAU28 VSS GNDAU30 VSS GNDAU32 VSS GNDAU33 VSS GND164 Datasheet

Processor Pin and Signal InformationTable 8-52.BGA1288 Processor BallList by Ball Number(Sheet 13 of 37)Table 8-52.BGA1288 Processor BallList by Ball Number(Sheet 14 of 37)Pin #Pin NameBufferTypeDirPin #Pin NameBufferTypeDirAU35 VSS GNDAU37 VCAP1 PWRAU39 VSS GNDAU41 VCAP1 PWRAU42 VSS GNDAU44 VCAP1 PWRAU46 VSS GNDAU48 VCAP0 PWRAU50 VSS GNDAU51 VCAP0 PWRAU53 VSS GNDAU55 VCAP0 PWRAU57 VSS GNDAU59 VTT0 REFAU60 VTT0 REFAU62 VSS GNDAU69 RSVDAU70 VSS GNDAU71 RSVDAV1 VSS GNDAV4 RSVDAV6 SA_DQ[5] DDR3 I/OAV7 SA_DQ[4] DDR3 I/OAV9 VSS GNDAV64 PM_EXT_TS#[1] CMOS I/OAV66 PM_EXT_TS#[0] CMOS I/OAV69 RSVDAV71 RSVDAW12 VTT0 REFAW14 VTT0 REFAW15 VTT0_DDR REFAW17 VTT0_DDR REFAW19 VTT0_DDR REFAW2 SB_DQ[1] DDR3 I/OAW21 VTT0_DDR REFAW23 VTT0_DDR REFAW24 VTT0_DDR REFAW26 VTT0_DDR REFAW28 VTT0_DDR REFAW30 VTT0_DDR REFAW32 VTT0_DDR REFAW33 VTT0 REFAW35 VTT0 REFAW37 VSS GNDAW39 VCAP1 PWRAW41 VSS GNDAW42 VCAP1 PWRAW44 VSS GNDAW46 VCAP1 PWRAW48 VSS GNDAW50 VCAP0 PWRAW51 VSS GNDAW53 VCAP0 PWRAW55 VSS GNDAW57 VCAP0 PWRAW59 VSS GNDAW60 VTT0 REFAW62 VSS GNDAW67 VSS GNDAW70 RSVD DDR3 I/OAY1 SB_DQ[4] DDR3 I/OAY4 VSS GNDAY5 SA_DQS#[0] DDR3 I/OAY7 SA_DQS[0] DDR3 I/OAY8 VSS GNDAY10 VTT0 REFAY12 VSS GNDAY14 VSS GNDAY15 VSS GNDAY17 VSS GNDAY19 VSS GNDAY21 VSS GNDDatasheet 165

Processor Pin and Signal InformationTable 8-52.BGA1288 Processor BallList by Ball Number(Sheet 15 of 37)Table 8-52.BGA1288 Processor BallList by Ball Number(Sheet 16 of 37)Pin #Pin NameBufferTypeDirPin #Pin NameBufferTypeDirAY23 VSS GNDAY24 VSS GNDAY26 VSS GNDAY28 VSS GNDAY30 VSS GNDAY32 VSS GNDAY33 VSS GNDAY35 VSS GNDAY37 VSS GNDAY39 VCAP1 PWRAY41 VSS GNDAY42 VCAP1 PWRAY44 VSS GNDAY46 VCAP1 PWRAY48 VSS GNDAY50 VCAP0 PWRAY51 VSS GNDAY53 VCAP0 PWRAY55 VSS GNDAY57 VCAP0 PWRAY59 VSS GNDAY60 VTT0 REFAY62 VSS GNDAY64 SA_DQ[62] DDR3 I/OAY66 VSS GNDAY69 RSVDAY71 VSS GNDB7 RSVDB9 RSVDB11 PEG_RBIAS Analog IB12 PEG_ICOMPI Analog IB14 PEG_RX#[15] PCIe IB16 PEG_RX[14] PCIe IB18 PEG_RX[13] PCIe IB19 PEG_RX[12] PCIe IB21 PEG_RX[11] PCIe IB23 PEG_RX#[10] PCIe IB25 PEG_RX[9] PCIe IB26 PEG_RX#[8] PCIe IB28 PEG_RX[7] PCIe IB30 PEG_TX[9] PCIe OB32 PEG_TX#[10] PCIe OB33 PEG_TX#[6] PCIe OB35 PEG_TX#[7] PCIe OB37 PEG_TX[4] PCIe OB39 PEG_TX[3] PCIe OB40 VSS GNDB42 VCC REFB44 VSS GNDB46 VCC REFB48 VSS GNDB49 VCC REFB51 VSS GNDB53 VCC REFB55 VSS GNDB56 VCC REFB58 VSS GNDB60 VCC REFB62 VSS GNDB63 CSC[1]/VID[4] CMOS I/OB65 VSS GNDBA2 SB_DQ[0] DDR3 I/OBA70 VSS GNDBB1 VSS GNDBB4 SB_DM[0] DDR3 OBB5 SA_DQ[2] DDR3 I/OBB7 VSS GNDBB9 SA_DQ[3] DDR3 I/OBB10 SA_DM[0] DDR3 OBB12 VDDQ_CK REFBB14 VDDQ_CK REFBB15 VDDQ REF166 Datasheet

Processor Pin and Signal InformationTable 8-52.BGA1288 Processor BallList by Ball Number(Sheet 17 of 37)Table 8-52.BGA1288 Processor BallList by Ball Number(Sheet 18 of 37)Pin #Pin NameBufferTypeDirPin #Pin NameBufferTypeDirBB17 VDDQ REFBB19 VDDQ REFBB21 VDDQ REFBB23 VDDQ REFBB24 VDDQ REFBB26 VDDQ REFBB28 VDDQ REFBB30 VDDQ REFBB32 VDDQ REFBB33 VDDQ REFBB35 VDDQ REFBB37 VCAP1 PWRBB39 VSS GNDBB41 VCAP1 PWRBB42 VSS GNDBB44 VCAP1 PWRBB46 VSS GNDBB48 VCAP0 PWRBB50 VSS GNDBB51 VCAP0 PWRBB53 VSS GNDBB55 VCAP0 PWRBB57 VSS GNDBB59 VTT0 REFBB60 VTT0 REFBB62 VSS GNDBB64 SA_DQ[58] DDR3 I/OBB66 SA_DQ[59] DDR3 I/OBB69 RSVDBB71 VSS GNDBC2 SB_DQ[5] DDR3 I/OBC67 SB_DQ[59] DDR3 I/OBC70 SA_DQ[63] DDR3 I/OBD1 SB_DQ[2] DDR3 I/OBD4 SB_DQS[0] DDR3 I/OBD14 VSS GNDBD15 VDDQ REFBD17 VDDQ REFBD19 VDDQ REFBD21 VDDQ REFBD23 VDDQ REFBD24 VDDQ REFBD26 VDDQ REFBD28 VDDQ REFBD30 VDDQ REFBD32 VDDQ REFBD33 VDDQ REFBD35 VDDQ REFBD37 VCAP1 PWRBD39 VSS GNDBD41 VCAP1 PWRBD42 VSS GNDBD44 VCAP1 PWRBD46 VSS GNDBD48 VCAP0 PWRBD50 VSS GNDBD51 VCAP0 PWRBD53 VSS GNDBD55 VCAP0 PWRBD57 VSS GNDBD59 VTT0 REFBD60 VTT0 REFBD69 SB_DQ[63] DDR3 I/OBD71 SB_DQ[62] DDR3 I/OBE1 VSS GNDBE2 SB_DQS#[0] DDR3 I/OBE4 SB_DQ[3] DDR3 I/OBE6 SA_DQ[6] DDR3 I/OBE8 SA_DQ[7] DDR3 I/OBE9 VSS GNDBE11 SA_DQ[9] DDR3 I/OBE62 SA_DQS#[7] DDR3 I/ODatasheet 167

Processor Pin and Signal InformationTable 8-52.BGA1288 Processor BallList by Ball Number(Sheet 19 of 37)Table 8-52.BGA1288 Processor BallList by Ball Number(Sheet 20 of 37)Pin #Pin NameBufferTypeDirPin #Pin NameBufferTypeDirBE64 SA_DQS[7] DDR3 I/OBE65 VSS GNDBE69 RSVDBE70 VSS GNDBE71 RSVDBF2 SB_DQ[6] DDR3 I/OBF6 SA_DQ[13] DDR3 I/OBF8 VSS GNDBF9 SA_DQ[12] DDR3 I/OBF11 SA_DQ[8] DDR3 I/OBF13 VSS GNDBF15 VDDQ REFBF16 VDDQ REFBF20 SA_CKE[0] DDR3 OBF21 SA_BS[2] DDR3 OBF28 SA_MA[9] DDR3 OBF30 VSS GNDBF38 SA_WE# DDR3 OBF40 SA_MA[13] DDR3 OBF43 SA_ODT[0] DDR3 OBF47 SA_DQ[34] DDR3 I/OBF48 SA_DQ[35] DDR3 I/OBF55 SA_DQ[48] DDR3 I/OBF57 SA_DQ[52] DDR3 I/OBF59 VTT0 REFBF60 VTT0 REFBF62 VSS GNDBF64 SA_DQ[57] DDR3 I/OBF65 SA_DQ[61] DDR3 I/OBF67 SB_DM[7] DDR3 OBF70 SB_DQ[57] DDR3 I/OBG1 SB_DQ[9] DDR3 I/OBG4 SB_DQ[8] DDR3 I/OBG15 SA_DQ[21] DDR3 I/OBG17 SA_DQ[18] DDR3 I/OBG24 SA_DQ[30] DDR3 I/OBG25 SA_DQ[31] DDR3 I/OBG32 SA_MA[4] DDR3 OBG34 SA_MA[3] DDR3 OBG36 VSS GNDBG43 VDDQ REFBG44 SA_DM[4] DDR3 OBG51 VSS GNDBG53 SA_DM[5] DDR3 OBG69 SB_DQS#[7] DDR3 I/OBG71 SB_DQ[58] DDR3 I/OBH2 SB_DQ[7] DDR3 I/OBH13 SA_DQ[11] DDR3 I/OBH15 VSS GNDBH17 SA_DQ[22] DDR3 I/OBH20 VSS GNDBH21 SA_DQ[29] DDR3 I/OBH24 VSS GNDBH25 SA_DQ[27] DDR3 I/OBH28 VDDQ REFBH30 SA_MA[11] DDR3 OBH32 VDDQ REFBH34 SA_MA[10] DDR3 OBH36 SA_CK#[1] DDR3 OBH38 SA_BS[1] DDR3 OBH40 SA_CS#[0] DDR3 OBH43 SA_DQ[37] DDR3 I/OBH44 SA_DQS#[4] DDR3 I/OBH47 VSS GNDBH48 SA_DQ[44] DDR3 I/OBH51 SA_DQS[5] DDR3 I/OBH53 SA_DQ[42] DDR3+C285BH55 VSS GNDBH57 VSS GNDI/OBH59 SA_DM[7] DDR3 I/OBH70 VSS GND168 Datasheet

Processor Pin and Signal InformationTable 8-52.BGA1288 Processor BallList by Ball Number(Sheet 21 of 37)Table 8-52.BGA1288 Processor BallList by Ball Number(Sheet 22 of 37)Pin #Pin NameBufferTypeDirPin #Pin NameBufferTypeDirBJ1 VSS GNDBJ4 SB_DQ[12] DDR3 I/OBJ5 SA_DQS[1] DDR3 I/OBJ7 SA_DQS#[1] DDR3 I/OBJ9 VSS GNDBJ10 SA_DM[1] DDR3 I/OBJ12 SM_DRAMRST# DDR3 OBJ20 SA_DQ[28] DDR3 I/OBJ21 VSS GNDBJ28 SA_MA[12] DDR3 OBJ30 SA_MA[7] DDR3 OBJ38 VDDQ REFBJ40 SA_DQ[32] DDR3 I/OBJ47 SA_CS#[1] DDR3 I/OBJ48 SA_DQ[45] DDR3 I/OBJ55 SA_DQ[43] DDR3 I/OBJ57 SA_DQ[53] DDR3 I/OBJ61 SA_DQ[51] DDR3 I/OBJ63 SA_DQ[56] DDR3 I/OBJ64 VSS GNDBJ66 SA_DQ[60] DDR3 I/OBJ69 SB_DQS[7] DDR3 I/OBJ71 SB_DQ[56] DDR3 I/OBK2 SB_DQ[13] DDR3 I/OBK5 SA_DQ[10] DDR3 I/OBK7 SA_DQ[14] DDR3 I/OBK9 SA_DQ[20] DDR3 I/OBK10 VSS GNDBK15 SA_DQ[19] DDR3 I/OBK17 SA_DQ[23] DDR3 I/OBK24 SA_CKE[1] DDR3 OBK25 SA_DQ[26] DDR3 I/OBK32 SA_MA[6] DDR3 OBK34 VSS GNDBK36 SA_CK[1] DDR3 OBK43 SA_CAS# DDR3 OBK44 SA_DQS[4] DDR3 I/OBK51 SA_DQS#[5] DDR3 I/OBK53 VSS GNDBK60 VSS GNDBK61 SA_DQ[55] DDR3 I/OBK63 VSS GNDBK64 SA_DQ[54] DDR3 I/OBK67 SB_DQ[61] DDR3 I/OBK70 SB_DQ[60] DDR3 I/OBL1 VSS GNDBL4 SB_DM[1] DDR3 OBL13 SA_DQS[2] DDR3 I/OBL20 VSS GNDBL21 SA_DQS#[3] DDR3 I/OBL28 VSS GNDBL30 VDDQ REFBL38 SA_RAS# DDR3 OBL40 VSS GNDBL47 SA_ODT[1] DDR3 OBL48 VSS GNDBL55 VSS GNDBL57 VSS GNDBL69 SB_DQ[55] DDR3 I/OBL71 VSS GNDBM3 SB_DQS#[1] DDR3 I/OBM15 SA_DM[2] DDR3 OBM17 VSS GNDBM24 VSS GNDBM25 VDDQ REFBM32 VSS GNDBM34 SA_CK[0] DDR3 OBM43 SA_DQ[33] DDR3 I/OBM44 VSS GNDBM51 VSS GNDBM53 SA_DQ[46] DDR3 I/OBM60 SA_DQS[6] DDR3 I/ODatasheet 169

Processor Pin and Signal InformationTable 8-52.BGA1288 Processor BallList by Ball Number(Sheet 23 of 37)Table 8-52.BGA1288 Processor BallList by Ball Number(Sheet 24 of 37)Pin #Pin NameBufferTypeDirPin #Pin NameBufferTypeDirBM70 VSS GNDBN1 VSS GNDBN4 SB_DQS[1] DDR3 I/OBN6 VSS GNDBN8 SA_DQ[15] DDR3 I/OBN9 SA_DQ[17] DDR3 I/OBN11 SA_DQ[16] DDR3 I/OBN13 SA_DQS#[2] DDR3 I/OBN17 SA_DQ[25] DDR3 I/OBN20 SA_DQ[24] DDR3 I/OBN21 SA_DQS[3] DDR3 I/OBN24 SA_DM[3] DDR3 OBN25 SA_MA[15] DDR3 OBN28 SA_MA[14] DDR3 OBN30 SA_MA[8] DDR3 OBN32 SA_MA[5] DDR3 OBN38 VDDQ REFBN40 SA_DQ[36] DDR3 I/OBN44 SA_DQ[38] DDR3 I/OBN47 SA_DQ[39] DDR3 I/OBN48 SA_DQ[40] DDR3 I/OBN51 SA_DQ[41] DDR3 I/OBN55 SA_DQ[47] DDR3 I/OBN57 SA_DQ[49] DDR3 I/OBN62 SA_DM[6] DDR3 OBN64 VSS GNDBN65 SA_DQ[50] DDR3 I/OBN68 SB_DQ[54] DDR3 I/OBN71 VSS GNDBP12 SB_DQ[21] DDR3 I/OBP15 SB_DQ[24] DDR3 I/OBP19 SB_DQ[28] DDR3 I/OBP22 SB_DM[3] DDR3 OBP26 SB_MA[7] DDR3 OBP30 SB_MA[1] DDR3 OBP33 SA_MA[1] DDR3 OBP35 SA_CK#[0] DDR3 OBP39 SM_RCOMP[1] AnalogBP42 VSS GNDBP46 SB_CS#[0] DDR3 OBP49 SB_DQ[35] DDR3 I/OBP53 SB_DQ[40] DDR3 I/OBP56 SB_DQ[44] DDR3 I/OBP58 SA_DQS#[6] DDR3 I/OBP60 SB_DQ[49] DDR3 I/OBR1 DC_TEST_BR1BR3 VSS GNDBR5 RSVD_TPBR6 SB_DQ[10] DDR3 I/OBR8 SB_DQ[11] DDR3 I/OBR10 SB_DQ[16] DDR3 I/OBR62 SB_DQ[52] DDR3 I/OBR64 SB_DQ[51] DDR3 I/OBR66 SB_DQ[50] DDR3 I/OBR68 VSS GNDBR69 VSS GNDBR71 DC_TEST_BR71BT1 DC_TEST_BT1BT3 DC_TEST_BT3BT5 RSVD_NCTFBT12 SB_DQ[17] DDR3 I/OBT13 SB_DM[2] DDR3 OBT15 SB_DQ[18] DDR3 I/OBT17 SB_DQS[3] DDR3 I/OBT19 SB_DQS#[3] DDR3 I/OBT20 SB_DQ[31] DDR3 I/OBT22 SB_DQ[27] DDR3 I/OBT24 SB_CKE[1] DDR3 OBT26 SB_CKE[0] DDR3 OBT27 SB_MA[9] DDR3 OBT29 SB_MA[12] DDR3 OBT31 SB_MA[6] DDR3 O170 Datasheet

Processor Pin and Signal InformationTable 8-52.BGA1288 Processor BallList by Ball Number(Sheet 25 of 37)Table 8-52.BGA1288 Processor BallList by Ball Number(Sheet 26 of 37)Pin #Pin NameBufferTypeDirPin #Pin NameBufferTypeDirBT33 SB_MA[5] DDR3 OBT34 SB_MA[0] DDR3 OBT36 SA_MA[0] DDR3 OBT38 SA_BS[0] DDR3 OBT40 SB_RAS# DDR3 OBT41 SB_WE# DDR3 OBT43 SB_CS#[1] DDR3 OBT45 SB_MA[13] DDR3 OBT47 SB_DQ[36] DDR3 I/OBT48 SB_DQ[32] DDR3 I/OBT50 SB_DQS[4] DDR3 I/OBT52 SB_DQS#[4] DDR3 I/OBT54 SB_DQ[39] DDR3 I/OBT55 SB_DQ[45] DDR3 I/OBT57 SB_DQ[43] DDR3 I/OBT59 SB_DQ[42] DDR3 I/OBT61 SB_DQ[53] DDR3 I/OBT68 VSS GNDBT69 DC_TEST_BT69BT71 DC_TEST_BT71BU7 VSS GNDBU9 SB_DQ[14] DDR3 I/OBU11 VSS GNDBU12 SB_DQS#[2] DDR3 I/OBU14 VSS GNDBU16 SB_DQ[23] DDR3 I/OBU18 VSS GNDBU19 SB_DQ[25] DDR3 I/OBU21 VSS GNDBU23 SB_MA[15] DDR3 OBU25 VSS GNDBU26 SB_MA[11] DDR3 OBU28 VDDQ REFBU30 SB_MA[3] DDR3 OBU32 VSS GNDBU33 SB_CK[0] DDR3 OBU35 VDDQ REFBU37 VSS GNDBU39 SB_CK#[1] DDR3 OBU40 VDDQ REFBU42 SB_MA[10] DDR3 OBU44 VSS GNDBU46 SB_CAS# DDR3 OBU48 VSS GNDBU49 SB_ODT[1] DDR3 OBU51 VSS GNDBU53 SB_DQ[41] DDR3 I/OBU55 VSS GNDBU56 SB_DQS[5] DDR3 I/OBU58 VSS GNDBU60 SB_DQ[46] DDR3 I/OBU62 VSS GNDBU63 SB_DQS#[6] DDR3 I/OBU65 SB_DM[6] DDR3 OBV1 DC_TEST_BV1BV3 DC_TEST_BV3BV5 DC_TEST_BV5BV6 RSVD_NCTFBV8 RSVD_NCTFBV10 SB_DQ[15] DDR3 I/OBV12 SB_DQ[20] DDR3 I/OBV13 SB_DQS[2] DDR3 I/OBV15 SB_DQ[19] DDR3 I/OBV17 SB_DQ[22] DDR3 I/OBV19 SB_DQ[29] DDR3 I/OBV20 SB_DQ[30] DDR3 I/OBV22 SB_DQ[26] DDR3 I/OBV24 SB_BS[2] DDR3 OBV26 SB_MA[14] DDR3 OBV27 SB_MA[8] DDR3 OBV29 SB_MA[2] DDR3 OBV31 SB_MA[4] DDR3 ODatasheet 171

Processor Pin and Signal InformationTable 8-52.BGA1288 Processor BallList by Ball Number(Sheet 27 of 37)Table 8-52.BGA1288 Processor BallList by Ball Number(Sheet 28 of 37)Pin #Pin NameBufferTypeDirPin #Pin NameBufferTypeDirBV33 SM_RCOMP[0] Analog IBV34 SB_CK#[0] DDR3 OBV36 SA_MA[2] DDR3 OBV38 SB_CK[1] DDR3 OBV40 SM_RCOMP[2] Analog IBV41 SB_BS[1] DDR3 OBV43 SB_BS[0] DDR3 OBV45 SB_ODT[0] DDR3 OBV47 SB_DM[4] DDR3 OBV48 SB_DQ[33] DDR3 I/OBV50 SB_DQ[34] DDR3 I/OBV52 SB_DQ[37] DDR3 I/OBV54 SB_DQ[38] DDR3 I/OBV55 SB_DQS#[5] DDR3 I/OBV57 SB_DM[5] DDR3 OBV59 SB_DQ[47] DDR3 I/OBV61 SB_DQ[48] DDR3 I/OBV62 SB_DQS[6] DDR3 I/OBV64 VSS GNDBV66 VSS GNDBV68 DC_TEST_BV68BV69 DC_TEST_BV69BV71 DC_TEST_BV71C3 DC_TEST_C3C5 RSVD_NCTFC68 VSS GNDC69 DC_TEST_C69C71 DC_TEST_C71D6 VSS GNDD8 RSVDD10 VSS GNDD12 PEG_RCOMPO Analog ID13 VSS GNDD15 PEG_RX[15] PCIe ID17 VSS GNDD19 PEG_RX#[13] PCIe ID20 VSS GNDD22 PEG_RX#[11] PCIe ID24 VSS GNDD26 PEG_RX#[9] PCIe ID27 VSS GNDD29 PEG_RX#[7] PCIe ID31 VSS GNDD33 PEG_TX[10] PCIe OD34 VSS GNDD36 PEG_TX[7] PCIe OD38 VSS GNDD40 PEG_TX#[3] PCIe OD41 VSS GNDD43 VCC REFD45 VCC REFD47 VCC REFD48 VCC REFD50 VCC REFD52 VCC REFD54 VCC REFD55 VCC REFD57 VCC REFD59 VCC REFD61 VID[1] CMOS OD62 VID[2] CMOS OD64 CSC[2]/VID[5] CMOS I/OD66 VID[6] CMOS OE1 DC_TEST_E1E3 RSVD_NCTFE5 VSS GNDE12 VSS GNDE16 VSS GNDE30 VSS GNDE33 VSS GNDE37 VSS GNDE42 VCC REF172 Datasheet

Processor Pin and Signal InformationTable 8-52.BGA1288 Processor BallList by Ball Number(Sheet 29 of 37)Table 8-52.BGA1288 Processor BallList by Ball Number(Sheet 30 of 37)Pin #Pin NameBufferTypeDirPin #Pin NameBufferTypeDirE46 VCC REFE50 VCC REFE53 VCC REFE57 VCC REFE60 VCC REFE68 VSS GNDE69 VSS GNDE71F1DC_TEST_E71RSVD_NCTFF4 VSS GNDF7 DMI_RX#[0] DMI IF9 DMI_RX[0] DMI IF10 DMI_TX#[3] DMI OF20 VSS GNDF21 PEG_TX[14] PCIe OF28 VSS GNDF40 PEG_RX[0] PCIe IF47 VSS GNDF48 VSS GNDF55 VCC REFF61 VSS GNDF63 VSS_SENSE Analog OF64 VCC_SENSE Analog OF66 PROC_DPRSLPVR CMOS OF68 PSI# AsyncCMOSF71 VSS GNDG3 RSTIN# CMOS IG13 DMI_TX[2] DMI OG15 VSS GNDG17 DMI_TX[0] DMI OG20 VSS GNDG21 PEG_TX#[14] PCIe OG24 VSS GNDG25 PEG_RX[5] PCIe IG28 PEG_RX#[4] PCIe IOG30 VSS GNDG32 PEG_TX#[5] PCIe OG34 PEG_RX[2] PCIe IG38 PEG_RX#[1] PCIe IG40 PEG_RX#[0] PCIe IG43 VSS GNDG44 VCC REFG47 VSS GNDG48 VSS GNDG51 VCC REFG53 VSS GNDG55 VCC REFG57 VSS GNDG60 VCC REFG70 VSS GNDH1 VSS GNDH15 VTTPWRGOOD AsyncCMOSH17 DMI_TX#[0] DMI OH24 PEG_RX#[6] PCIe IH25 PEG_RX#[5] PCIe IH32 PEG_TX[5] PCIe OH34 PEG_RX#[2] PCIe IH36 VSS GNDH43 VSS GNDH44 VCC REFH51 VCC REFH53 VSS GNDH60 VCC REFH71 VSS GNDJ11 DMI_TX[3] DMI OJ13 DMI_TX#[2] DMI OJ2 DMI_RX[3] DMI IJ4 DMI_RX#[3] DMI IJ6 DMI_RX[1] DMI IJ8 DMI_RX#[1] DMI IIDatasheet 173

Processor Pin and Signal InformationTable 8-52.BGA1288 Processor BallList by Ball Number(Sheet 31 of 37)Table 8-52.BGA1288 Processor BallList by Ball Number(Sheet 32 of 37)Pin #Pin NameBufferTypeDirPin #Pin NameBufferTypeDirJ9 VSS GNDJ20 PEG_TX#[15] PCIe OJ21 PEG_CLK# DIFFCLKJ28 PEG_RX[4] PCIe IJ30 PEG_TX[8] PCIe OJ38 PEG_RX[1] PCIe IJ40 VSS GNDJ47 VSS GNDJ48 VSS GNDJ55 VCC REFJ57 VSS GNDJ62 BPM#[2] GTL I/OJ64 BPM#[5] GTL I/OJ65 VSS GNDJ67 BPM#[1] GTL I/OJ69 BPM#[0] GTL I/OJ70 BCLK_ITP # DIFFCLKK1 FDI_TX[0] FDI OK4 VSS GNDK6 VSS GNDK8 DMI_RX#[2] DMI IK9 DMI_RX[2] DMI IK11 VSS GNDK15 DMI_TX#[1] DMI OK17 VSS GNDK24 PEG_RX[6] PCIe IK25 VSS GNDK32 VSS GNDK34 VSS GNDK36 VSS GNDK43 VSS GNDK44 VCC REFK51 VCC REFK53 VSS GNDIOK60 VCC REFK62 BPM#[4] GTL I/OK64 VSS GNDK65 BPM#[3] GTL I/OK69 BPM#[6] GTL I/OK71 BCLK_ITP DIFFCLKL2 FDI_TX#[0] FDI OL13 VSS GNDL20 PEG_TX[15] PCIe OL21 PEG_CLK Diff CLK IL28 PEG_TX#[11] PCIe OL30 PEG_TX#[8] PCIe OL38 PEG_TX#[1] PCIe OL40 PEG_TX[0] PCIe OL47 VSS GNDL48 VSS GNDL55 VCC REFL57 VSS GNDL70 VSS GNDM1 VSS GNDM4 FDI_TX#[2] FDI OM15 DMI_TX[1] DMI OM17 PM_SYNC CMOS IM24 PEG_TX#[13] PCIe OM25 PEG_TX[12] PCIe OM32 PEG_TX#[2] PCIe OM34 PEG_RX[3] PCIe IM36 VSS GNDM42 VSS GNDM44 VCC REFM51 VCC REFM53 VSS GNDM60 VCC REFM69 BPM#[7] GTL I/OO174 Datasheet

Processor Pin and Signal InformationTable 8-52.BGA1288 Processor BallList by Ball Number(Sheet 33 of 37)Table 8-52.BGA1288 Processor BallList by Ball Number(Sheet 34 of 37)Pin #Pin NameBufferTypeDirPin #Pin NameBufferTypeDirM71PROC_DETECTN2 FDI_TX[2] FDI ON5 FDI_TX[1] FDI ON7 FDI_TX#[1] FDI ON9 FDI_TX[4] FDI ON10 FDI_TX#[4] FDI ON13 VTT_SENSE Analog ON15 VSS GNDN17 THERMTRIP# AsyncGTLN19 PECI Async I/ON21 VSS GNDN24 PEG_TX[13] PCIe ON26 PEG_TX#[12] PCIe ON28 PEG_TX[11] PCIe ON30 VSS GNDN32 PEG_TX[2] PCIe ON38 PEG_TX[1] PCIe ON40 PEG_TX#[0] PCIe ON42 VCC REFN44 VCC REFN46 VSS GNDN48 VCC REFN50 VSS GNDN51 VCC REFN53 VSS GNDN55 VCC REFN57 VSS GNDN61 CATERR# GTL I/ON63 VSS GNDN65 TMS CMOS IN67 PROCHOT# AsyncGTLN70 RESET_OBS# AsyncCMOSOI/OP1 FDI_TX#[3] FDI OOP4 VSS GNDP34 PEG_RX#[3] PCIe IP60 VCC REFP69 TRST# CMOS IP71 TDI_M CMOS IR2 FDI_TX[3] FDI OR5 VSS GNDR7 FDI_TX#[5] FDI OR8 FDI_TX[5] FDI OR12 VSS_SENSE_VTT Analog OR14 VSS GNDR15 VTT1 REFR17 VTT1 REFR19 VTT1 REFR21 VTT1 REFR23 VTT0 REFR24 VTT0 REFR26 VTT0 REFR28 VTT0 REFR30 VTT0 REFR32 VTT0 REFR33 VTT0 REFR35 VTT0 REFR37 VCCPLL REFR39 VCCPLL REFR41 VCC REFR42 VSS GNDR44 VCC REFR46 VSS GNDR48 VCC REFR50 VSS GNDR51 VCC REFR53 VSS GNDR55 VCC REFR57 VSS GNDR59 VCAP2 PWRDatasheet 175

Processor Pin and Signal InformationTable 8-52.BGA1288 Processor BallList by Ball Number(Sheet 35 of 37)Table 8-52.BGA1288 Processor BallList by Ball Number(Sheet 36 of 37)Pin #Pin NameBufferTypeDirPin #Pin NameBufferTypeDirR60 VCAP2 PWRR62 VSS GNDR64 RSVDR66 RSVDR70 VSS GNDT1 VSS GNDT2 RSVDT4 RSVDU6 FDI_TX[6] FDI OU7 FDI_TX#[6] FDI OU9 VSS GNDT67 TCK CMOS IT69 TDI CMOS IT70 TDO_M CMOS OT71 TDO CMOS OU1 RSVDU4 VSS GNDU12 VTT1 REFU14 VTT1 REFU15 VTT1 REFU17 VTT1 REFU19 VTT1 REFU21 VTT1 REFU23 VTT0 REFU24 VTT0 REFU26 VTT0 REFU28 VTT0 REFU30 VTT0 REFU32 VTT0 REFU33 VTT0 REFU35 VTT0 REFU37 VCCPLL REFU39 VSS GNDU41 VCC REFU42 VSS GNDU44 VCC REFU46 VSS GNDU48 VCC REFU50 VSS GNDU51 VCC REFU53 VSS GNDU55 VCC REFU57 VSS GNDU59 VCAP2 PWRU60 VCAP2 PWRU62 VSS GNDU64 VSS GNDU69 PREQ# AsyncGTLU71 PRDY# AsyncGTLV2RSVDV70 VSS GNDW1 VSS GNDW4 DPLL_REF_SSCLK# DIFFCLKW6 VSS GNDW8 FDI_TX#[7] FDI OW10 FDI_TX[7] FDI OW12 VTT1 REFW14 VTT1 REFW15 VTT1 REFW17 VTT1 REFW19 VTT1 REFW21 VTT1 REFW23 VTT0 REFW24 VTT0 REFW26 VTT0 REFW28 VTT0 REFW30 VTT0 REFW32 VTT0 REFW33 VTT0 REFW35 VTT0 REFIOI176 Datasheet

Processor Pin and Signal InformationTable 8-52.BGA1288 Processor BallList by Ball Number(Sheet 37 of 37)Pin #Pin NameBufferTypeDirW37 VCCPLL REFW39 VCCPLL REFW41 VCC REFW42 VSS GNDW44 VCC REFW46 VSS GNDW48 VCC REFW50 VSS GNDW51 VCC REFW53 VSS GNDW55 VCC REFW57 VSS GNDW59 VCAP2 PWRW60 VCAP2 PWRW62 VSS GNDW64W66VCAP0_VSS_SENSEVCAP0_SENSEW69 VSS GNDW71 DBR# OY2 DPLL_REF_SSCLK DIFFCLKY67 VCCPWRGOOD_0 AsyncCMOSY70 TAPPWRGOOD AsyncCMOSIIODatasheet 177

Processor Pin and Signal Information8.2 Package Mechanical InformationFigure 8-25. rPGA Mechanical Package (Sheet 1 of 2)178 Datasheet

Processor Pin and Signal InformationFigure 8-26.rPGA Mechanical Package (Sheet 2 of 2)Datasheet 179

Processor Pin and Signal InformationFigure 8-27.BGA Mechanical Package (Sheet 1 of 2)180 Datasheet

Processor Pin and Signal InformationFigure 8-28.BGA Mechanical Package (Sheet 2 of 2)§Datasheet 181