CHAPTER 8: MEMORY MANAGEMENT

Base and Limit RegistersA f b d li i d f h A pair of base and limit registers define thelogical address space

Multistep Processing of a User Program

Logical vs. Physical Address SpaceThe concept of a logical address space that is bound to a separatephysical address space is central to proper memory management Logical address – generated by the CPU; also referred to as virtual address Physical address – address seen by the memory unitLogical and physical addresses are the same in compile-time andload-time address-binding schemes.Logical (virtual) and physical addresses differ in execution-timeaddress-binding scheme

Memory-Management Management Unit (MMU)Hardware device that maps virtual to physical addressIn MMU scheme, the value in the relocation register is added toevery address generated by a user process at the time it is sentto memoryThe user program deals with logical addresses; it never sees thereal physical addresses

Dynamic relocation using a relocation register

OverlaysKeep in memory only those instructions ti and data that t areneeded at any given time.Needed when a process is larger than amount of memoryallocated to it.Implemented by users, no special support needed fromoperating system, programming design of overlay structure iscomplex

Overlays for a Two-Pass Assembler

SwappingA process can be swapped temporarily out of memory to abacking store, and then brought back into memory for continuedexecutionBacking store fast disk large enough to accommodate copies of all memory images forall users; must provide direct access to these memory imagesRoll out, roll in swapping variant used for priority-based scheduling algorithms; lowerpriorityprocess is swapped out so higher-priority process can be loadedand executed

SwappingMajor part of swap time is transfer time; total transfer time isdirectly proportional to the amount of memory swappedModified versions of swapping are found on many systems (i.e.,UNIX, Linux, and Windows)

Schematic View of Swapping

Contiguous AllocationMain memory usually can be divided into two partitions: Resident operating system, usually held in low memory with interrupt vector User processes then held in high memoryRelocation registers used to protect user processes from eachother, and from changing operating-system code and data Base register contains value of smallest physical address Limit register contains range of logical addresses – each logical addressmust be less than the limit register MMU maps logical address dynamically

Hardware support for relocation and limitregisters

Memory Allocation How to satisfy a request of size n from a list of free holes First-fit: Allocate the first hole that is big enough Best-fit: Allocate the smallest hole that is big enough; must search entire list,unless ordered by size. Produces the smallest leftover hole. Worst-fit: Allocate the largest hole; must also search entire list. Producesthe largest leftover hole.First fit and best fit are usually better than worst fit in terms of speedFirst-fit and best-fit are usually better than worst-fit in terms of speedand storage utilization

FragmentationExternal Fragmentation total memory space satisfies a request, but it is not contiguousInternal Fragmentation allocated memory may be slightly larger than requested memory;y y g y g q y;this size difference is memory internal to a partition, but not beingused

Fragmentation (cont.)Rd Reduce external fragmentation by compaction Shuffle memory contents to place all free memory together in one largeblock Compaction is possible only if relocation is dynamic, and is done atexecution time I/O problem• Latch job in memory while it is involved in I/O• Do I/O only into OS buffers

PagingLogical address space of a process can be noncontiguous; processis allocated physical memory whenever the latter is availableDivide physical memory into fixed-sized blocks called frames(size is power of 2, between 512 bytes and 8192 bytes)Divide logical memory into blocks of same size called pages.

PagingKeep track of all free framesTo run a program of size n pages, need to find n free framesand load programSet up a page table to translate logical to physical addressesInternal fragmentation

Address Translation SchemeAddress generated by CPU is divided id d into: Page number (p) – used as an index into a page tablewhich contains base address of each page in physicalmemory Page offset (d) – combined with base address to definethe physical memory address that is sent to the memoryunitpage number page offsetpm - n For given logical address space 2 m and page size 2 ndn

Paging hardware

Paging Example

Associative Memory Associative memory – parallel searchPage # Frame #Address translation (p, d) If p is in associative register, get frame # out Otherwise get frame # from page table in memory

Paging Hardware With TLB

Effective Access TimeAssociative Lookup = ε time unitAssume memory cycle time is 1 microsecondHit ratio – percentage of times that a page number is found inthe associative registers; ration related to number of associativeregistersHit ratio = αEffective e Access Time (EAT)EAT = (1 + ε) α + (2 + ε)(1 – α)= 2 + ε – α

Memory ProtectionMemory protection implemented by associating protection bit witheach frameValid-invalid bit attached to each entry in the page table: “valid” indicates that the associated page is in the process’ logical addressspace, and is thus a legal page “invalid” indicates that the page is not in the process’ ’ logical address space

Valid (v) () or Invalid () (i) Bit In A PageTable

Shared PagesShared code One copy of read-only (reentrant) code shared among processes (i.e., texteditors, compilers, window systems). Shared code must appear in same location in the logical address space ofall processesPrivate code and data Each process keeps a separate copy of the code and data The pages for the private code and data can appear anywhere in thelogical address space

Sharing of code in a pagingenvironment

Structure of Page TableHierarchical PagingHashed Page TablesInverted Page Tables

Hierarchical Page TablesBreak up the logical address space into multiple page tablesA simple technique is a two-level page table

Two-Level Page-Table Scheme

Two-Level Paging ExampleA logical address (on 32-bit machine with 4K page size) is divided into: a page number consisting of 20 bits a page offset consisting of 12 bitsSince the page table is paged, the page number is further divided id d into: a 10-bit page number a 10-bit page offsetThus, a logical address is as follows:page numberpage offsetp ip 2 dwhere p i is an index into the outer page table, and p 2 is the displacement10 10 12within the page of the outer page table

Address-Translation SchemeAddress-translation scheme for a two-level 32-bit pagingarchitecture

Three-level Paging Scheme

Hashed Page TablesCommon in address spaces > 32 bitsThe virtual page number is hashed h into a page table. This pagetable contains a chain of elements hashing to the same location.Virtual page numbers are compared in this chain searching fora match. If a match is found, the corresponding physical frameis extracted.

Hashed Page Table

Inverted Page TableOne entry for each real page of memoryEntry consists of the virtual address of the page stored in thatreal memory location, with information about the process thatowns that pageDecreases memory needed to store each page table, butincreases time needed d to search the table when a pagereference occurs Use hash table to limit the search to one — or at most a few —page-table entries

Inverted Page Table Architecture

SegmentationMemory-management management scheme that supports user view ofmemoryA program is a collection of segments. A segment is a logicalunit such as:main program,procedure,function,method,object,local variables, global variables,common block,stack,symbol table, arrays

User’s s View of a Program

Logical View of Segmentation11423423user spacephysical memory space

Segmentation ArchitectureLogical address consists of a two tuple:,Segment table – maps two-dimensional i physical addresses; eachtable entry has: base – contains the starting physical address where the segments reside inmemory limit – specifies the length of the segmentSegment-table base register (STBR) points to the segment table’slocation in memorySegment-table length register (STLR) indicates number of segmentsused by a program;segment number s is legal if s < STLR

Segmentation Architecture (Cont.)Relocation. dynamic by segment tableSharing. shared segments same segment numberAllocation. first fit/best fit external fragmentation

Segmentation Architecture (Cont.)Protection. With each entry in segment table associate: validation bit = 0 ⇒ illegal segment read/write/execute privilegesProtection bits associated with segments; code sharing occurs atsegment levelSince segments vary in length, memory allocation is a dynamicstorage-allocation problemA segmentation example is shown in the following diagram

Segmentation hardware

Example of Segmentation

Sharing of Segments

Example: The Intel Pentium Supports both segmentation and segmentation withpaging CPU generates logical address Given to segmentation unit• Which produces linear addresses Linear address given to paging unit• Which generates physical address in main memory• Paging units form equivalent of MMU

Logical to Physical Address Translation in Pentium

Intel Pentium Segmentation

Pentium Paging Architecture

Linear Address in LinuxBroken into four parts:

Three-level Paging in Linux

END OF CHAPTER 8