Simultaneous Multithreading â Blending Thread-level and ...

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Komodo microcontroller [3,15] which is a multithreadedJava microcontroller aimed at embedded real-timesystems with a hardware event handling mechanism thatallows handling of simultaneous overlapping events withhard real-time requirements.Compared to the cycle-by-cycle interleavingtechnique, in block-interleaving a smaller number ofthreads is needed and a single thread can execute at fullspeed until the next context switch. In addition, singlethreadperformance is similar to the performance of acomparable processor without multithreading.5 Simultaneous MultithreadingCycle-by-cycle interleaving and block interleaving aremultithreading techniques which are most efficient whenapplied to scalar RISC or VLIW processors. Combiningmultithreading with the superscalar technique naturallyleads to a technique where all hardware contexts areactive simultaneously, competing each cycle for allavailable resources. This technique, called simultaneousmultithreading (SMT), inherits from superscalars theability to issue multiple instructions each cycle; and likemultithreaded processors it contains hardware resourcesfor multiple contexts. The result is a processor that canissue multiple instructions from multiple threads eachcycle. Therefore, not only can unused cycles in the caseof latencies be filled by instructions of alternativethreads, but so can unused issue slots within one cycle.Thread-level parallelism can come from eithermultithreaded, parallel programs or from individual,independent programs in a multiprogramming workload,while instruction-level parallelism is utilized from theindividual threads. Because a SMT processorsimultaneously exploits thread-level and instructionlevelparallelism, it uses its resources more efficientlyand thus achieves better throughput and speedup thansingle-threaded superscalar processors for multithreaded(or multiprogramming) workloads. The trade-off is aslightly more complex hardware organization.The SMT approach combines a wide superscalarinstruction issue with the multithreading approach byproviding several register sets on the multiprocessor andissuing instructions from several instruction queuessimultaneously. Therefore, the issue slots of a wide-issueprocessor can be filled by operations of several threads.Latencies occurring in the execution of single threads arebridged by issuing operations of the remaining threadsloaded on the processor. In principle, the full issuebandwidth can be utilized. The SMT fetch unit can takeadvantage of the interthread competition for instructionbandwidth in two ways. First, it can partition thisbandwidth among the threads and fetch from severalthreads each cycle. In this way, it increases theprobability of fetching only nonspeculative instructions.Second, the fetch unit can be selective about whichthreads it fetches. For example, it may fetch those thatwill provide the most immediate performance benefit.The main drawback to SMT may be that itcomplicates the issue stage, which is always central tothe multiple threads. A functional partitioning asdemanded for processors of the 10 9 -transistor era cannottherefore be easily reached.SMT processors can be organized in the followingtwo ways.5.1 Shared-resources TechniqueThey may share an aggressive pipeline among multiplethreads when there is insufficient instruction-levelparallelism in any one thread to use the pipeline fully.Instructions of different threads share all resources suchas the fetch buffer, the physical registers for renamingregisters of different register sets, the instructionwindow, and the reorder buffer. Thus SMT addsminimal hardware complexity to conventionalsuperscalars; hardware designers can focus on building afast single-threaded superscalar and add multithreadcapability on top. The complexity added to superscalarsby multithreading include the thread tag for each internalinstruction representation, multiple register sets, and theabilities of the fetch and the retire units to fetch/retireinstructions of different threads.5.2 Replicated-resources TechniqueThe second organizational form replicates all internalbuffers of a superscalar such that each buffer is bound toa specific thread. Instruction fetch, decode, rename, andretire units may be multiplexed between the threads or beduplicated themselves. The issue unit is able to issueinstructions of different instruction windowssimultaneously to the execution units. This form oforganization adds more changes to the organization ofsuperscalar processors but leads to a natural partitioningof the instruction window and simplifies the issue andretire stages.5.3 Processor ExamplesUntil recently no commercial SMT processors exist.There were, however, several projects simulatingdifferent configurations of SMT processors and (at least)one which implemented SMT in hardware [6]. In whatfollows we briefly mention some of them.At the University of Washington two simulations ofthe SMT processor architecture were made. The fist wasbased on an enhancement of the Alpha 21164 processor[29]. Simulations were conducted to evaluate processorconfigurations of an up to 8-threaded and 8-issuesuperscalar. This maximum configuration with 32execution units showed a throughput of 6.64 IPC on theSPEC92 benchmark suite. The next simulation was
ased on a hypothetical out-of-order issue superscalarmicroprocessor that resembles the MIPS R10000 and HPPA-8000 [7]. This approach evaluated more realisticprocessor configurations, again with the 8-threaded and8-issue superscalar organization and reached athroughput of 5.4 IPC on the same benchmarks.The SMT processor simulated at the University ofKarlsruhe [23] was based on a simplified PowerPC 604processor with multimedia enhancement [21]. Thesimulations showed that a single-threaded, 8-issuemaximum processor (assuming an abundance ofresources) reaches an IPC count of only 1.60, while an8-threaded 8-issue processor reaches an IPC of 6.07. Amore realistic processor model reaches an IPC of 1.21 inthe single-threaded 8-issue and 3.11 in the 8-threaded 8-issue model. Increasing the issue bandwidth from 4 to 8yields only a marginal gain (except for the 4-threaded to8-threaded maximum processor). Increasing the numberof threads from single-threaded to 2-threaded or 4-threaded yields a high gain for the 2-issue to 8-issuemodel, and a significant gain for the 8-threaded model.The steepest performance increases arise for the 4-issuemodel from the single-threaded (IPC of 1.21) to the twothreaded(IPC of 2.07) and to the 4-threaded (IPC of2.97) cases. In [21] a 2-threaded 4-issue or 4-threaded 4-issue processor configurations are suggested as realisticnext generation processor.At the University of California at Irvine combinedout-of-order execution within an instruction stream withthe simultaneous execution of instructions of differentinstruction streams [19] which resulted in the superscalardigital signal processor. Based on simulations aperformance gain of 20–55% due to multithreading wasachieved across a range of benchmarks. Similarly, at thePolytechnic University of Catalunya combinedsimultaneous multithreaded execution and out-of-orderexecution with an integrated vector unit and vectorinstructions [8]. Recently, a commercial four-threadedSMT processor Alpha 21464 has been announced.6 ConclusionResearch on multithreaded architectures has beenmotivated by two concerns: tolerating memory latencyand bridging of synchronization waits by rapid contextswitches. Older multithreaded processor approachesfrom the 1980s usually extend scalar RISC processors bya multithreading technique and focus at effectivelybridging very long remote memory access latencies.Such processors will only be useful as processor nodesin distributed-shared-memory multiprocessors. However,developing a processor that is specifically designed fordistributed-shared-memory multiprocessors is commonlyregarded as too expensive. Multiprocessors todaycomprise standard off-the-shelf microprocessors andalmost never specifically designed processors (with theexception of Tera MTA and SPELL). Therefore, newermultithreaded processor approaches also strive fortolerating smaller latencies that arise from primary cachemisses that hit in secondary cache, from long-latencyoperations, or even from unpredictable branches.Multithreaded processors aim at a low execution timeof a multithreaded workload, while a superscalarprocessor aims at a low execution time of a singleprogram. Depending on the implemented multithreadingtechnique, a multithreaded processor running only asingle thread does not reach the same efficiency as acomparable single-threaded processor. The penalty maybe only slight in the case of a block-interleavingprocessor or be several times as long as the run-time on asingle-threaded processor in the case of a cycle-by-cycleinterleaving processor.Reeferences:[1] A. Agarwal, J. Babb, D. Chaiken, G. D'Souza, K. L.Johnson, D. Kranz, J. Kubiatowicz, B.-H. Lim, G.Maa, K. Mackenzie, Sparcle: A multithreaded VLSIprocessor for parallel computing, Lect. NotesComput. Sc., Vol.748, 1993, pp.359.[2] R. Alverson, D. Callahan, D. Cummings, B.Koblenz, A. Porterfield, J.B. Smith, The Teracomputer system, Proc. 1990 Int. Conf.Supercomput., Amsterdam, The Nederland, June1990, pp.1-6.[3] U. Brinkschulte, C. Krakowski, J. Kreuzinger, T.Ungerer, A multithreaded Java microcontroller forthread-oriented real-time event-handling, Proc. 1999Conf. PACT, Newport Beach, CA, 1999, pp.34-39.[4] M. Butler, T.-Y. Yeh, Y.N. Patt, M. Alsup, H.Scales, M. Shebanow, Single instruction streamparallelism is greater than two. Proc. 18th Ann.Symp. Comp. Arch., Toronto, Canada, May 1991,pp.276-286.[5] M. Dorojevets, COOL Multithreading in HTMTSPELL-1 processors, Intl. Journal on High SpeedElectronics and Systems, 1999. (to be published).[6] M.N. Dorozhevets, P. Wolcott, The El'brus-3 andMARS-M: Recent advances in Russian highperformancecomputing, The Journal ofSupercomputing, Vol.6, 1992, pp.5-48.[7] S.J. Eggers, J.S. Emer, H.M. Levy, J.L. Lo, R.M.Stamm, D.M. Tullsen, Simultaneous multit-hreading:A platform for next-generation processors, IEEEMicro, Vol.17, September/October 1997, pp.12-19.[8] R. Espasa, M. Valero, Exploiting instruction- anddata-level parallelism, IEEE Micro, Vol.17,September/October 1997, pp.20-27.[9] A. Formella, J. Keller, T. Walle, HPP: A high performancePRAM, Lect. Notes Comput. Sc., Vol.1123,1996, pp.425-434.
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