16700 Series Logic Analysis System - Equipland Inc.

16700 SeriesLogic Analysis SystemProduct OverviewDebugging today's digital systemsis tougher than ever. Increasedproduct requirements, complexsoftware, and innovative hardwaretechnologies make it difficult tomeet your time-to-market goals.The Agilent Technologies16700 Series logic analysis systemsprovide the simplicity and power youneed to conquer complex systemsby combining state/timing analysis,oscilloscopes, pattern generators,post-processing tool sets, andemulation in one integrated system.

Table of ContentsSystem OverviewModular Design page 3Features and Benefits page 4Selecting the Right System page 6MainframesDisplay page 7Back Panel page 8System Screens page 9IntuiLink page 12Probing SolutionsCriteria for Selection page 13Technologies page 14Data Acquisition and StimulusState/Timing Modules page 17Oscilloscope Modules page 30Pattern Generation Modules page 33Emulation Modules page 37Post-Processing and Analysis Tool SetsSoftware Tool Sets page 39Source Correlation page 41Data Communications page 45System Performance Analysis page 54Serial Analysis page 61Tool Development Kit page 67Licensing Information page 73Time Correlation with Agilent Infiniium OscilloscopesE5850A Logic Analyzer - Oscilloscope Time Correlation Fixture page 74Technical Specifications and CharacteristicsMainframe page 75Probing Solutions page 83State/Timing Modules page 85Oscilloscope Modules page 101Pattern Generation Modules page 104Trade-In, Trade-Up page 115Ordering Information page 116Third-Party Solutions page 123Support, Warranty and Related Literature page 124Sales Offices Information page 1252

System OverviewModular DesignModular Design Protects YourLong-Term InvestmentModularity is the key to the Agilent16700 Series logic analysis systems'long term value. You purchase onlythe capability you need now, thenexpand as your needs evolve. Allmodules are tightly integrated toprovide time-correlated, crossdomain measurements.Module ChoicesState/TimingHigh-Speed TimingOscilloscopesPattern GenerationEmulationUser BenefitsAgilent offers a wide variety of state/timing modules for a rangeof applications, from high-speed glitch capture to multi-channelbus analysis.Precisely characterize setup/hold times over a wide channelcount. Capture data over many clock cycles while retaining thehighest multi-channel accuracy.Identify signal integrity issues and characterize signals quicklywith automatic measurements of rise time, voltage, pulse width,and frequency.Use stimulus to substitute for missing system components or toprovide a stimulus-response test environment.An emulation module connects to the debug port (BDM or JTAG)on your target. You have full access to processor executioncontrol features of the module through the built-in emulationcontrol interface or a third-party debugger.External PortsTarget Control PortPort-in/Port-outUse the target control port to force a reset of your target oractivate a target interrupt.A BNC connector allows you to trigger or arm external devicesor to receive signals that can be used to arm acquisitionmodules within your logic analyzer.Helpenables you toaccess the onlineuser’s guide andmeasurementexamples.Figure 1.1. The system boot up screen shows youwhat modules are configured into your logicanalysis system.3

System OverviewFeatures and BenefitsSystem CapabilityNEW Touch Screen InterfaceNEW Multiframe ConfigurationNEW Enhanced Mainframe HardwareScalable System• State/timing analyzers• High-speed timing• Oscilloscopes• Pattern generators• Emulation modulesThe Agilent 16702B mainframe supports a large, 12.1 inch LCD touch screen and redesigned front panelcontrols for an easy-to-operate, self-contained unit requiring minimal bench space and offering simpleportability.By connecting up to eight mainframes and expanders you can simultaneously view time-correlated traces forall buses in a large channel count, multibus system.Mainframe now includes a 40X CD-ROM drive, a 9 GB hard disk drive, 100BaseT-X LAN, and 128 MB ofinternal system RAM (optional 256 MB total).• Select the optimum combination of performance, features, and price that you need for your specificapplication today, with the flexibility to add to your system as your measurement needs change.• View system activity from signals to source code.Measurement Modules/InterfacesThe Agilent 16760AState/Timing ModuleWith up to 1.5 Gb/s state speed, the 16760A lets you debug today’s and tomorrow’s ultra-high-speeddigital buses. NEW Eye scan gives a rapid comprehensive overview of signal integrity on hundreds ofchannels simultaneouslyThe Agilent 16750A, 16751A,With up to 400 MHz state speed and up to 32 MBytes of trace depth these modules help you address today’sand 16752A State/Timing Modules high-performance measurement requirements. (See page 19)The Agilent 16720APattern GeneratorHigh-Speed Bus MeasurementsMade Simple with Eye FinderTechnologyTiming Zoom TechnologyVisiTrigger TechnologyProcessor and Bus SupportDirect Links to Industry StandardDebuggers and High-LevelLanguage ToolsDirect Links to EDA ToolsWith up to 16 MVectors depth and 300 MVectors/sec operation and up to 240 channels[1] of stimulus, the16720A provides a new level of capability that makes complex device substitution a reality. Supports TTL,CMOS, 3.3V, 1.8V, LVDS, 3-state, ECL, PECL, and LVPECL.Agilent’s eye finder technology automatically adjusts the setup and hold on every channel, eliminating theneed for manual adjustment and ensuring accurate state measurements on high-speed buses.Simultaneously acquire data at up to 2 GHz timing and 400 MHz state through the same connection. TimingZoom is available across all channels, all the time. (See page 23)• Use graphical views and sentence-like structure to help you define a trace event.• Select trigger functions as individual trigger conditions or as building blocks to easily customize a triggerfor your specific task.• Get control over your microprocessor’s internal and external data.• Quickly and reliably connect to the device under test. (See page 36)• Debuggers provide visibility into software execution for systems running software written in C and C++ aswell as active microprocessor execution control (run control).• Import symbol files created by your language tool. Symbols allow you to set up trigger conditions and reviewwaveform and state listings in easily recognized terms that relate directly to the names used for signals onyour target and the functions and variables in your code.• Use captured logic analysis waveforms to generate simulation test vectors.• Easily find problems by comparing captured waveforms with simulated waveforms.[1] 240 channel system consists of five 16720A pattern generator modules with 48 channels per module. Full channel mode runs at 180 MVectors/s and 8 MVectors depth.300 MVectors/s and 16 MVectors depth are offered in half channel mode.4

System OverviewFeatures and BenefitsData Transfer, Documentation, and Remote ProgrammingDirect Link to Microsoft ® Excel via • Automatically move your data from the logic analyzer into Microsoft Excel with just a click of the mouse.Agilent IntuiLink (See page 12)• Use Microsoft Excel’s powerful functions to post-process captured trace data to get the insight you need.Transfer Data for Offline Analysis -Data ExportTransparent File System AccessDocumentation CapabilityRemote Programming withMicrosoft’s COM UsingMicrosoft Visual Basic orVisual C++• Fast binary (compressed binary) from the FileOut tool provides highest performance transfer rate.• ASCII format provides same format as listing display, including inverse-assembled data.• Access, transfer, and archive files.• Stay synchronized with your source code by mapping shared directories and file systems from yourWindows 95/98/NT-based PC directly onto the logic analyzer and vice versa.• Move data files to and from the logic analyzer for archiving or use elsewhere.• Save graphics in standard TIFF, PCX, and EPS formats.• Print screen shots and trace listings to a local or networked printer.• Save your lab notes and trace data in the same file by entering relevant information in the Comments tab ofthe display.• Perform pass/fail analysis, stimulus response tests, data acquisition for offline analysis, and systemverification and characterization tests.• Powerful-yet-efficient command set focuses on your programming tasks, resulting in a shorter learningcurve while maintaining necessary functionality.System Software FeaturesPost-Processing Analysis ToolsRapidly consolidate large amounts of data into displays that provide insight into your system’s behavior.(See page 38)Setup Assistant Quickly configure the logic analysis system for your target microprocessor. (See page 9)Tabbed Interface• Groups like tasks together so you can quickly find and complete the task you want to perform.• Spend your time solving problems, not setting up a measurement.Multi-Windowed View of • View your cross-domain measurements, time-corrected on the same screen. (See page 10)Target System Activity• Debug faster because you can view system activity at a glance.Global MarkersResizable Windows and Data ViewsTrack a symptom in one domain (e.g., timing) to its cause in another domain (e.g., analog).• Magnify your view or zoom in on a boxed area of interest.• Resize waveforms and data or quickly change colors to highlight areas of interest.Web-Enabled System • Directly access the instrument’s web page from your web browser. (See page 11)• Remotely check the instrument’s measurement status without disturbing the acquisition.• Remotely access, monitor and control your logic analysis system.Network SecurityNEW Time Correlation withInfiniium 54800 Series Oscilloscopes• Protect your networked assets and comply with your company’s security requirements with individual userlogins that provide system integrity.• Make time-correlated measurements using an Agilent 16700 Series logic analyzer and anAgilent Infiniium 54800 Series oscilloscope.• View Infiniium oscilloscope waveforms in the 16700 logic analyzer’s waveform display.• Use the 16700 logic analyzer’s global markers to measure time between any domain in the 16700 and voltagewaveforms acquired by the Infiniium oscilloscope.5

System OverviewSelecting the Right SystemSelecting a system for your applicationSelect a mainframe (page 7)Choose a system based on your needs:• Self-contained unit or a unit withexternal mouse, keyboard, and monitor• Expander frame for large channel countrequirementsDetermine your probing requirements (page 13)• Are you analyzing a microprocessor?• Do you need to probe a specific package type?Select the measurement modules to meet yourapplication needs• State/Timing Logic Analyzers (page 17)• Oscilloscopes (page 29)• Pattern Generation (page 32)• Emulation (page 36)Add post-processing tool sets for analysis andinsight (page 38)• Source correlation• Data communications• System performance analysis• Serial analysis• Tool development kitSupport, services, and assistance (page 123)• Training classes• Consulting• On-line support• Warranty extension6

MainframesDisplay12.1" LCD display with touch screen onthe 16702B makes it easy to view a largenumber of waveforms or states.Select a modifiable variable by touchingit, then turn the knob to quickly stepthrough values for the variable.Dedicated hot keys give instant access tothe most frequently used menus, displays,and on-line help.Dedicated knobs for horizontal and verticalscaling and scrolling. Adjust the display toget just the information you need to solveyour problem."Touch Off" button disables the touchscreen and allows you to point out anomalies to a colleague without alteringthe display settings.Dedicated knobs for global markers helptrack down tough problems. A symptomseen in one domain (e.g., timing) can betied to its cause in another domain(e.g., analog).Figure 2.1. The Agilent 16702B quickly tracks down problems in your design while saving precious bench space.7

MainframesBack PanelFive slots formeasurementmodulesConnection for optional monitor.(Up to 1600x1200 videoresolution with option 003)Parallel printer port10/100BaseT LAN - autosensingSCSI-II connection for anexternal 18 GByte data drive orexternal removable hard driveExpander frame connection provides anadditional five slots for measurementmodules.Built-in 40x CD-ROM drive makes it easyto install or update system software,processor support, or tool sets.Figure 2.2. The mainframe and expander frame provide advanced capabilities for debugging complex target systems.Option slot for an emulation module orfor a multiframe module. Multiframeoption allows up to eight mainframesand expanders to be combined so thatyou can see all the buses in a complextarget system.8

MainframesSystem ScreensFigure 2.3. Icons in the power-up screen give youquick access to common tasks.System Adminallows you to quicklyset up the instrumenton your network,configureprint servers, set upuser accounts forsecurity or installsoftware updates.Setup Assistantis a guided menusystem that helpsyou configure thelogic analysis systemfor your targetmicroprocessor orbus. Online informationguides youthrough the setup.(See figure 2.4)Demo Centerprovides simpledemos of the mostcommonly usedfeatures.Figure 2.4. Setup Assistant gets you up andrunning quickly.9

MainframesSystem ScreensSee the Big Picture of YourPrototype System's BehaviorA large external display (option 001)with multiple, resizable windowsallows you to see at a glance more ofyour target system's operation. Abuilt-in, flat-panel display in the16702B fits in environments withlimited space. Color lets you highlightcritical information so you can findit quickly.Use one system to examine targetoperation from different perspectives.Multiple time-correlated viewsof data let you confirm both signalintegrity and software executionflow. These views are invaluable insolving cross-domain problems.Figure 2.5. You can quickly isolate the root cause of system problems by examining target operation across a wideanalysis domain, from signals to source code.10

MainframesSystem ScreensExpanding Possibilities withNetwork ConnectivityWeb-enabled instrumentation givesyou the freedom to access thesystem—anywhere, anytime. Haveyou ever needed to check on ameasurement's status while you werein a remote location? Now you can.With a Web Enabled LogicAnalysis System You Can......install Agilent IntuiLink to seamlesslytransfer data from the system to a PC...access Agilent's Web site for the latestonline manuals and technical information...access the logic analysissystem's Web page fromyour browser by using theinstrument's hostname asa URL...access the system’s userinterface directly from withinyour browser, giving youfull control of all analysisfunctions...remotely check currentmeasurement status to findout if the system hastriggered...quickly check instrumentstatus to determine if thesystem is available for useFigure 2.6. Your logic analyzer is its own web site. From the Home Page, you can perform multiple remote functions.11

MainframesIntuiLinkAgilent IntuiLink Moves YourData Automatically intoMicrosoft ® Excel forAdvanced Offline AnalysisIntuiLink is shipped with each logicanalysis system and can be downloadedto your PC from the system’sown web page. Use the AgilentIntuiLink tool bar to connect to alogic analysis system. Select fromthe available labels and specifythe destination cell location inMicrosoft Excel.Use Microsoft Excel's powerfulfunctions to post-process capturedtrace data for the insight you need.Import data from a currentacquisition or data previously savedto a file via the File Out tool.Figure 2.7. Transfer data into Microsoft Excel with just a click of the mouse.ProgrammingIntuiLink also includes an Active-Xautomation server to provideprogrammatic control of the logicanalysis system from an externalenvironment, such as LabVIEW or theMicrosoft VisualStudio environmentof Visual Basic and Visual C++ tools.The instrument's RemoteProgramming Interface (or RPI) alsoallows you to write Perl or otherscripts to control the logic analyzer.Use the sample programs providedto assist you in creating your owncustom programs.12

Probing SolutionsCriteria for SelectionWhy is Probing Important?Your debugging tools perform threeimportant tasks: probing your targetsystem, acquiring data, and analyzingdata. Data acquisition and analysistools are only as effective as thephysical interface to your targetsystem. Use the following criteria tosee how your probing measures up.How to Determine YourRequirementsTo determine what probing methodis best to use you need to take thefollowing into consideration:• The number of signals to beprobed• The ability to design probingconnectors on the target PC boarditself• Mechanical probing clearancerequirements• Signal loading effects• Ease of attachment• Package type to be probedDIP Dual In-line PackagePGA Pin Grid ArrayBGA Ball Grid ArrayPLCC Plastic Leaded ChipCarrierPQFP Plastic Quad Flat PackTQFP Thin Quad Flat PackSOPTSOPSmall Outline PackageThin Small OutlinePackage• Package Pin Pitch (distancebetween pin centers)Figure 3.1. A rugged connection lets you focus on debugging your target, not your probe.Immunity to NoiseImpedanceRuggednessConnectivityEMF noise is everywhere and can corrupt your data. Activeattenuator probing can be particularly susceptible to noise effects.Agilent Technologies designs probing solutions with high immunity totransient noise.High input impedance will minimize the effect of probing on yourcircuit. Although many probes are acceptable for lower frequencies,capacitive loading dominates at higher frequencies.A flimsy probe will give you unintended open circuits. AgilentTechnologies' probes are mechanically designed to relieve strain andensure a rugged and reliable connection.A multitude of device packages exist in the digital electronics industry.Check our large selection of probing solutions designed for specificchip packages or buses. As an alternative, we offer reliabletermination adapters that work with standard on-target connectors.13

Probing SolutionsTechnologiesChoose the Optimum ProbingStrategy for Your ApplicationConnecting to individual testpoints with flying leadsNEW Figure 3.3. The E5382A single-ended flying leadprobe set provides connections for 17 channels ofthe 16760A logic analyzer.Figure 3.4. Surface mount IC clip.5090-4356 (20 clips).Figure 3.2.Figure 3.5. 0.5 mm IC clip.10467-68701 (4 clips).AdvantagesMost flexible method.Flying-lead probes are included with logicanalyzer module (except 16760A).LimitationsCan be time-consuming to connect a largenumber of channels. Least space-efficientmethod.Connecting to all the pins of aquad flat pack (QFP) packageFigure 3.6. Wedge adapters connect to multiplepins of 0.5 mm or 0.65 mm QFP ICs. Refer to“Probing Solutions for Agilent TechnologiesLogic Analysis Systems,” publication number5968-4632E, for specific part numbers.Figure 3.7.AdvantagesRapid access to all pins of fine-pitchQFP package.Very reliable connections.14LimitationsRequires minimal keepout area.Refer to “Probing Solutions forAgilent Technologies Logic AnalysisSystems,” publication number5968-4632E, for specific solutions.

Probing SolutionsTechnologiesDesigning connectors intothe target systemFigure 3.8.AdvantagesVery reliable connections.Saves time in making multiple connections.LimitationsRequires advance planning in the design stage.Requires some dedicated board space.Moderate incremental cost.High-density probing solutionsModel Description Requires kit of 5 connectors Usable withnumber and 5 shrouds logic analyzersE5385A 100-pin probe with built-in isolation networks for the logic analyzer 16760-68701 All except 16517A,16518A,16760AE5346A 34-channel, 38-pin probe with built-in E5346-68701 All except 16517A,isolation networks for the logic analyzer.16518A, 16760AE5351A 34-channel 38-pin adapter cable, requires logic analyzer E5346-68701 All except 16517A,isolation networks on the target.16518A, 16760AE5339A 34-channel 38-pin low-voltage probe with E5346-68701 All except 16517A,built-in isolation networks for the logic analyzer. Designed for signals16518A, 16760Awith peak-to-peak amplitude as small as 250 mV.E5378A 34-channel 100-pin single-ended probe for 16760A 16760-68701 16760A onlyE5379A 17-channel 100-pin differential probe for 16760A 16760-68701 16760A onlyE5380A 34-channel 38-pin single-ended probe for 16760A E5346-68701 16760A onlyModerate-density probing solutionsFigure 3.9. 01650-63203 termination adapter.The Agilent 01650-63203 isolationadapter contains the terminationnetworks for the logic analyzer. The01650-63203 connects to a 3M 20-pinconnector on the target PC board.Refer to "Probing Solutions forAgilent Technologies Logic AnalysisSystems," publication number5968-4632E, for design guidelinesand part numbers for matingconnectors.You may also add the isolationnetworks to the target PC board andconnect the logic analyzer cabledirectly to a 40-pin 3M connector onthe PC board. Refer to "ProbingSolutions for Agilent TechnologiesLogic Analysis Systems," publicationnumber 5968-4632E, for designguidelines in addition to part numbersfor mating connectors andisolation networks.15

Probing SolutionsTechnologiesUsing a processor- or bus-specificanalysis probeFigure 3.10.AdvantagesEasiest and fastest connection to supportedprocessors and buses.LimitationsModerate to significant incremental cost.Only useable for the specific processor or bus.May require moderate clearance aroundprocessor or bus.Refer to “Processor and Bus Supportfor Agilent Technologies LogicAnalyzers,” publication number5966-4365E, for specific solutions.16

Data Acquisition and StimulusState/Timing ModulesSelecting the Correct Modulesto Meet Your NeedsSelecting the proper logic analyzermodules for your needs requires aseries of choices concerningperformance, cost, and the amount ofdata you will be able to capture. Thefollowing table explains these factorsin greater detail.Considerations for Choosing ModulesMicroprocessor/Bus SupportState SpeedHeadroomSetup/HoldTiming ResolutionTransitional TimingWill you be using an analysis probe for a particular processor or bus? If so, a good starting point is the document Processorand Bus Support for Agilent Technologies Logic Analyzers, publication number 5966-4365E, available on the worldwide webat www.agilent.com/find/logicanalyzer. This document provides the number of channels and state speed required for anyparticular analysis probe. It also indicates which analysis modules are supported and how many are required.• State analysis uses a clock or strobe signal from your system under test to determine when to sample. Because stateanalysis samples are synchronous with the system under test, they provide a view of how your system is executing. You canuse state analysis to capture bus cycles from a microprocessor or I/0 bus and convert the data into processor mnemonicsor bus transactions using an Agilent Technologies inverse assembler.• Select a state acquisition system that provides the speed and headroom you need without breaking your budget. Rememberthat a microprocessor will have an internal core frequency that is normally 2X-5X the speed of the external bus.You may realize a better return on your investment if you consider possible future needs when purchasing analysis modules.The things to consider are primarily state speed and memory depth.• Logic analyzers require time for the data at the inputs to become valid (setup time), and time to capture the data (hold time).A lengthy setup and hold can make the difference between capturing valid data or data in transition.• Your device under test will ensure that data is valid on the bus for a defined length of time. This is known as the data validwindow. Your target's data valid window must be large enough to meet the setup/hold specifications of the logic analyzer.The data valid window of most devices is generally less than half of the clock period. Don't be fooled by "typical" setup andhold specifications for logic analyzers.• As bus speeds increase, the time window during which data is stable decreases. Jitter, skew, and pattern-dependent ISIadd more uncertainty and consume a greater portion of the data-valid window at high speeds. A logic analyzer withadjustable setup/hold with fine position resolution provides unparalleled measurement accuracy at high frequencies.Timing analysis uses the logic analyzer's internal clock to determine when to sample. Since timing analysis samplesasynchronously to the system under test, you should consider what accuracy you will need to verify your system.Accuracy is made up of two elements: sample speed and channel-to-channel skew. Remember to evaluate both of theseelements and be careful of logic analyzers that have a fast sample speed with a large channel-to-channel skew.If your system has bursts of activity followed by times with little activity, you can use transitional timing to capture a longertrace. In transitional timing, the analyzer samples data at regular intervals, but only stores the data when there is a transitionon one of the signals.17

Data Acquisition and StimulusState/Timing ModulesConsiderations for Choosing Modules (continued)Channel CountMemory DepthTriggeringOtherMeasurementsDetermine the number of signals you want to analyze on your system under test. You will need this number of channels inyour logic analyzer. Even if you have enough channels to view all the signals in your system today, you should consider logicanalysis systems that allow you to add more channels for your future application needs.• Complex architectures and bus protocols make your debugging job increasingly challenging. Split transactions, multipleoutstanding transactions, pipelining, out-of-order execution, and deep FIFOs, all mean that the flow of data related to aproblem can be distributed over thousands or millions of bus cycles.• The keys to useful insight are the combination of deep memory with responsive display refresh, search, rescaling, andscrolling to help you find information and answers quickly. Hardware-assisted memory management in the Agilent16740A, 16741A, 16742A, 16750A, 16751A, 16752A, and 16760A state and timing analysis modules makes quick work ofrefreshing the display, rescaling, scrolling, and searching. It takes only a few seconds to refresh, rescale, or scroll a 32Msample record. Agilent Technologies offers a range of state and timing analyzer modules with memory depths up to 128Msamples, at prices to meet your budget.• The logic analyzer memory system is similar to a circular buffer. When the acquisition is started, the analyzer continuouslygathers data samples and stores them in memory. When memory becomes full, it simply wraps around and stores each newsample in the place of the sample that has been in memory the longest. This process will continue until the logic analyzerfinds the trigger point. The logic analyzer trigger stops the acquisition at the point you specify and provides a view into thesystem under test. The primary responsibility of the trigger is to stop the acquisition, but it can also be used to control theselective storage of data. Consider a logic analyzer with the trigger resources you need to quickly set up yourmeasurements.• After memory depth, triggering is the most important aspect of a logic analyzer to consider. On the one hand, powerfultriggering resources and algorithms will allow you to focus on potential problem sources without using up valuable memory.On the other hand, to be useful, the trigger must be easy to set up.In addition to the measurements made with an analysis probe, consider whether you need to monitor other signals. Be sure toallow enough channels to make those measurements. For state measurements, the state speed of the analyzer must be at leastas high as the clock speed of your circuit. You may want to test the margin in your circuit by operating it at higher than thenominal clock speed to determine if the analyzer has sufficient clock speed. For timing measurements, the timing analyzer rateshould be from 2-10X the clock speed of your target.18

Data Acquisition and StimulusState/Timing ModulesVisiTriggerYour most commonly used triggers arejust a mouse click away with the built-intrigger functions. VisiTrigger’s graphicalrepresentation shows you how thetrigger condition will be defined. You canuse trigger functions as building blocksto easily customize a trigger for yourspecific task.Sequence levels allow you to develop asequence of analyzer instructions tospecify a trigger point or to qualify dataand store only the information thatinterests you. Each step in the sequencecontains an "IF/THEN/ELSE" structurethat can evaluate up to four logicevents. Each event can specify acombination of actions such as: storesample, increment counters, resettimers, trigger, or go to another stepin the sequence level.Ranges provide a way to monitorprogram and data accesses within aspecified area in memory.Global counters can count events suchas the number of times a functionexecutes or accesses an I/O port.Timers can be set up to evaluate whenone event happens too late or too soonwith respect to another event.In timing mode, edge terms let youtrigger on a rising edge, falling edge,either edge, or a glitch.Patterns and their logical combinationslet you identify which states to store,when to branch and when to trigger.View current information on the state ofthe timers, counters, flags, and the triggersequence level.Flags can be set, cleared and evaluated byany 16715A/16A/17A/40A/41A/42A/50A/51A/52A/60A module in the frame. Thisallows you to set up a trigger that is dependenton activity from more than one bus in thesystem.Save and recall up to ten of yourcustom trigger setups without loadinga new configuration file.Values can be easily entered directly intothe trigger description.Figure 4.2. Set up your trigger in terms of the measurements you want to make.22

Data Acquisition and StimulusState/Timing Modules2 GHz Timing Zoom Provides High-Speed Timing Analysis Across AllChannels, All the TimeWhen you're pushing the speedenvelope, you may run into elusivehardware problems. Capturingglitches and verifying that yourdesign meets critical setup/holdtimes can be difficult without theproper tools. With Timing Zoom youhave access to the industry's mostpowerful tool for high-speeddigital debug.Features and ApplicationsTiming Zoom• Simultaneously acquire up to 16K of data at 2 GHz timing and(available in the 16716A, 400 MHz state across all channels, all the time, through the same16717A, 16740A, 16741A, connection16742A, 16750A, 16751A • Vary the Timing Zoom sample rate from 250 MHz to 2 GHzand 16752A state/timing • Vary the placement of Timing Zoom data around the trigger pointmodules)• Efficiently characterize hardware with 500 ps resolutionNow it’s easy to capture simultaneous2 GHz timing and high-speed stateinformation through a single connection.Use the globalmarkers totime-correlateevents acrossmultiple displays.Timing Zoom labels are automaticallycreated and marked with an _TZ extension.Figure 4.3. Verifying critical edge timing in your system is easy with Agilent Technologies' 2 GHz Timing Zoom technology.23

Data Acquisition and StimulusState/Timing ModulesProbing solutions to match themeasurement capabilitiesThree probing options are availablefor the Agilent 16760A. Each probecan be ordered by its individualmodel number or as an option to the16760A. The following table indicatesboth the model number and theoption number.Probes are not supplied as part of thestandard 16760A. Probes must beordered separately, either as optionsto the 16760A or individually by theirrespective model numbers.Agilent Model Number 16760A Option Number Description NotesE5378A 010 100-pin single-ended probe Requires a kit of mating connectors and shrouds(see the next table) to connect to target system.E5379A 011 100-pin differential probe Two E5379A (or two option 011 on the 16760A) arerequired to support all 34 channels on a 16760A.Requires a kit of mating connectors and shrouds(see the next table) to connect to target system.E5380A 012 38-pin single-ended probe, compatible Maximum state analysis speed is 600 Mb/s.with target systems designed for the Minimum input amplitude is 300 mV p-p.Agilent E5346A Mictor adapter cable Requires a kit of mating connectors and shrouds(see the next table) to connect to target system.E5382A 013 17-channel, single-ended flying lead Two E5382A are required to support all the channelsprobe set for the 16760A of a 16760A.Connector and shroud kits for probes for the 16760A logic analyzerFor probe model number For PC board thickness Probing connector kit part number(each contains 5 mating connectors and 5 support shrouds)E5378A Up to 1.57 mm (0.062") 16760-68702Up to 3.05 mm (0.120") 16760-68703E5379A Up to 1.57 mm (0.062") 16760-68702Up to 3.05 mm (0.120") 16760-68703E5380A Up to 1.57 mm (0.062") E5346-68701Up to 3.18 mm (0.125") E5346-6870029

Data Acquisition and StimulusOscilloscope ModulesWhen integrated into the 16700Series logic analysis systems, theoscilloscope modules make powerfulmeasurement and analysis moreaccessible, so you can find theanswers to tough debugging problemsin less time. Oscilloscope controls areeasy to find and use.Multiple Views of Target BehaviorIsolate Problems QuickerFrequently a problem is detected inone measurement domain, while theclues to the cause of the problem arefound in another. That’s why the abilityto view your prototype's behaviorfrom all angles simultaneously—fromsoftware execution to analog signals—is essential for quickly gaining insightinto problems.For example, using a state analyzeryou may observe a failed bus cycle. Atiming problem caused by a reflectionon an incorrectly terminated linemay be causing the bus cycle to fail.By triggering an oscilloscope from thestate analyzer, you can quickly identifythe cause. The ability to cross-triggerand time-correlate state, timing,and analog measurements can helpyou in solving these tough problems.Scope controlsand waveformdisplay are integratedinto asingle window,making interactiveadjustmenteasy.Trigger iconindicates triggerlevel, making iteasy for you toadjust triggerlevel.Time and voltagemarkers allow youto measure signaldetails precisely.Figure 4.5. All primary oscilloscope control settings, including scale factors and trigger settings, are visiblesimultaneously.Ground iconalways showsyou where groundis relativeto signal.30

Data Acquisition and StimulusOscilloscope ModulesAutomatic Measurements QuicklyCharacterize SignalsThe Agilent Technologies 16534Aoscilloscope modules quickly characterizesignals with automatic measurementsof rise time, voltage, pulsewidth, and frequency.Markers Easily Set Up Timing andVoltage Margin MeasurementsFour independent voltage markersand two local time markers are availableto quickly set up measurementsof voltage and timing margins.The global time markers of the 16700Series logic analysis systems let youcorrelate state, timing, and oscilloscopemeasurements to track problemsacross multiple measurementdomains.Automatic measurementssave time in characterizingsignal parameters.Figure 4.6. Automatic measurements and markers let you make faster analysis.31

Data Acquisition and StimulusOscilloscope ModulesMore Channels When You Need ThemYou can combine up to four 16534Aoscilloscope modules to provide upto eight channels on a single timebase. When you operate in thismode, you can use the master modulefor triggering.Calibrator output usedfor operational accuracycalibrationExternal trigger input and output areused to connect up to four oscilloscopemodules, providing up to eight channelson a single time base.Probe power output provides powerfor 1145A dual active probe or two1141A active probesChannel 1 inputChannel 2 inputCHAN1INECL EXTCHAN2! CHAN 1 & 216534A1MW = 7pF250V MAX ORTRIG50W 5Vrms MAXAC/DC CAL!!OUT! PROBE POWERSN US3502192416534A MADE IN THE USA2 GSa / sOSCILLOSCOPEFigure 4.7. Connector panel of the 16534A oscilloscope module.32

Data Acquisition and StimulusPattern Generation ModulesDigital Stimulus and Response in aSingle InstrumentConfigure the logic analysis system toprovide both stimulus and responsein a single instrument. For example,the pattern generator can simulate acircuit initialization sequence andthen signal the state or timing analyzerto begin measurements. Use thecompare mode on the state analyzerto determine if the circuit or subsystemis functioning as expected. Anoscilloscope module can help locatethe source of timing problems ortroubleshoot signal problems due tonoise, ringing, overshoot, crosstalk,or simultaneous switching.Parallel Testing of SubsystemsReduces Time to MarketBy testing system subcomponentsbefore they are complete, you can fixproblems earlier in the developmentprocess. Use the Agilent 16720A as asubstitute for missing boards,integrated circuits (ICs), or busesinstead of waiting for the missingpieces. Software engineers can createinfrequently encountered testconditions and verify that their codeworks—before complete hardware isavailable. Hardware engineers cangenerate the patterns necessary toput their circuit in the desired state,operate the circuit at full speed orstep the circuit through a seriesof states.Key CharacteristicsAgilent Model 16720AMaximum clock (full/half channel)Number of data channels (full/half channel)Memory depth (full/half channels)Maximum vector width(5 module system, full/half channel)Logic levels supportedMaximum binary vector set sizeEditable ASCII vector set size180/300 MHz48/24 Channels8/16 MVectors240/120 BitsTTL, 3-state TTL, 3.3V, 1.8V, 3-state CMOS, ECL,5V PECL, 3.3V LVPECL, LVDS16 MVectors (24 channels)1 MVectors33

Data Acquisition and StimulusPattern Generation ModulesVectors Up To 240 Bits WideVectors are defined as a "row" oflabeled data values, with each datavalue from one to 32 bits wide. Eachvector is output on the rising edge ofthe clock.Up to five, 48-channel 16720A modulescan be interconnected within a16700 Series mainframe or expansionframe. This configuration supportsvectors of any width up to 240 bitswith excellent channel-to-channelskew characteristics (see specificdata pod characteristics in PatternGeneration Modules Specificationsstarting on page 105). The modulesoperate as one time-base with onemaster clock pod. Multiple modulesalso can be configured to operateindependently with individual clockscontrolling each module.Depth Up to 16 MVectorsWith the 16720A pattern generator,you can load and run up to16 MVectors of stimulus. Depth onthis scale is most useful when coupledwith powerful stimulusgenerated by electronic designautomation tools, such asSynaptiCAD's WaveFormer andVeriLogger. These tools createstimulus using a combination ofgraphically drawn signals, timingparameters that constrain edges,clock signals, and temporal andBoolean equations for describingcomplex signal behavior. Thestimulus also can be created fromdesign simulation waveforms. To takeadvantage of the full depth of the16720A pattern generator, data mustbe loaded into the module in thePattern Generator Binary (.PGB) format.The SynaptiCAD tools allow youto convert .VCD files into .PGB filesdirectly, offering you an integratedsolution that saves you time.Synchronized Clock OutputYou can output data synchronized toeither an internal or external clock.The external clock is input via a clockpod, and has no minimum frequency(other than a 2 ns minimum hightime).The internal clock is selectablebetween 1 MHz and 300 MHz in1 MHz steps. A Clock Out signal isavailable from the clock pod and canbe used as an edge strobe with avariable delay of up to 8 ns.Initialize (INIT) Block forRepetitive RunsWhen running repetitively, the vectorsin the initialize (init) sequenceare output only once, while the mainsequence is output as a continuallyrepeating sequence. This "init"sequence is very useful when thecircuit or subsystem needs to beinitialized. The repetitive run capabilityis especially helpful when operatingthe stimulus module independentof the other modules in the logicanalysis system."Signal IMB" Coordinates SystemModule ActivityA "Signal IMB" (intermodule bus)instruction acts as a trigger armingevent for other logic analysis modulesto begin measurements. IMB setupand trigger setup of the other logicanalysis modules determine theaction initiated by "Signal IMB"."Wait" for Input PatternThe clock pod also accepts a 3-bitinput pattern. These inputs are levelsensedso that any number of "Wait"instructions can be inserted into astimulus program. Up to four patternconditions can be defined from theOR-ing of the eight possible 3-bitinput patterns. A "Wait" also can bedefined to wait for an intermodulebus event. This intermodule busevent signal can come from any othermodule in the logic analysis system.34

Data Acquisition and StimulusPattern Generation ModulesFigure 4.8. Stimulus vectors are defined in theSequence menu tab. In this example, vector outputhalts until the WAIT UNTIL condition is satisfied.Figure 4.9. To fill the 16720A pattern generator's 8 MVectordeep memory (16 MVector in half channel mode) with data,the stimulus must be in 'pattern generator binary' format.Stimulus files in .PGB format can be loaded directly fromthe user interface.35

Data Acquisition and StimulusPattern Generation Modules"User Macro" and "Loop" SimplifyCreation of Stimulus ProgramsUser macros permit you to define apattern sequence once, then insertthe macro by name wherever it isneeded. Passing parameters to themacro will allow you to create a moregeneric macro. For each call to themacro you can specify unique valuesfor the parameters. Each macro canhave up to 10 parameters. Up to 100different macros can be defined foruse in a single stimulus program.Loops enable you to repeat a definedblock of vectors for a specifiednumber of times. The repeat countercan be any value from 1 to 20,000.Loops and macros can be nested,except that a macro can not be nestedwithin another macro. When nested,each invocation of a loop or a macrois counted towards the 1,000 invocationlimit. At compile time, loops andmacros are expanded in memory to alinear sequence.Convenient Data Entry and EditingFeatureYou can conveniently enter patternsin hex, octal, binary, decimal, andtwo's complement bases. The dataassociated with an individual labelcan be viewed with multiple radixesto simplify data entry. Delete, Insert,Copy, and Merge commands areprovided for easy editing. Fast andconvenient Pattern Fills give theprogrammer useful test patterns witha few key strokes. Fixed, Count,Rotate, Toggle, and Random areavailable to quickly create a testpattern, such as "walking ones".Pattern parameters, such as StepSize and Repeat Frequency, can bespecified in the pattern setup.ASCII Input File Format: Your DesignTool ConnectionThe 16720A supports an ASCII fileformat to facilitate connectivity toother tools in your design environment.Because the ASCII format doesnot support the instructions listedearlier, they cannot be edited into theASCII file. User macros and loopsalso are not supported, so the vectorsneed to be fully expanded in theASCII file. Many design tools willgenerate ASCII files and output thevectors in this linear sequence. Datamust be in Hex format, and each labelmust represent a set of contiguousoutput channels. Data in this ASCIIformat is limited to 1 MVectors inthe 16720A.ConfigurationThe 16720A pattern generatorsrequire a single slot in a logicanalysis system frame. The patterngenerator operates with the clockpods, data pods, and lead setsdescribed later in this section. Atleast one clock pod and one data podmust be selected to configure a functionalsystem. Users can select from avariety of pods to provide the signalsource needed for their logic devices.The data pods, clock pods and datacables use standard connectors. Theelectrical characteristics of the datacables also are described for userswith specialized applications whowant to avoid the use of a data pod.The 16720A can be configured insystems with up to five cards for atotal of 240 channels of stimulus.Direct Connection to Your TargetSystemThe pattern generator pods can bedirectly connected to a standardconnector on your target system. Usea 3M brand #2520 Series, or similarconnector. The 16720A clock or datapods will plug right in. Short, flatcable jumpers can be used if theclearance around the connector islimited. Use a 3M #3365/20, or equivalent,ribbon cable; a 3M #4620Series, or equivalent, connector onthe 16720A pod end of the cable; anda 3M #3421 Series, or equivalent,connector at your target system endof the cable.Probing AccessoriesThe probe tips of the Agilent 10474A,10347A, and 10498A lead sets plugdirectly into any 0.1 inch grid with0.026 inch to 0.033 inch diameterround pins or 0.025 inch square pins.These probe tips work with theAgilent 5090-4356 surface mountgrabbers and with the Agilent5959-0288 through-hole grabbers.Other compatible probing accessoriesare listed in ordering information onpage 121.36

Data Acquisition and StimulusEmulation ModulesSpeed Problem Solving WithOff-the-Shelf Solutions for ManyCommon MicroprocessorsTo help you design and debug yourmicroprocessor-based target systems,Agilent offers different microprocessorspecific products that let you getcontrol and visibility over yourmicroprocessor’s internal andexternal data.An analysis probe allows you toquickly connect an Agilent logicanalyzer to your target system. Theanalysis probe provides non-intrusivecapture and disassembly of microprocessorand bus activityAnalysis probes are available for over200 microprocessors and microcontrollers.Bus probes allow probing ofpopular bus architectures such asPCI, AGP, USB, VXI, SCSI, and manyothers.Figure 4.10. Agilent analysis probes make it easy to connect a logic analyzer to your target system.Flexible physical probing schemesgive quick and reliable connections toalmost any device on your prototype.On-Chip Emulation Tools Make FixingBugs EasierFor specific microprocessor familiesthat feature on-chip emulation, youcan add a processor emulationmodule to your system to connectthe on-board debugging resourcesof the microprocessor to the logicanalysis system.The microprocessor’s BDM or JTAGtechnology provides control overprocessor operation even if there isno software monitor on the targetsystem. This feature is particularlyhelpful during the development ofyour target system’s boot code.37

Data Acquisition and StimulusEmulation ModulesEmulation Control InterfaceThe emulation control interface isaccessed from the power up screen ofthe Agilent 16700 Series system. Theinterface is included with the AgilentE5901A/B emulation modules.Designed for hardware engineers,this graphical user interface providesthe following features:• Control over processor execution:run/break/reset/step.• Register display/modification.• Memory display/modification invarious formats including disassemblyfor code visualization.Memory modification or memoryblock fill can be done to checkprocessor memory access or toreinitialize memory areas.• Multiple breakpoint configuration:hardware, software, and processorinternal breakpoint registers.• Code download to the target.• Command scripts to reproducetest sequences.• The ability to trigger a measurementmodule on a processor breakor to receive a trigger from thelogic analysis system’s measurementmodules.Integrated Debugger SupportWhen the hardware turn-on phase iscompleted, the same Agilent emulationmodule can be connected tohigh-level debuggers for C or C++software development.You can achieve the functionality ofa full-featured emulator by using athird-party debugger to drive theinstalled Agilent emulation module.This gives you complete microprocessorexecution control (run control).Figure 4.11. Emulation control interface.38

Post-Processing and Analysis Tool SetsSoftware Tool SetsOnce the data is acquired, you canrely on the post-processing tools torapidly consolidate data into displaysthat provide insight into your system'sbehavior. The tool setsdescribed in the following pages areoptional, post-processing softwarepackages for the 16700 Series logicanalysis systems.Selecting the Right Tool SetTake a look at the tool set descriptionsbelow to see if they meet yourneeds. If you don't immediately seewhat you need there is also theoption of writing your own analysisapplication using the tool developmentkit. Best of all, you can try outany one of these tool sets with noobligation to buy.Application Product Name Model Number Detailed InformationDebug your real-time code at the source level Source Correlation B4620B Page 40Correlate a logic analyzer trace with the high-level sourceTool Setcode that produced it. Set up the logic analyzer trace bysimply pointing and clicking on a line of source code.Debug your parallel data communication buses Data Communications B4640B Page 44Display logic analyzer trace information at a protocol level. Tool SetPowerful trigger macros allow triggering on standard orcustom protocol fields. Data bus width is limited only bythe number of available channels.Optimize your target system's performance System Performance B4600B Page 53Profile your target system's performance to identify system Analysis Tool Setbottlenecks and to identify areas needing optimization.Solve your serial communication problems Serial Analysis B4601B Page 60Convert serial bit streams to parallel format for easy viewing Tool Setand analysis. Supports serial data with or without an externalclock reference and protocols that use bit stuffing to maintainclock synchronization. Works at speeds up to 1 GHz.Customize your trace for greater insight Tool Development B4605B Page 66Create custom tools using the C programming language.KitCustom tools can analyze captured data and present it ina form that makes sense to you. Analysis systems do notrequire the tool development kit to run generated tools.39

Post-Processing and Analysis Tool SetsSoftware Tool SetsFree Tool Set EvaluationTo see which tool sets best fit yourneeds, Agilent Technologies offers afree 21-day trial period that lets youevaluate any tool set as your workschedule permits. Once you receiveyour tool, you obtain a password thattemporarily enables the tool.Figure 5.1. For a free, one-time, 21-day trial of any tool set, simply type “demo” in the password field for the productyou want to evaluate.40

Post-Processing and Analysis Tool SetsSource CorrelationDebug Your Source CodeThe Agilent B4620B source correlationtool set correlates a microprocessorexecution trace window with acorresponding high-level source codewindow. The source correlation toolset enhances your software developmentenvironment by providing multipleviews of code execution andvariable content under severe realtimeconstraints.Using the B4620B you can obtainanswers to many of your questionsconcerning software code execution,data tracking, and software-hardwareintegration.Obtain Answers to the FollowingQuestions:Software Code Execution• What happened just before thetarget system crashed?• What source code was executed ata specific point in time?• What is the exact time betweentwo user-defined system events?• What is the execution historyleading up to or occurring after anarea of interest?Data Tracking• What is the exact history of avariable's value over time?• Which routine(s) corrupted thedata?Software-Hardware Integration• What is the root cause of a systemfailure—hardware or software?• Are timing anomalies found by thehardware engineer the cause ofsoftware problems?• Is the software engineer workingon the same problem as the hardwareengineer?• What portion of the source codecorrelates to the problem thehardware engineer reported?Product DescriptionThe tool set's main advantage is itsability to allow you to observe softwareexecution without halting thesystem or adding instructions to thecode. The tool set uses informationprovided in your compiler's object fileto build a database of source files,line numbers and symbol informationto reference to logic analyzer traces.The tool set can also be used to set upthe logic analyzer trace by simplypointing and clicking on a sourceline.Once the tool set is enabled on your16700 Series system, you can supportnew processors by changing analysisprobes and verifying object file compatibility.Multiple-processor systemsare also supported.Your Development EnvironmentSourceCompileRelocatableObject CodeAnalyzerTraceLinkAbsoluteObject CodeSymbol FileEditSource FileDownloadDebugFigure 5.2. The source correlation tool set allows you to observe software execution without halting the system oradding instructions to the code.41

Post-Processing and Analysis Tool SetsSource CorrelationWhen You Wantto Trace . . ....on a variable to see what caused datacorruption....on a function to determine where it is beingcalled from in order to understand the contextof a system error....on a line number to determine if aspecific code segment is ever executed.Simply Click . . .... to trace about a variable, function, orline number.... to halt processor execution with anintegrated emulation module when the traceevent occurs....to use text search to quickly navigatethrough hundreds of symbols. To recallprevious entries when rotating through debugtests....to specify alignment conditions forprocessors that don’t include lower addressbits on the bus. This is necessary if yourprocessor uses bursting or byte enables whenfetching instructions....to use address offsets for code that isdynamically loaded or moved from ROM toRAM during a boot-up sequence.42Figure 5.3.

Post-Processing and Analysis Tool SetsSource CorrelationOnce You Acquirethe Trace . . ....“step” through thetrace at the sourcecodelevel or theassembly level.Locate the cause of aproblem by “steppingbackward” from thepoint where you seea problem to its rootcause....quickly locate aspecific function,variable, or textstring. The systemmaintains a historyof previous textsearches for quickrecall....click the source linewhich you want totrace about on yournext acquisition....set the data type to“Symbols” to viewfile and symbolnames or ”line #s” toview file name andline number....filter out unexecutedcode fetchesfrom the inverseassembled trace toview executed codeonly, using Agilent’sadvanced inverseassembly filtering forpopular processors....scroll or step throughthe time-correlatedsource code (left) orinverse assembled tracelisting (right)Also...Figure 5.4.Analyze a function’s behavior without viewingcalls to subroutines or interrupts by using theanalyzer’s filtering capabilities to focus on aspecific part of the executed software.43

Post-Processing and Analysis Tool SetsSource CorrelationProduct CharacteristicsData SourcesAll state and timing measurementmodules supported by the 16700Series logic analysis systems (exceptthe 16517A/518A) serve as datasources for the source correlationtool set.Microprocessor SupportThe source correlation tool set supportsmany of the most popularembedded microprocessors Nonintrusiveanalysis probes for the16700 Series systems provide reliable,fast and convenient connectionsto your target system.New microprocessors are constantlybeing added to the list of supportedCPUs. For the most current informationabout supported microprocessors,please contact your AgilentTechnologies sales representative orvisit our web site: http://www.agilent.com/find/ logic analyzer.Object File Format CompatibilityThe 16700 Series logic analysis systemsquickly and reliably read yourspecific object file format. AgilentTechnologies' extensive experiencewith different file formats and symbolrepresentations ensures that yoursource code files are accurately correlatedand your system is preciselycharacterized.Source correlation and system performancemeasurements do notrequire any change in your softwaregeneration process. No modificationor recompilation of your source codeis required.You can load multiple object files.Address offsets are also supported,enabling system performance measurementsand source-code level viewsof dynamically loaded software executionor code moved from ROM toRAM during a boot-up sequence.High-level language tools that producethe following file formats aresupported:• Agilent(HP)/MRI IEEE696• ELF/DWARF*• ELF/Stabs*• TI_COFF• COFF/Stabs*• Intel OMF86• Intel OMF96• Intel OMF 286• Intel OMF 386 (which supportsIntel80486 and Pentium Language)*Supports C++ name de-manglingIf your language system does not generateoutput in one of the listed formats,a generic ASCII file format isalso supported.For the most current informationabout supported compiler file formatsand processor support, pleasecontact your Agilent Technologiessales representative.Source File AccessThe source correlation tool set mustbe able to access source files to providesource line referencing.Source files can reside in multipledirectories on the hard drive of yourworkstation, PC, or on the 16700Series mainframe's internal harddisk. You can access the files via NFSmounteddisks or CIFS mounteddisks. To display the source file, thetool set first looks for the source pathname in the object file, follows thepath to access the source file and, ifnot found, looks for the source file inalternate user-defined directories.The 16700 Series logic analysissystems automatically place thefollowing in the directory searchpath:• NFS mounted directories• Directory paths specified inloaded symbol files• Directory paths specified inloaded source filesSource Correlation Functionality• Source code and inverseassembled trace listing are timecorrelated.• User can alternate between sourceviewer and browsing of othersource files.• Trace specification can be set upfrom the source viewer or filebrowser.• For multiple-processor systems,each trace window can betime-correlated to a source viewer.44

Post-Processing and Analysis Tool SetsData CommunicationsMonitor Packet Information onParallel Data BusesThe data communications tool setshows parallel bus data at a protocollevel on the logic analyzer. Developershave the capability to find complex,system-level bus interaction problemsin applications such as a switching orrouting system.Obtain Answers to the FollowingQuestions:• What is the time differencebetween two or more data pathsand/or a microprocessor?• Did a packet make it through theswitch or router?• Why did a packet take so long togo through the switch or router?• Where did an illegal packet comefrom?• What is the latency on packetinformation?• What is corrupting packets?Product DescriptionThe Agilent Technologies B4640Bdata communications tool set addsprotocol analysis capabilities to thelogic analyzer for viewing paralleldata buses (e.g, UTOPIA or a proprietarydata bus) in a switching orrouting system. Each protocol layer isdisplayed with a different color in thelogic analyzer lister display to alloweasy viewing of the protocol data.Payload information is included afterthe header in a raw hex format.Filters are included to allow manydifferent views of the data. Protocollayers can be collapsed or expandedto create a custom view of the dataacquired in the logic analyzer. Withthe filters, you can concentrate onthe data of interest for a particularmeasurement.The powerful protocol trigger macroallows easy trigger setup by eliminatingthe need to manually configurethe trigger sequencer for complexmeasurements. All custom-definedprotocol fields or layers are supportedin the trigger macro.All packets or cells are time-stampedin the logic analyzer for time-correlationmeasurements with other systembuses, such as a microprocessor,memory interface, PCI bus, or otherUTOPIA bus. All state listing andwaveform displays in the logic analyzerare time-correlated with globalmarkers for a complete view of thesystem. With this tool, it is possibleto trigger the logic analyzer with amicroprocessor event and see what ishappening on a parallel data bus withprotocol information.By monitoring multiple time-correlateddata buses, you can monitor apacket entering one ASIC and seehow long it takes for the packet toreach another part of the system. Thepowerful trigger can also monitor apacket entering one port and triggerif the packet has not reached anotherport by a designated time.45

Post-Processing and Analysis Tool SetsData CommunicationsTheory of OperationUse a logic analyzer to probe thesystem’s parallel data buses (e.g.,UTOPIA).UTOPIA Level 2CPUCustom/UTOPIAThe analyzer needs access to:• Data signals• Qualifying signals• Start of cell or packet bit• Synchronous clock for the busThe synchronous bus clock samplesdata into the logic analyzer.Qualifiers such as "Data Valid" allowthe logic analyzer to sample only onevents of interest instead of allcycles.PHYPHYPHYPHYATMLayerATMLayerSwitchFabricATMLayerATMLayerPHYPHYPHYWith access to the "Start of Cell" or"Start of Packet" bit on the data bus,the analyzer starts looking at thebeginning of a cell or packet. With theprotocol definition set up by the user,the logic analyzer can sequence downinto the cell or packet to find thedesired protocol field to trigger on.Figure 5.5. Typical ATM Switch Design.UTOPIA Level 146

Post-Processing and Analysis Tool SetsData CommunicationsProduct CharacteristicsAdditional InformationRequiresApplications16700 Series logic analysis system withsystem software version A.01.50.00 or higherTrigger on a processor event and see whatis happening on a parallel data bus withprotocol information or vice versa.Supported Measurement Modules 16715A, 16716A, 16717A, 16718A, 16719A,16750A, 16751A, 16752AProtocols Supported • Ethernet • Example files for these protocols are provided with the• ATMproduct. These standard files can be edited to include• TCP/IP Stackany custom protocol "wrapper" layers or fields.• Custom• Custom protocols are supported by entering the protocolsetup information via the logic analyzer interface or a textfile. Custom protocol definitions are used in both thetrigger definition and packet display.Trigger MacroMaximum Parallel Bus WidthAll custom-defined protocol fields or layersare supported in the trigger macroLimited only by the number of available channelsDisplay Features • Color • Each protocol layer is displayed with a different color inthe analyzer’s lister display to allow easy viewing ofprotocol data.• Filters and preferences• Specific protocol layers and fields can be selected forviewing in the trace. Provides many different views of thedata. Allows you to concentrate on the data of interestfor a particular measurement.• Payload information• Included after the header in a raw hex format• Protocol layers• Can be collapsed or expanded to create a custom view ofthe acquired data47

Post-Processing and Analysis Tool SetsData CommunicationsEdit or create aprotocol using thelogic analyzeruser interface.Select a knownprotocol and addproprietary fields.Insert customwrapper orfield here.Insert name, numberof bits andformat for triggeranddisplay.Define any symbolsfor bothtrigger anddisplay ofpackets.Edit or create aprotocol using atext file.Start with standardprotocoldefinition and addcustom fields withtext file.Insert protocollayer name.Define protocolfields, number ofbits, and formatfor trigger anddisplay.Define any usersymbols to maketriggering and displayeasier to use.Figure 5.6.48

Post-Processing and Analysis Tool SetsData CommunicationsNew packettrigger macros.Choose from a listof buses.Trigger on simpleIP address insteadof setting up triggersequencer.Specify whataction to performonce a packet isfound.Specify protocollayer to trigger on.Use any definedprotocol fields asa trigger, such assource address,destinationaddress, etc.Physical representation of bit fields to be triggered on.This window is automatically updated when fields are edited.Figure 5.7.49

Post-Processing and Analysis Tool SetsData CommunicationsUse the bus editor feature to specifywhat protocol runs on your bus. Thisis helpful when probing more thanone bus with a single state/timingmodule.Figure 5.8.50

Post-Processing and Analysis Tool SetsData CommunicationsProtocol Filters and ViewingPreferencesFilter captured data toonly view key data formeasurement.Choose to view payloaddata with headerinformation.Select which protocollayers and fields toview in trace.Figure 5.9.51

Post-Processing and Analysis Tool SetsData CommunicationsDisplay ofprotocol levels.Protocol view ofdata acquired inlogic analyzer.Figure 5.10.Time tags for system level correlation of other databuses, memory interfaces, microprocessors, etc.52

Post-Processing and Analysis Tool SetsData CommunicationsGlobal markers measure time intervals betweenpackets on separate parallel interfaces or timingbetween the data path and a microprocessor.Collapsed viewof protocol informationusing preferences.Raw packetheaderinformation.Raw payloadinformation.Figure 5.11.53

Post-Processing and Analysis Tool SetsSystem Performance AnalysisOptimize System PerformanceYour design has to meet consistentperformance requirements over arange of operating conditions andover a specific time period. Using thesystem performance analysis tool set,you can obtain answers to many ofyour questions concerning performanceand responsiveness, softwareexecution coverage, debug and systemparameter analysis, etc.Obtain Answers to the FollowingQuestions:Performance and Responsiveness• What functions monopolize microprocessorbandwidth?• What functions are never executed?What is the relative workloadof each processor in a multipleprocessorsystem?• What is the minimum, maximum,and average execution time of afunction (including calls)?• How many interrupts does thesystem receive per consecutivetime slice?• What is the response time of thetarget system to an externalevent?Software Execution Coverage• Do test suites provide thoroughcoverage of the application?• Is this function or variableaccessed by the application?Debug and System ParameterAnalysis• Does this pointer address the rightmemory buffer?• How does the system react when itreceives too many simultaneousinterrupts?• Is the stack size adequate?• Is the cache size adequate?Analog, Timing, and BusMeasurements• What is the setup/hold time of thissignal or group of signals?• Is the distribution of voltages forthis analog signal acceptable?• Is this signal spending too muchtime in the switching region?• What bus states occur most often?• What is the bus loading?• How does the bus affect overallsystem performance?• How much time is spent in busarbitration?• What is the histogram of bustransfer times?Processor/Cache Measurements• Which microprocessor bus statesoccur most often?• Which peripherals are used mostoften?• What is the profile of load sharingin a multiple-processor system?• How does the cache size affectsystem performance?Product DescriptionThe Agilent Technologies B4600B systemperformance analysis (SPA) toolset profiles an entire target system atall levels of abstraction—from signalsto high-level source code. It clearlyidentifies the components that affectthe behavior of your system. In additionto performance analysis, it canbe used at any time to test and documentmany other characteristics,such as memory coverage andresponse time.The SPA tool set generates statisticalrepresentations of the captured data.It shows the amount and percent oftime spent in each of the targetedfunctions or data locations. Data isconveniently displayed in histogramsand bar charts, reducing the time youspend analyzing results and identifyingsystem bottlenecks.54

Post-Processing and Analysis Tool SetsSystem Performance AnalysisProduct CharacteristicsSPA ToolsState Interval Display Time Interval Display Time Overview Display State Overview DisplayGeneratesStatistical representations of the captured dataShows the amount and percent of time spent in each of the targeted functions or data locations.Provides Histogram of event Histogram of event times. Overview of occurrence Overview of bus/memoryactivity. Display shows Display shows a rates over time. activity. Display shows thethe percentage of hits distribution of the Measurements of the number of hits for eachfor each procedure, execution time of a occurrence rate of any possible bus state.function, or event specific function or of event, including(states). Events are the time between two interrupts, over time.defined as patterns or user-defined events.ranges associated withany set of data (labels,symbols).Usage Helps prioritize functions Determines a specific Views the frequency of First step of analysis orthat are candidates for routine’s execution times events over time. optimization process toduration measurements and verifies signal timing identify which events occurusing the time interval tool. specifications most frequently.Applications Cache hit and miss Measures setup and hold Isolates defects such asanalysis. Bus headroom times, the jitter between invalid pointers (filtering).analysis can be made by two edges, or the Distribution of signalexamining ratio of active variation between two voltages can tell whether ato idle status states. bus states. digital signal is spending tooExamines workload ofmuch time in the switchingeach processor in aregion. Evaluates themulti-processor systemlinearity of the output of ato determine if systemD/A converter.is balanced.Displays IncludeAbility to be viewed simultaneouslyFiltering capabilities for removing portions of a trace that are not applicable to the analysisMaximum Number of Events No theoretical limit. Number of events limited by size of the windowUp to 10,000 events tested with a standard configuration (e.g. pixels on the screen)55

Post-Processing and Analysis Tool SetsSystem Performance AnalysisProduct Characteristics (continued)SPA ToolsState Interval Display Time Interval Display Time Overview Display State Overview DisplaySupplemental Information Number of hits Minimum time Number of hits Number of hitsMaximum time Time bucket width State bucket widthAverage timeStandard deviationDisplay Modes Sort by number of hits Sort by time Autoscale zoomSort alphabetically by Sort alphabetically byevent nameevent nameAccumulate ModeNo theoretical limit to the number of acquisitions in accumulate mode.Any modification of the display will cause the display to revert back to the last data acquisition.Object File Format Object file formats are identical for SPA and the source correlation tool sets. See page 43.CompatibilityOff-Line Analysis andPost-ProcessingProcessor SupportData SourcesAll measurements can be saved using the file out tool.Data can be recalled at any time for later analysis using any SPA or other tool.Performance measurements can be exported to your host computer as histograms or as tabular formatted text files.Supports any analysis probe listed in Processor and Bus Support for Agilent Technologies Logic Analyzers(pub no. 5966-4365E)All measurement modules supported by the 16700 Series logic analysis systems serve without modification as datasources for the B4600B.The particular module determines time resolution and accuracy.Sample rate, channel count, memory depth and triggering are controlled by the user independent of the SPA tool set.56

Post-Processing and Analysis Tool SetsSystem Performance AnalysisState Overview ToolNarrow in on an area of interestusing built-in qualification and zoomfunctions.Pinpoint regions of high memory activity todetermine which routines or operations areresponsible for throughput bottlenecks.Measure memory coverage or stackusage by observing whether memorylocations are accessed. You can alsodetect which peripherals are most frequentlyused.Figure 5.12. Identify which events occur most frequently.57

Post-Processing and AnalysisSystem Performance AnalysisState Interval ToolSort and display symbols alphabetically by eventname or by the number of hits.Display just the symbols youwant to evaluate by using thesymbol-navigation utility. The utilityautomatically configures thetool for the selected function andvariable names from large symbolfiles created by complex softwareprojects.To help simplify your display,delete all functions below aselected point with a singlemouse click.Pass the mouse over a histogram bar andbucket information gives you detailedinformation for each event.Figure 5.13. Determine which functions use the most CPU cycles.58

Post-Processing and AnalysisSystem Performance AnalysisTime Interval ToolBecause time interval measurements oftendepend upon hardware-software interaction,the event definition can be a combinationof symbolics and hardware events. Dataqualification can be used to define thespecific hardware context in which theanalysis will be made.Data is displayed in histograms, whichcan be exported to your host computereither as histograms or as tabularformatted text files.Statistics such as maximum time,minimum time, standard deviation andmean help you document system behavior.Use “accumulate mode” to analyzethe behavior of your system over a longperiod of time.Figure 5.14. Determine a specific routine's execution times.59

Post-Processing and Analysis Tool SetsSystem Performance AnalysisTime Overview ToolUse “Comments” to document your trace. The“Comments” field contents are saved with theconfiguration and data.Use the markers in this window to correlateinterrupts to a state listing or timing waveform.Elusive system crashes are oftencaused by too many interrupts occurringover a short period of time. If thesoftware cannot handle all simultaneousservice requests, the system canexhibit random defects while leavingno clues as to their cause. In this situation,you need a tool that can measureand display interrupt loading.Figure 5.15. View the frequency of events over time.60

Post-Processing and Analysis Tool SetsSerial AnalysisSolve Serial Communication ProblemsYour system may use serial buses tocommunicate between ICs and totransfer data to and from peripheraldevices. Sifting through thousands ofserial bits by looking at long verticalcolumns of captured 1's and 0's canbe very tedious, time-consuming, anderror-prone.Obtain Answers to the FollowingQuestions:• Is the software sending the correctmessage?• Is the communication hardwareacting as expected?• When multiple messages areinvolved, in what order is databeing transmitted?• How does the serial bus activitycorrelate to the target systemprocessor?• What is causing the data corruptionin the target system?Product DescriptionThe Agilent Technologies B460lB serialanalysis tool set is a general-purposetool that allows easy viewingand analysis of serial data.The tool set enables you to:• Convert acquired serial bitstreams into readable parallelword formats• Time-correlate real-time serialtraces to system activity• Remove stuffed bits from the datablock• Process frame and data portionsseparately• Process serial data from a signalwith or without an external clockreference• Capture and analyze high-speed(1 GHz) serial buses61

Post-Processing and Analysis Tool SetsSerial AnalysisWhen You Want to Analyze SerialBit Streams . . ....specify which signal you want toconvert to parallel format byselecting a specific bit of anyavailable label....accept the default outputlabel“Parallel” or modify thelabel name for easy recognition....set the output parallel wordwidth (up to 32 bits)....select the specific state inthe trace where conversionbegins....specify the order in whichthe bits occur in the serialdata streamMSB = Most SignificantBit firstLSB = Least SignificantBit first....enable frame processing toextract all instances of adefined frame....maintain or invert theinput serial bit stream....capture serial data with or withoutan external clock reference.Enable clock recovery for anincoming serial bit stream that hasno external clock reference.(RS-232 is an example of a buswith clocking embedded within theserial bit stream).Figure 5.16.62

Post-Processing and Analysis Tool SetsSerial AnalysisTo Separate Frame Informationfrom the Data Block . . ....accept the defaultstart of frame label“Start” or modify thelabel to a name of yourchoosing....specify the patternthat designates the startof a frame....get immediate feedbackas you configurethe tool set for yourdata. This diagramchanges as you makeyour framing and datablock selections....remove stuffed 0s or0/1s from the tracebefore other serialanalysis functions areperformed. Some protocolsuse bit stuffing tomaintain clocksynchronization....specify whether theend of frame occurs atthe end of a data blockof X bits or on a specifiedpattern....specify the portion ofthe data block for theserial-to-parallelconversion....accept the defaultend of frame label“End” or enter adifferent name.Figure 5.17.63

Post-Processing and Analysis Tool SetsSerial AnalysisTo Acquire a Serial Bit Streamwithout an External ClockReference . . ....set the sample period ofyour timing analyzer to takefour or more samples foreach serial bit....accept the “Samples”default label or enter a newlabel name....specify the embedded bittime of the serial bitstream....specify the incomingsignal’s data encodingmethod, normal or NRZI.Figure 5.18.Clock Recovery Algorithm1. For analysis purposes the data iscaptured in conventional timingmode using the internal timinganalyzer clock as the clock reference.Set the sample period of thetiming analyzer to take four ormore samples for each serial bit.2. The timing analyzer data is sampledin the middle of each bitaccording to the serial bit ratedefined in the clock recoverywindow.3. Data edges (transitions from 0 to 1or 1 to 0 in the timing analyzertrace) are used to resynchronizethe sampling.How Clock Recovery WorksEmbedded bit timeResynchronize on edgeIncoming serialbit streamTiming analyzer samples(with timing analyzer setto take five samples foreach serial bit)New “Samples”serial data00000000000000000000011111111111111111111111111110 0 0 0 1 1 1 1 1Figure 5.19.64

Post-Processing and Analysis Tool SetsSerial AnalysisOnce the Serial Bit Stream isAcquired . . .This example shows the conversion of an RS-232 serial bit stream. The data sent to theprinter includes the column header”MACHINE”....configure theserial tool once foryour specific bus,then save the configurationforfuture uses....view the serial-to-parallelconversion in the format thatis easiest for you — waveformor listing....display the parallel data in binary, hex, octal, decimal,ASCII or Twos Complement....use the global markers and time tags to correlatereal-time serial traces to other system activity....synchronize the start of the serial-to-parallel conversionto the start of the frame pattern for your specificbus....convert the data block into parallel words, in thiscase 8-bit words....find the Nth occurrence of specific frames or datarelative to the trigger, other markers, or the beginningor end of the trace. Markers allow you to quicklysearch from frame to frame in the data....view the data in the order in which the bits occurin the serial stream, in this case LSB.Figure 5.20.65

Post-Processing and Analysis Tool SetsSerial AnalysisProduct CharacteristicsData SourcesAll state and timing measurementmodules supported by the 16700Series logic analysis systems servewithout modification as data sourcesfor the B4601B serial analysis toolset. The particular measurementmodule used determines time resolutionand accuracy. Sample rate, channelcount, memory depth and triggeringare controlled by the user independentof the serial analysis tool.Because every trace is non-intrusive,and every event captured in the traceis time-stamped, you can correlateactivity from your serial bus withother events in the target system.The Agilent Technologies 16720A and16522A pattern generator modulescan be used to generate your ownserial test data.Maximum Parallel Word Width32 bitsParallel Data Display TypesBinary, Octal, Hex, Decimal, ASCII,Twos ComplementOff-line Analysis and Post-ProcessingAll measurements can be saved usingthe file out tool. Data can be recalledat any time for later analysis usingany analysis or display tool. Serialmeasurement data can be exported toyour host computer as ASCII files.Serial Measurement Characteristics16517A/18A 16710A/11A/12A 16715A 16716A 16717A/18A/19A 16750A/51A/52AMaximum serial Clocked data [1] 64 Kbits 8 Kbits/32 Kbits/ 2 Mbits 512 Mbits 2 Mbits/8 Mbits/ 4 Mbits/16Mbits/trace depth 128 Kbits 32 Mbits 32 MbitsUnclocked data [2] 16-32 Kbits 4 Kbits/16Kbits/ 1 Mbit 256 Mbit 1 Mbit/4 Mbits/ 2 Mbits/8 Mbits/64 Kbits 16 Mbits 16 MbitsMaximum serial Clocked data [3] 1 Gbit/s 100 Mbits/s 167 Mbits/s 167 Mbits/s 333 Mbits/s 400 Mbits/sbus frequencyUnclocked data [4] 1 Gbit/s 125 Mbits/s 167 Mbits/s 167 Mbits/s 167 Mbits/s 200 Mbits/sMinimum serial Clocked data 20 Mbit/s No limit No limit No limit No limit No limitbus frequencyUnclocked data [5] 765 Mbits/s 5 Kbits/s 50 bits/s 50 bits/s 50 bits/s 50 bits/sInformation in Table above calculated according to notes [1] to [5][1] =Maximum State Memory Depth[2] =Maximum Timing Memory Depth/4[3] =Maximum State Frequency[4] =Maximum Timing Frequency/4[5] =1/(Maximum sample period x 20)66

Post-Processing and Analysis Tool SetsTool Development KitCustomize Your MeasurementsThe ability to interpret and displayinformation is vital to your project.At times the information you needcan be buried in the raw data of yourmeasurement. This might be due toone of several reasons:• The use of a protocol, encodeddata, or proprietary bus• Events that happen only undercertain conditions• The need to analyze systemperformance• The need to analyze data acrossa large number of repetitivemeasurementsProduct DescriptionThe Agilent Technologies B4605B tooldevelopment kit provides a completeenvironment for creating customtools that processes data using thepowerful search and filtering capabilitiesof the logic analysis system.Features of the tool kit include:• Fast, compiled and optimized Ccode• Push button compiling, no makefiles• A rich library of functions thatspeeds development• Extensive examples of code• The creation of installable tools• One year of technical support forthe B4605BData is processed quickly by the customtools, because they consist ofcompiled, optimized C code. A C languageprogramming background ishighly recommended. A tutorial,extensive examples, and a richlibrary of functions are provided thathelp you easily access analyzer dataand the tool's interface.The custom tools can be used on any16700 Series logic analysis system.This allows you to purchase just oneor two copies of the development kitand develop custom tools to supporta large number of analyzers.Enhance Data Displays• Color-code specific states of yourtrace.• Display some of your trace data inengineering units.• Convert the raw trace of a proprietarybus to a transaction-leveltrace of that bus.Manipulate Data• Unravel interleaved data into twoor more columns of data.• Combine the traces of two differentanalyzers into one trace, witheach column being combined orseparately displayed as prescribedby you.• Modify your scope trace using analgorithm developed by you, suchas an analog filter, beat frequency,or DSP algorithm.Read or Write External Files• Accumulate information fromrepetitive traces taken by the analyzerin a file on your PC or UNIXworkstation.• Write specific types of states ortrace data that have been analyzedto an Excel consumable ASCII fileon your PC or UNIX workstation.• Use information read from a fileon your PC or UNIX workstationto modify the display of ananalyzer trace.67

Post-Processing and Analysis Tool SetsTool Development KitCustom Tool Example, Added Text inTraceThis example shows how a customtool can convert data to text to presentinformation in an easy-to-understandform.The original trace comes from acontrol unit in an automobile.Embedded in the data is informationabout the engine and transmission.When MODE = 0, DATA representsengine information, including RPM,fuel level, fuel to air ratio, and manifoldpressure. When MODE = 1,DATA represents transmission information,including gear position andtemperature.Output of Custom ToolOriginal TraceThis custom tool allows the user tospecify Fahrenheit or Centigrade forthe engine temperature data.68Figure 5.21.Parameter Interface of Custom Tool

Post-Processing and Analysis Tool SetsTool Development KitCustom Tool Example, MicroprocessorCode ReconstructionThe original trace came from the busof a MPC 555 processor. As you cansee, no data was placed on the bus atthe time of the trace because cachememory was turned on. Normally, itwould not be possible to inverseassemble this trace.The output of the custom tool in thisexample is shown. Notice that thereis now data in the DATA column. Thecustom tool was able to reconstructthe code flow after the trace wastaken. The code was reconstructed byusing the branch trace messages andinformation in the SRecord file creat-ed when the code was compiled. Thetool took the address of the appropriatestates in the trace data and foundthe corresponding code (data) in theSRecord file. This created a trace thatthe MPC 555 inverse assembler couldoperate on properly.Original TraceOutput of Custom ToolBy entering information here, users can directthe tool to the correct SRecord file and controlhow much of the data the tool is to operate on.They can also indicate if the AT2 pin of the MPC555 processor is in use.Figure 5.22. Code reconstructionParameter Window of Custom Tool69

Post-Processing and Analysis Tool SetsTool Development KitCustom Tool Example, Multiplex DataCustom tools can combine severallines of data acquired sequentiallyunder one label into one line of data.However the data to be combineddoes not have to come from the samelabel, it can come from differentlabels. The labels can even come fromdifferent analyzers.Output of Custom ToolOriginal TraceAt left are the parameter window andmessage display created by the customtool in this example. Parameters allow theuser to control different aspects of whatthe tool does to the acquired trace. Theuser can change the parameters and hitthe execute button to change the outputof the tool. The output dialog to theleft displays information generated bythe tool.Figure 5.23.70Parameter and Output Windows

Post-Processing and Analysis Tool SetsTool Development KitCustom Tool DevelopmentEnvironmentThis is the main window fordeveloping code with the tooldevelopment kit.Select this button to cause the compiled codeto operate on the acquired data.Select this button to compile thecode displayed in the “SourceCode” tab.Load a file created on anothersystem or create your code hereusing the “Source Code” editor.Compilation status is shownat the bottom of the tooldevelopment kit Display window.Runtime errors are displayed inthe “Runtime” tab.Errors generatedduring a compileare displayed inthe “Buildtime”tab.Output generatedduring the tool’sexecution aredisplayed in the“Output” tab.Figure 5.24. TDK development environment71

Post-Processing and Analysis Tool SetsTool Development KitProduct CharacteristicsAnalyzer compatible custom toolswill run on any 16700 Series analyzerrunning version A.01.40.00 orgreater. In some rare instances,changes in the operating system canrequire that your tools be recompiledin order to run on that version of theoperating system.Analysis and Stimulus ModulesThe tool development kit supportsthe following Agilent Technologiesmeasurement modules:• 16715A, 16716A, 16717A, 16718A,16719A, 16750A, 16751A, 16752A• 16710A, 16711A, 16712A• 16557D• 16556A/D, 16555A/D• 16554A• 16550A• 16534A, 16533A• 16517A, 16518A• 16522A, 16720A• 16740A, 16741A, 16742AC CompilerThe libraries provided with the Ccompiler allow you to perform standardoperations such as creatingASCII or binary files, reading fromthese files, writing or appending tothese files, and IEEE 764 floatingpoint operations.Provided FunctionsAgilent Technologies provides a richlibrary of functions that allow you tocopy data sets, create new data setswith new labels, and to reorganizethe acquired data under these newlabels or to include data or textderived from the acquired data.The functions allow:• Stopping a repetitive run• Filtering of the data• Randomly accessing the data• Searching the data• Displaying the data in one of eightcolors• Accessing the trigger point• Accessing the acquired time orstate of the data• Outputting text strings to thetool's display window• Outputting errors to the runtimewindowBy using two of the provided functions,a simple user interface can easilybe created that consists of labelstrings and input fields. This allowsthe input of parameters during thetool's execution.72

Post-Processing and Analysis Tool SetsLicensing InformationLicensing and MiscellaneousDescriptionSystem Configuration RequirementsTool Set ControlFile AccessOrdering and Shipment• 16700 Series logic analysis system• Desired tool set(s)• Supported and compatible measurement hardware• Locally control and view tool set measurements• Remotely access any tool set from a PC or workstation through a web browser or X-window emulationsoftware.• Access source files or other development environment applications (compiler, debugger) from the logicanalyzer via Telnet, NFS, or mapped file systems, and X-Windows client/server protocols.• Save or access files via the standard network capabilities of the logic analyzer, such as FTP, NFS, or CIFS(Common Internet File System for Windows 95/98/NT based PCs.• When a tool set is ordered with a 16700 Series mainframe, the tool set is shipped installed and ready torun (Unless option 0D4 is ordered.)• Tool set proof-of-receipt is provided by the entitlement certificate.See page 121 for ordering information.Tool Set Licensing InformationLicense PolicyNodelock ModeFree Tool Set Evaluation(Temporary Demo License)License ManagementPassword BackupThe 16700 Series logic analysis systems’ tool set software is licensed for single-unit use only. Licensesare valid for the life of the tool set. Software updates do not affect the license.• Tool set licenses are shipped or first installed as nodelocked applications. Nodelocked means that use ofthe tool set license is only allowed on the single node (16700 Series analyzer on which it is installed). Toolsets ordered with a 16700 Series mainframe will be installed with a permanent password and are ready torun.• For tool sets purchased as upgrades to existing 16700 Series mainframes, you must access the Agilentpassword redemption web site to obtain a password. Your entitlement certificate provides the web URLand alternate contact information. Password turnaround is generally the same business day.A single temporary license is available for any tool set type not previously licensed on a node. Thetemporary password for any node on any tool set is "demo". The temporary license is valid for 21 calendardays from first entry of the password in the license management window of the 16700 Series logicanalysis system.Licenses are managed from ‘Licensing…’ in the Admin tab of System Admin. Licenses are reserved at thestart of a measurement session. They remain in use until the measurement session is terminated.Passwords can be backed up to a floppy disk or network file. Should the passwords on your 16700 Serieslogic analysis system hard drive become corrupted, the tool set passwords can be reinstated by copyingyour backed up password file to: /system/licensing/license.dat73

Time Correlation with Agilent Infiniium OscilloscopesE5850A Logic Analyzer - Oscilloscope Time Correlation FixtureE5850A Logic Analyzer – OscilloscopeTime Correlation FixtureThe Agilent E5850A time correlationfixture allows you to make time-correlatedmeasurements between a16700 logic analyzer and an Agilent548XX Series Infiniium oscilloscopeto solve the following types of problemsmore effectively:• Verifying signal integrity• Tracking down problems causedby signal integrity• Verifying correct operation of A/Dand D/A converters• Verifying correct logical and temporalrelationships between theanalog and digital portions of adesignAgilent’s E5850A time correlationfixture works in conjunction withsoftware in the 16700 family logicanalyzers, and any Agilent Infiniium54800 Series oscilloscope, to deliverthe following features:• Automatic de-skew.Measurements between the logicanalyzer and Infiniium oscilloscopeare automatically de-skewedin time. This saves you time andgives you confidence in the measurementresults.• Combined waveform display.The Infiniium oscilloscope waveformsare displayed in the waveformdisplay window on the 16700logic analyzer, along with timinganalyzer waveforms. This allowsyou to instantly visualize timerelationships among oscilloscopeand timing measurements.• Global markers.The global markers in the 16700may be used to measure timeamong all measurements made inthe logic analyzer and Infiniiumoscilloscope measurements.• Tracking markers.The Infiniium oscilloscope’s timemarkers track the global markersin the 16700 logic analyzer. If youwish to view a waveform ingreater detail on the oscilloscope’sdisplay, or measure a voltage levelusing the oscilloscope’s voltagemarkers, this feature allows you torelate information on the oscilloscope’sdisplay precisely to correspondinginformation on the logicanalyzer display.Figure 5.26. E5850A time correlation fixture.CompatibilityFor Infiniium Software version Software version for oscilloscopefor 16700 series Infiniium oscilloscopemodel number logic analyzer54810A A.02.20.00 or higher A.04.00 or higher54815A54820A54825A54835A54845A54856A54830B A.02.50.00 or higher A.01.00 or higher54831B54832BThe E5850A requires the versions of operating software indicated in the tableFigure 5.25. Infiniium oscilloscope waveforms are displayed in the 16700 logicanalyzer waveform display window along with logic analyzer timing waveforms,accurately time-correlated.74

Mainframe Specifications andCharacteristicsAgilent 16700 Series TechnicalInformationSystem SoftwareAll features and functionalitydescribed in this document areavailable with system softwareversion A.02.20.00Mass StorageHard Disk DriveFloppy Disk Drive• Capacity• Media• FormatsInternal System RAMStandardOption 003 (Must be ordered attime of frame purchase)9 GB formatted disk drive1.44 MB formatted3.5 inch floppyMS-D0S (Read, write, format), LIF (Read only)128 MB256 MB totalSupported Monitor ResolutionsStandard 640 x 480 through 1280 x 1024(The 16702B has a built-in 800 x 600, 12.1”(26.2mm) diagonal monitor.)Option 003 (Must be ordered at Adds support for up to 1600 x 1200time of frame purchase)LAN, IEEE 802.3Physical ConnectorsProtocols SupportedX-Window Support16700B Series:10BaseT/100BaseT-X (ethertwist): RJ-4516700A Series:10BaseT (ethertwist): RJ-45; 10Base2: BNCTCP/IPNFSCIFS (Windows® 95/98/NT) [1]FTPNTPPCNFSX Window system version 11, release 6, as a client andserver[1] User and share level control supported for Windows NT ® 4.0. Share level control only supported forWindows 95/98.75

Mainframe Specifications andCharacteristicsAgilent 16700 Series TechnicalInformation (continued)Web ServerSupported from InstrumentWeb PagePC RequirementsSupported Web Browsers(on Your PC or Workstation)Measurement status check,remote display, installationof PC application software, link to Agilent’s Test andMeasurement sitePentium® (family) PC (200 MHz, 32 MB RAM) runningWindows 95, Windows 98, or Windows NT 4.0 withservice pack 3 or higherInternet Explorer 4.0 or higher,Netscape 4.0 or higherIntuiLink SupportInstallation of PC Application SoftwareMS ExcelDirectly from instrument web pageExcel 97 Version 7.0 or later. Excel limits maximum tracedepth to 64K per sheet.Available Data FormatsFast Binary (CompressedBinary Format)Uncompressed BinaryASCIIPattern Generator BinaryHigh performance transfer rate. Includes source code toparse data. Available via File Out.Includes utility routines. Available via RPI.Provides same format as listing display, includinginverse-assembled data. Available via RPI and File Out.Used to load large amount of stimulus (> 1M) into the16720A pattern generatorIntermodule Bus (IMB)Time Correlation Resolution2 nsPort In/OutConnectorsBNC76

Mainframe Specifications andCharacteristicsAgilent 16700 Series TechnicalInformation (continued)Port InLevelsInput ResistanceInput VoltageTTL, ECL, or user defined4 KΩ–6V at –1.5 mA to +6V at 1.6 mAPort OutLevelsFunctions3V TTL compatible into 50 ΩLatched (latch operation is module dependent)Pulsed, width from 66 ns to 143 nsTarget Control PortNumber of signals 8LevelsConnector3V TTL compatible2 rows of 5 pins, 0.1-inch centersOperating EnvironmentTemperature• Instrument• Disk Media• Probes/CablesAltitudeHumidity0°C to 50°C (32°F to 122°F)10°C to 40°C (50°F to 104°F)O°C to 65°C (32°F to 149°F)To 3000m (10,000 ft)8 to 80% relative humidity at 40°C (104°F)PrintingPrinter InterfacePrinters SupportedGraphicsParallel interface for Centronics compatible printersPostScript printers and printers which support theHP Printer Control Language (PCL)Graphics can be printed directly to the printer or to a file.Graphic files can be created in black-and-white or colorTIFF format, PostScript, PCX, or XWD formats77

Mainframe Specifications andCharacteristicsRemote Programming Interface (RPI)RPI OverviewTypical ApplicationsRemote ProgrammingStepsPhysical ConnectionManufacturing TestData Acquisition for Offline AnalysisSystem Verification and CharacterizationPass/Fail AnalysisStimulus Response Tests1.Set up the logic analyzer and save the test configuration.2.Create a program that remotely:Loads a test configurationStarts the acquisition processChecks measurement status (verifies completion)Acts on the results of the data acquisition• Saves configuration and captured data• Exports data• Executes a compare• Modifies the trigger setup or trigger value for the nextacquisition• Accesses the oscilloscope’s automatic measurementsRemote programming is done via the LAN connectionRequirements16700B SeriesAnalysis SystemsPCUNIX ®RPI is standard with system software version A.02.00.00 orhigherProgramming is done via Microsoft® ActiveX/COMautomationPentium (family) PC with one of the following:• Windows 95• Windows 98• Windows NT 4.0 with Service Pack 3 or higherVisual Basic or Visual C++ (Version 5.0 or higher)Programming is done via TCP/IP socket basedASCII commands78

Mainframe Specifications andCharacteristicsRemote Programming Interface (RPI) (continued)Command Set Summary - Commands available on both UNIX and PCSystemLogic Analysis ModulesOscilloscope ModulesPattern GeneratorEmulation ModuleListing ToolCompare ToolFile Out ToolSystem Configuration QueryLoad/Save Configuration and DataStart/Stop MeasurementCurrent Run StatusStart/Stop/Query a SessionLoad/Save Configuration and DataTrigger SetupAcquisition Data and ParametersSet/Query Acquisition ModeSet/Query Acquisition DepthSet/Query Pod AssignmentAdd/Delete/Load/Query LabelsSet/Query Trigger PositionModify Occurrence CountLoad/Save Configuration and DataAcquisition Data / ParametersQuery Automatic MeasurementsTrigger SetupLoad/Save Configuration and DataLoad ASCII file (vectors) or PGB (pattern generator binary)files (16720A only)Modify VectorSet/Query Clock FrequencySet/Query Clock Out DelayInsert New Vector at Specific PositionDelete Specific VectorReset ProcessorRun ProcessorBreak ProcessorSingle StepStatusAcquisition Data and ParametersTransfer Data (includes inverse assembled information)Execute CompareSet Compare MaskQuery Compare ResultSpecify Range to CompareAbort Compare After Specified Number of DifferencesReturn Labels and Values Where Differences OccurTransfer Data to FileSelect Range to ExpertAdditional InformationInstrument Online HelpWeb SitesProgramming Information in instrument online helpFull remote programming documentation (pdf) available onthe hard drive. Sample programs are provided79

Mainframe Specifications andCharacteristicsIntuiLinkProgramming Examples Provided with IntuiLinkVisual Basic Examples have been included for use with Visual Basic 5.0or higher. These examples perform simple functions suchas: system checks, oscilloscope measurements, pass/failtests using stored configuration and pattern generatorstimulus files, and stimulus/response tests. They also cancapture and retrieve data for off-line analysis.Visual C++LabVIEWHP VEEExamples have been included for use with Visual C++ 5.0 orhigher to perform simple functions such as: system check,capturing and retrieving data for off-line analysis.An instrument library has been included for use withLabVIEW 5.1 or higher. This library contains five LabVIEWsamples that provide a starting point for creating your ownLabVIEW programs.• Load/Run/Save - loads a configuration, runs ameasurement, then saves results to a file• Analyzer Listing - runs the logic analyzer and displaysdata in a table• Pass/Fail - runs the logic analyzer and compares themeasurement data against a standard• Scope Waveform - runs the oscilloscope module anddisplays waveform data• Scope Measurements - runs the oscilloscope moduleand displays a number of oscilloscope measurementsAn instrument library has been included for use withHP VEE 5.0 or higher that provides a starting point forcreating your own application.• Load/Run/Save - loads a configuration, runs ameasurement, then saves results to a file80

Mainframe Specifications andCharacteristicsAgilent 16700B Series PhysicalCharacteristicsPower12.1” Built-in LCDDisplay with TouchScreen3.5 Inch FloppyDisk Drive16700B16701B16702B115/230 V, 48 to 66 Hz, 610 W max115/230 V, 48 to 66 Hz, 545 W max115/230 V, 48 to 66 Hz, 610 W maxOn/OffPower SwitchWeight*Max Net Max Shipping16700B 12.7 kg (27.0 lb) 34.2 kg (75.4lbs)16701B 10.4 kg (23.0 lb) 32.0 kg (70.6lbs)16702B 15.2 kg (32.4 lb) 36.7 kg (80.8lbs)* Weight of modules ordered with mainframes will add0.9 kg (2.0 lb) per module.Figure 6.1. Agilent 16702B front panel.RS-Five Slots forMeasurementModulesMonitorABCDEParallel PortTouch Screen On/OffLAN 10BaseT/100BaseT-XSCSI-2 Single EndedOne Slot forEmulation orMultiframeModuleTarget Control PortPort INPort OUTKeyboard MouseExpansion Frame Cable Connector40x CD-ROMDriveFigure 6.2. Back panel for Agilent models 16700B and 16702B.551.2 (21.7”)425.7 (16.75”)234.2(9.22”)Figure 6.3. Exterior dimensions for the 16700B Series mainframe.Dimensions: mm (inches)81

Mainframe Specifications andCharacteristicsAgilent 16700A Series PhysicalCharacteristicsPowerBuilt-in LCD Display3.5 Inch FloppyDisk Drive16700A16701A16702A115/230 V, 48 to 66 Hz, 610 W max115/230 V, 48 to 66 Hz, 545 W max115/230 V, 48 to 66 Hz, 610 W maxOn/OffPower SwitchWeight*Max Net Max Shipping16700A 12.7 kg (27.0 lb) 34.2 kg (75.4lbs)16701A 10.4 kg (23.0 lb) 32.0 kg (70.6lbs)16702A 15.2 kg (32.4 lb) 36.7 kg (80.8lbs)* Weight of modules ordered with mainframes will add0.9 kg (2.0 lb) per module.Figure 6.4. Agilent 16702A front panel.RS-Five Slots forMeasurementModulesMonitorTarget Control PortABCDEScreen Intensity AdjustmentParallel PortKeypads for Alpha-Numeric EntryLAN 10BaseTSCSI-2 Single EndedLAN 10Base212Two Slots forEmulationModulesPort INPort OUTKeyboard MouseExpansion Frame Cable ConnectorFigure 6.5. Back panel for Agilent models 16700A and 16702A.548.64 (21.6”)556.3 (21.9”) 482.6 (19.0”)425.7 (16.76”)234.2(9.22”)Figure 6.6. Exterior dimensions for the 16700A Series mainframe.Dimensions: mm (inches)82

Probing Solutions Specifications andCharacteristicsProbing Technical SpecificationsPOWER GND 2SIGNAL GND 4SIGNAL GND 6SIGNAL GND 8SIGNAL GND 10SIGNAL GND 12SIGNAL GND 14SIGNAL GND 16SIGNAL GND 18SIGNAL GND 20SIGNAL GND 22SIGNAL GND 24SIGNAL GND 26SIGNAL GND 28SIGNAL GND 30SIGNAL GND 32SIGNAL GND 34SIGNAL GND 36SIGNAL GND 38POWER GND 401 +5V3 CLK15 CLK27 D159 D1411 D1313 D1215 D1117 D1019 D921 D823 D725 D627 D529 D431 D333 D235 D137 D039 +5V+5V 1CLK1 3CLK2 5D15 7D14 9D13 11D12 13D11 15D10 17D9 19D8 21D7 23D6 25D5 27D4 29D3 31D2 33D1 35D0 37+5V 392 POWER GND4 SIGNAL GND6 SIGNAL GND8 SIGNAL GND10 SIGNAL GND12 SIGNAL GND14 SIGNAL GND16 SIGNAL GND18 SIGNAL GND20 SIGNAL GND22 SIGNAL GND24 SIGNAL GND26 SIGNAL GND28 SIGNAL GND30 SIGNAL GND32 SIGNAL GND34 SIGNAL GND36 SIGNAL GND38 SIGNAL GND40 POWER GNDCLK 2 2D15 4D13 6D11 8D9 10D7 12D5 14D3 16D1 18GND 201 +5V3 CLK 15 D147 D129 D1011 D813 D615 D417 D219 D0Figure 6.7. Pinout for state/timing module pod cable and 100 KΩ isolation adapter. (Agilent 01650-63203)+5V 1CLK1 3D14 5D12 7D10 9D8 11D6 13D4 15D2 17D0 192 CLK24 D156 D138 D1110 D912 D714 D516 D318 D120 GNDFigure 6.8. Pinout for 20-pin connector. (Agilent 1251-8106)83

Probing Solutions Specifications andCharacteristicsIsolation Adapter 01650-63203Isolation adapters that connect tothe end of the probe cable aredesigned to perform two functions.The first is to reduce the number ofpins required for the header on thetarget board from 40 pins to 20pins. This process reduces theboard area dedicated to the probingconnection. The second functionis to provide the proper RCisolation networks in a very convenientpackage.SignalGroundSignalGroundAdapter RC Network250 90.9kohm ohm8.2pFEquivalent Load370ohm4.6pF7.4pFTo LogicAnalyzerPod100kohmIncludes logic analyzerFigure 6.9. Termination adapter and equivalent load.E5346A 38-pin ProbeSignal370 ohm3pF9pF100kohmGroundFigure 6.10. E5346A equivalent load.E5339A 38-pin Low Voltage ProbeSignal220 ohm3pF18pF50.5kohmGroundFigure 6.11. E5339A equivalent load.84

State/Timing Modules Specifications andCharacteristicsKey Specifications* and CharacteristicsAgilent Model Number 16715A, 16716A, 16717A 16740A, 16741A, 16742A 16750A, 16751A, 16752A 16760AMaximum state acquisition rate on 16715A, 16716A: 167 Mb/s 200 Mb/s 400 Mb/s [1] Full channel: 800 Mb/seach channel 16717A, 333 Mb/s [1] Half channel: 1.25 Gb/sMaximum timing sample rate Timing Zoom: 2 GHz (16716A, Timing Zoom: 2 GHz Timing Zoom: 2 GHz Conventional: 800 MHz(half/full channel) 16717A only) Conventional: 800/400 MHz Conventional: 800/400 MHz Transitional: 400 MHzConventional: 667/333 MHz Transitional: 400 MHz Transitional: 400 MHzTransitional: 333 MHzChannels/module 68 68 68 34Maximum channels on a 340 (5 modules) 340 (5 modules) 340 (5 modules) 170 (5 modules)single time base and triggerMemory depth 16715A, 16717A: 4/2M [2] 16740A: 2/1 M [2] 16750A: 8/4M [2] 128/64M [5](half/full channel) 16716A: 1M/512K [2] 16741A: 8/4 M [2] 16751A: 32/16M [2]16742A 32/16 M [2] 16752A: 64/32M [2]Trigger resources Patterns: 16 Pattern: 16 Patterns: 16 At 800 Mb/s: 4 patterns orRanges: 15 Ranges: 15 Ranges: 15 2 ranges, 4 flags, arm inEdge & Glitch: 2 Edge & Glitch: 2 Edge & Glitch: 2 At 200 Mb/s: same as16750A,Timers: (2 per module) -1 Timers: (2 per module) –1 Timers: (2 per module) -1 16751A, 16752AOccurrence Counter: [4] Occurrence Counter: 2 Occurrence Counter: [4] Other speeds: refer toGlobal Counters: 2 Global Counter: 2 Global Counters: 2 synchronous state analysisFlags: 4 Flags: 4 Flags: 4 (page 98) and asynchronoustiming analysis (page 100)Maximum trigger sequence levels 16 16 16 1.25 Gb/s: 2800 Mb/s: 4200 or 400 Mb/s: 16Maximum trigger sequence speed 16715A, 16716A: 167 MHz 200 MHz 400 MHz 1.25 Gb/s16717A: 333 MHzTrigger sequence level branching 4-way arbitrary “IF/THEN/ELSE” 4-way arbitary 4-way arbitrary “IF/THEN/ELSE” 800 or 1.25 Gb/s: nonebranching “IF/THEN/ELSE” branching 200 Mb/s: arbitrarybranching“IF/THEN/ELSE” branching400 Mb/s: dedicated nextstatebranch or resetNumber of state clocks/qualifiers 4 4 4 1 (state clock only)Setup/hold time* 2.5 ns window adjustable from 2.5 ns windows adjustable from 2.5 ns window adjustable from 1 ns window adjustable from4.5/-2.0 ns to -2.0/4.5 ns in 100 ps 4.5/2.0 ns to -2.0/4.5 ns in 100 ps 4.5/-2.0 ns to -2.0/4.5 ns in 100 ps 2.5/-1.5 ns to -1.5/2.5 nsincrements per channel [3] increments per channel [3] increments per channel [3] 10 ps increments per channelThreshold range TTL, ECL, user-definable ±6.0 V TTL, ECL, user-definable ±6.0 V TTL, ECL, user-definable ±6.0 V -3.0 V to 5.0 V adjustable inadjustable in 10-mV increments adjustable in 10-mV increments adjustable in 10-mV increments 10-mV increments* All specifications noted by an asterisk are the performance standards against which the product is tested.[1] State speeds greater than 167 MHz (16717A) or 200 MHz (16750A, 16751A, 16752A, 16760A) require a trade-off in features.Refer to “Supplemental Specifications and Characteristics” on page 93 for more information.[2] Memory depth doubles in half-channel timing mode only.[3] Minimum setup/hold time specified for a single clock, single edge acquisition. Multi-clock, multi-edge setup/hold window add 0.5 ns.[4] There is one occurrence counter per trigger sequence level.[5] Memory depth doubles in half-channel 1.25 Gb/s state mode only.85

State/Timing Modules Specifications andCharacteristicsKey Specifications* and Characteristics (continued)Agilent Model NumberMaximum state acquisition rate oneach channelMaximum timing sample rate(half/full channel)16710A, 16711A, 16712A100 Mb/sConventional: 500/250 MHzTransitional: 125 MHzChannels/module 102Maximum channel count on asingle time base and trigger204 (2 modules)Memory depth 16710A: 16/8K [1](half/full channel) 16711A: 64/32K [1]16712A: 256/128k [1]Trigger resources Patterns: 10Ranges: 2Edge & Glitch: 2Timers: 2Maximum trigger sequence levels State mode: 12Timing mode: 10Maximum trigger sequence speedTrigger sequence level branching125 MHzDedicated next state orsingle arbitrary branchingNumber of state clocks/qualifiers 6Setup/hold time*Threshold range4.0 ns window adjustable from4.0/0 ns to 0/4.0 ns in 500 psincrements [2] per 34 channelsTTL, ECL, user-definable ±6.0 Vadjustable in 50 mV increments* All specifications noted by an asterisk are the performance standards against which the product is tested.[1] Memory depth doubles in half-channel timing mode only.[2] Minimum setup/hold time specified for single-clock, single-edge acquisition. Single-clock, multi-edge setup/holdadd 0.5 ns. Multi-clock, multi-edge setup/hold window add 1.0 ns.86

State/Timing Modules Specifications andCharacteristicsAgilent Technologies 16710A, 16711A, 16712ASupplemental Specifications* and Characteristics370 ohmsProbes (general-purpose lead set)Input resistance 100 KΩ, ±2%1.5pF7.4pF100KohmParasitic tip capacitanceMinimum voltage swingThreshold accuracy*Maximum input voltage1.5 pF500 mV, peak-to-peak±(100 mV + 3% of threshold setting)±40 V peakGROUNDFigure 6.12. Equivalent probe load for theAgilent 16710A, 16711A and 16712A, generalpurposelead set.State AnalysisMinimum state clock pulse widthTime tag resolution [1]Maximum time count between statesMaximum state tagcount between states [1]Minimum master to master clock time*Minimum master to slave clock timeMinimum slave to master clock timeContext store block sizes16710A/11A/12A only3.5 ns8 ns34 seconds4.29 x 10 9 states16710A, 16711A, 16712A: 10 ns0.0 ns4.0 ns16, 32, 64 statesTiming AnalysisSample period accuracyChannel-to-channel skewTime interval accuracyMinimum detectable glitch0.01% of sample period2 ns, typical± (sample period + channel-to-channelskew + 0.01% of time interval reading)3.5 ns* All specifications noted by an asterisk are the performance standards against which the product is tested.[1] Time or state tags halve the acquisition memory when there are no unassigned pods.87

State/Timing Modules Specifications andCharacteristicsAgilent Technologies 16710A, 16711A, 16712ASupplemental Specifications* and Characteristics (continued)TriggeringMaximum trigger sequence speed125 MHz, maximumMaximum occurrence counter 1,048,575Range widthTimer value rangeTimer resolutionTimer accuracy32 bits each400 ns to 500 seconds16 ns or 0.1% whichever is greater±32 ns or ±0.1% whichever is greaterOperating EnvironmentTemperatureHumidityAltitudeAgilent 16700 Series mainframes:• Instrument 0˚C to 50˚C (+32˚F to 122˚F)• Probe lead sets and cables, 0˚C to 65˚C (+32˚F to 149˚F)80% relative humidity at +40˚COperating 4600m (15,000ft)Nonoperating 15,300m (50,000ft)* All specifications noted by an asterisk are the performance standards against which the product is tested.88

State/Timing Modules Specifications andCharacteristicsAgilent Technologies 16715A, 16716A, 16717A, 16740A, 16741A,16742A, 16750A, 16751A, 16752A Supplemental Specifications*and CharacteristicsProbes (general-purpose lead set)Input resistance 100 KΩ, ± 2%1.5pF370 ohms7.4pF100KohmParasitic tip capacitanceMinimum voltage swingMinimum input overdriveThreshold rangeThreshold accuracy*Input dynamic rangeMaximum input voltage1.5 pF500 mV, peak-to-peak250 mV-6V to +6V in 10 mV increments± (65 mV + 1.5% of settings)± 10V about threshold± 40V peakGROUNDFigure 6.13. Equivalent probe load for theAgilent 16715A, 16716A, 16717A, 16718A,16719A, 16750A, 16751A, 16752A generalpurposelead set.+5V Accessory current 1/3 amp maximum per podChannel assignmentEach group of 34 channels can be assigned toAnalyzer 1, Analyzer 2 or remain unassigned2 GHz Timing Zoom (Agilent 16716A, 16717A, 16740A, 16741A, 16742A, 16750A, 16751A, 16752A only)Timing analysis sample rateSample period accuracyChannel-to-channel skewTime interval accuracyMemory depthTrigger position2 GHz/1 GHz/500 MHz/250 MHz± 50 ps< 1.0 ns± (sample period + channel-to-channel skew + 0.01% oftime interval reading)16 KStart, center, end, or user definedOperating EnvironmentTemperatureHumidityAltitudeAgilent 16700 Series frame: 0˚C to 50˚C (+32˚F to 122˚F)Probe lead sets and cables: 0˚C to 65˚C (+32˚F to 149˚F)80% relative humidity at + 40˚COperating 4600 m (15,000 ft)Non-operating 15,300 m (50,000 ft)* All specifications noted by an asterisk are the performance standards against which the product is tested.89

State/Timing Modules Specifications andCharacteristicsAgilent Technologies 16715A, 16716A, 16717A, 16740A, 16741A, 16742A,16750A, 16751A, 16752A Supplemental Specifications* and CharacteristicsState Mode 16715A, 16716A, 16717A 16740A, 16741A, 16742A167 Mb/s State Mode 16750A, 16751A, 16752A200 Mb/s State ModeMaximum state acquisition rate on 167 Mb/s 200 Mb/seach channelChannel count 68 per module 68 per moduleMaximum channels on a single 340 340time base and triggerNumber of independent analyzers 2, can be set up in state or timing modes 2, can be set up in state or timing modesMinimum master to 5.988 ns 5 nsmaster clock time* [1]Minimum master to slave clock time 2 ns 2 nsMinimum slave to master clock time 2 ns 2 nsMinimum slave to slave clock time 5.988 ns 5 nsSetup/hold time* [1] 2.5 ns window adjustable from 4.5/-2.0 ns to 2.5 ns window adjustable from 4.5/-2.0 ns to(single-clock, single-edge) -2.0/4.5 ns in 100 ps increments per channel -2.0/4.5 ns in 100 ps increments per channelSetup/hold time* [1] 3.0 ns window adjustable from 5.0/-2.0 ns to 3.0 ns window adjustable from 5.0/-2.0 ns to(multi-clock, multi-edge) -1.5/4.5 ns in 100 ps increments per channel -1.5/4.5 ns in 100 ps increments per channelSetup/hold time (on individual channels, 1.25 ns window 1.25 ns windowafter running eye finder)Minimum state clock pulse width 1.2 ns 1.2 nsTime tag resolution [2] 4 ns 4 nsMaximum time count between states 17 seconds 17 secondsMaximum state tag count 2 32 2 32between states [2]Number of state clocks/qualifiers 4 4Maximum memory depth 16716A: 512K 16740A: 1M 16750A: 4M16715A, 16717A: 2M 16741A: 4M 16751A: 16M16742A: 16M 16752A: 32MMaximum trigger sequence speed 167 MHz 200 MHzMaximum trigger sequence levels 16 16* All specifications noted by an asterisk are the performance standards against which the product is tested.[1] Tested at input signal VH=-0.9V, VL=-1.7V, Slew rate=1V/ns, and threshold=-1.3V.[2] Time or state tags halve the acquisition memory when there are no unassigned pods.90

State/Timing Modules Specifications andCharacteristicsAgilent Technologies 16715A, 16716A, 16717A, 16740A, 16741A, 16742A,16750A, 16751A, 16752A Supplemental Specifications* and Characteristics (continued)State Mode 16715A, 16716A, 16717A 16740A, 16741A, 16742A167 Mb/s State Mode 16750A, 16751A, 16752A200 Mb/s State ModeTrigger sequence level branching 4 way arbitrary “IF/THEN/ELSE” branching 4 way arbitrary “IF/THEN/ELSE” branchingTrigger position Start, center, end, or user defined Start, center, end, or user definedTrigger resources 16 Patterns evaluated as =, ≠, >, ,

State/Timing Modules Specifications andCharacteristicsAgilent Technologies 16715A, 16716A, 16717A, 16740A, 16741A, 16742A,16750A, 16751A, 16752A Supplemental Specifications* and Characteristics (continued)State Mode 16715A, 16716A, 16717A 16750A, 16751A, 16752A167 Mb/s State Mode 400 Mb/s State ModeMaximum state acquisition rate 333 Mb/s 400 Mb/son each channelChannel count (Number of modules x 68) - 34 (Number of modules x 68) - 34Maximum channels on a single 306 306time base and triggerNumber of independent analyzers 1, when 333 MHz state mode is selected 1, when 400 MHz state mode is selectedthe second analyzer is turned offthe second analyzer is turned offMinimum master to master clock time* [1] 3.003 ns 2.5 nsSetup/hold time* [1] 2.5 ns window adjustable from 4.5/-2.0 ns to 2.5 ns window adjustable from 4.5/-2.0 ns to(single-clock, single-edge) -2.0/4.5 ns in 100 ps increments per channel -2.0/4.5 ns in 100 ps increments per channelSetup/hold time* [1] 3.0 ns window adjustable from 5.0/-2.0 ns to 3.0 ns window adjustable from 5.0/-2.0 ns to(single-clock, multi-edge) -1.5/4.5 ns in 100 ps increments per channel -1.5/4.5 ns in 100 ps increments per channelSetup/hold time (on individual channels 1.25 ns window 1.25 ns windowafter running eye finder)Minimum state clock pulse width 1.2 ns 1.2 nsTime tag resolution [2] 4 ns 4 nsMaximum time count between states 17 seconds 17 secondsNumber of state clocks 1 1Maximum memory depth 16717A: 2M 16750A: 4M16751A: 16M16752A: 32MMaximum trigger sequence speed 333 MHz 400 MHzMaximum trigger sequence levels 15 15Trigger sequence level branching Dedicated next state branch or reset Dedicated next state branch or resetTrigger position Start, center, end, or user defined Start, center, end, or user defined* All specifications noted by an asterisk are the performance standards against which the product is tested.[1] Tested at input signal VH=-0.9V, VL=-1.7V, Slew rate=1V/ns, and threshold=-1.3V.[2] Time or state tags halve the acquisition memory when there are no unassigned pods.92

State/Timing Modules Specifications andCharacteristicsAgilent Technologies 16715A, 16716A, 16717A, 16740A, 16741A, 16742A,16750A, 16751A, 16752A Supplemental Specifications* and Characteristics (continued)State Mode 16715A, 16716A, 16717A 16750A, 16751A, 16752A167 Mb/s State Mode 400 Mb/s State ModeTrigger resources 8 Patterns evaluated as =, ≠, >, ,

State/Timing Modules Specifications andCharacteristicsAgilent Technologies 16715A, 16716A, 16717A, 16740A, 16741A, 16742A, 16750A,16751A, 16752A Supplemental Specifications* and Characteristics (continued)Timing Mode (continued) 16715A, 16716A, 16717A 16740A, 16741A, 16742A16750A, 16751A, 16752AMaximum trigger sequence speed 167 MHz 200 MHzMaximum trigger sequence levels 16 16Trigger sequence level branching 4 way arbitrary “IF/THEN/ELSE” branching 4 way arbitrary “IF/THEN/ELSE” branchingTrigger position Start, center, end, or user defined Start, center, end, or user definedTrigger resources 16 Patterns evaluated as =, ≠, >, ,

State/Timing Modules Specifications andCharacteristicsAgilent Technologies 16760ASupplemental Specifications* and CharacteristicsProbes E5378A Single-ended E5379A Differential E5380A Mictor E5382A Single-Ended Flying LeadsInput resistance and Refer to figure 6.14 Refer to figure 6.14 Refer to figure 6.14 Refer to figure 6.15capacitanceMaximum state data 1.5 Gb/s 1.5 Gb/s 600 Mb/s 1.5 Gb/srate supportedMating connector Agilent part number Agilent part number Amp Mictor 38 [2] None required1253-3620 [1] 1253-3620 [1]Minimum voltage swing 250 mV p-p V in+ - Vin - >= 200 mV p-p 300 mV p-p 250 mV p-pInput dynamic range -3 Vdc to +5 Vdc -3 Vdc to +5 Vdc -3 Vdc to +5 Vdc -3 Vdc to +5 VdcThreshold accuracy +/- (30 mV + 1% of setting)* +/- (30 mV + 1% of setting) [3] +/- (30 mV + 1% of setting) +/- (30 mV + 1% of setting)Threshold range -3.0 V to +5.0 V -3.0 V to +5.0 V -3.0 V to +5.0 V -3.0 V to +5.0 VUser-supplied threshold -3.0 V to +5.0 V N/A N/A N/Ainput rangeUser-supplied threshold >= 100K ohms N/A N/A N/Ainput resistanceThreshold control options • User-provided input If operated single-ended Adjustable from user Adjustable from user• Adjustable from user (minus inputs grounded), interface interfaceinterfacethe threshold can be adjustedfrom the user interfaceMaximum nondestructive +/-40 Vdc +/-40 Vdc +/-40 Vdc +/-40 Vdcinput voltageMaximum input slew rate 5 V/ns 5 V/ns 5 V/ns 5 V/nsClock input Differential Differential Single-ended DifferentialNumber of inputs [4] 34 (32 data and 2 clock/data) 17 (16 data and 1 clock/data) 34 (32 data and 2 clock/data) 17 (16 data and 1 clock/data)* All specifications noted by an asterisk are the performance standards against which the product is tested.[1] A support shroud, Agilent part number 16760-02302 (for boards up to 0.062" thick) or 16760-02303 (for boards up to 0.120" thick) is recommended.A kit of 5 shrouds and 5 connectors is available as Agilent part number 16760-68702 (for boards up to 0.062" thick) or 16760-68703 (for boards up to 0.120" thick).[2] A kit of 5 Amp Mictor connectors and 5 support shrouds is available, Agilent part number E5346-68701.A support shroud is available separately, Agilent part number E5346-44701.[3] If operated single-ended (minus inputs grounded), the threshold can be adjusted from the user interface.[4] Refer to specifications on specific modes of operation for details on how inputs can be used.C 1R 1R 221512120k0.7pF1pF20k0.6pF+0.75 V+0.75 V30Model Number C 1 R 1 R 2E5378A, E5379A 1.5pF 120 30E5380A 3pF 120 60Figure 6.15. E5382A input equivalent probe load, with5cm damped wire (see user’s guide for load modelswith other accessories).Figure 6.14. E5378A, E5379A, E5380A inputequivalent probe load.95

State/Timing Modules Specifications andCharacteristicsAgilent Technologies 16760ASupplemental Specifications* and Characteristics (continued)Synchronous Data SamplingIndividualData ChannelvHeighttWidthData EyeFigure 6.17. Data Sampling.tSetuptHoldvThreshold*SamplingPositiontSample*—0V—*User AdjustableClock Channel Note (1)Specifications for Each InputParameter Minimum Description/Notes800, 1250, 1500 Mb/s modes 200, 400 Mb/s modesData tWidth* 500 ps 1.25 ns Eye width in system under test [2]to Clock tSetup 250 ps 625 ps Data setup time required before tSampletHold 250 ps 625 ps Data hold time required after tSampleAll vHeight [1] 100mV 100mV E5379A 100-pin differential probe [3]Inputs 250 mV 250 mV E5378A 100-pin single-ended probe [4],E5382A single-ended flying-lead probe set300mV 300mV E5380A 38-pin single-ended probeUser Adjustable Settings for Each InputParameterAdjustment Range1500 Mb/s mode 1250 Mb/s mode 800 Mb/s mode 400 Mb/s mode 200 Mb/s modeData Adjustment Resolution 10 ps 10 ps 10 ps 100 ps 100 psto Clock tSample [5] 0 to +4 ns -2.5 to +2/5 ns -2.5 to +2/5 ns -3.2 to +3.2 ns -3.5 to +3 nsAll vThreshold [6] 10 mV resolution 10 mV resolution 10 mV resolution 10 mV resolution 10 mV resolutionInputs -3 to +5 V -3 to +5 V -3 to +5 V -3 to +5 V -3 to +5 V* All specifications noted by an asterisk in the table are the performance standards against which the product is tested.[1] The analyzer can be configured to sample on the rising edge, the falling edge, or both edges of the clock. If both edges are used with a single ended clock input, take care to set theclock threshold accurately to avoid phase error.[2] Eye width and height are specified at the probe tip. Eye width as measured by eye finder in the analyzer may be less, and still sample reliably.[3] For each side of a differential signal.pSignalnSignalvHeightvHeight——0V——2X vHeight[4] The clock inputs in the E5378A and the E5382A may be connected differentially or single ended. Use the E5379A vHeight spec for clock channel(s) connected differentially.[5] Sample positions are independently adjustable for each data channel input. A negative sample position causes the input to be synchronously sampled by that amount before eachactive clock edge. A positive sample position causes the input to be synchronously sampled by that amount after each active clock edge. A sampling position of zero causes synchronoussampling coincident with each active clock edge.[6] Threshold applies to single-ended input signals. Thresholds are independently adjustable for the clock input of each pod and for each set of 16 data inputs for each pod. Threshold limitsapply to both the internal reference and to the external reference input on the E5378A.96

State/Timing Modules Specifications andCharacteristicsAgilent Technologies 16760ASupplemental Specifications* and Characteristics (continued)Synchronous state analysis 1.5 Gb/s mode 1.25 Gb/s mode 800 Mb/s mode 400 Mb/s mode 200 Mb/s modeMaximum data rate E5378A, E5379A probes: E5378A, E5379A probes: E5378A, E5379A, E5382A 400 Mb/s 200 Mb/son each channel 1.5 Gb/s 1.25 Gb/s probes: 800 Mb/sE5380A probe: 600 Mb/sMinimum clock interval, 667 ps 800 ps E5378A, E5379A probes: 2.5 ns 5 nsactive edge to active edge*1.25 nsE5380A probe: 1.67 nsMinimum state clock pulse N/A N/A E5378A, E5379A probes: 1.5 ns 1.5 nswidth with clock polarity600 psrising or fallingE5380A probe: 800 psClock periodicity Clock must be periodic Clock must be periodic Periodic or aperiodic Periodic or aperiodic Periodic or aperiodicNumber of clocks 1 1 1 1 1Clock polarity Both edges Both edges Rising, falling, or both Rising, falling, or both Rising, falling, or bothMinimum data pulse width 600 ps 750 ps E5378A, E5379A, E5382A 1.5 ns 1.5 nsprobes: 750 psE5380A probe: 1.5 nsNumber of channels [1]• With time tags 16 x (number of modules) - 16 x (number of modules) - 34 x (number of modules) - 34 x (number of modules) - 34 x (number of modules)8 8 16 16• Without time tags 16 x (number of modules) 16 x (number of modules) 34 x (number of modules) 34 x (number of modules) 34 x (number of modules)Maximum channels on a 80 (5 modules) 80 (5 modules) 170 (5 modules) 153 (5 modules) 170 (5 modules)single time base and triggerMaximum memory depth 128M samples 128M samples 64M samples 32M samples 32M samplesTime tag resolution 4 ns [2] 4 ns [2] 4 ns [2] 4 ns [2] 4 nsMaximum time count 17 seconds 17 seconds 17 seconds 17 seconds 17 secondsbetween statesTrigger resources 3 Patterns on each pod 3 Patterns on each pod 4 Patterns on each pod 8 Patterns evaluated as 16 Patterns evaluated asevaluated as =, ≠, >, , , , ,

State/Timing Modules Specifications andCharacteristicsAgilent Technologies 16760ASupplemental Specifications and Characteristics (continued)Synchronous state 1.5 Gb/s mode (only 1.25 Gb/s mode (only 800 Mb/s mode 400 Mb/s mode 200 Mb/s modeanalysis (continued) available with E5378A available with E5378Aand E5379A probes) and E5379A probes)Maximum trigger 2 2 4 16 16sequence levelsMaximum trigger 1.5 Gb/s 1.25 Gb/s 800 MHz 400 MHz 200 MHzsequencer speedStore qualification Default Default Default Default Default and persequence levelMaximum global counter N/A N/A N/A N/A 16,777,215Maximum occurrence N/A N/A N/A N/A 16,777,215counterMaximum pattern/range 32 bits [3] 32 bits [3] 32 bits [3] 32 bits [3] 32 bits [3]term widthTimer value range N/A N/A N/A N/A 100 ns to 4397 secondsTimer resolution N/A N/A N/A N/A 4 nsTimer accuracy N/A N/A N/A N/A ±(10 ns + 0.01% of value)Timer reset latency N/A N/A N/A N/A 65 nsData in to BNC port out 150 ns 150 ns 150 ns 150 ns 150 nslatencyFlag set/reset to evaluation N/A N/A N/A N/A 110 nslatency[1] In 1.25 Gb/s mode, only the even-numbered channels (0, 2, 4, etc.) are acquired.[2] The resolution of the hardware used to assign time tags is 4 ns. Times of intermediate states are calculated.[3] Maximum label width is 32 bits. Wider patterns can be created by “Anding” multiple labels together.Asynchronous Timing Analysis Conventional Timing Analysis Transitional Timing AnalysisMaximum timing analysis sample rate 800 MHz 400 MHzNumber of channels 34 x (number of modules) Sampling rates < 400 MHz: 34 x (number of modules)Sampling rates = 400 MHz:34 x (number of modules) - 17 [1]Maximum channels on a 170 (5 modules) 170 (5 modules)single time base and triggerSample period 1.25 ns 2.5 ns to 1 ms [1]Memory Depth 64 M Samples 32 M Samples [1][1] With all pods assigned in transitional/store qualified timing, minimum sample period is 5 ns and maximum memory depth is 16 M samples.98

State/Timing Modules Specifications andCharacteristicsAgilent Technologies 16760ASupplemental Specifications and Characteristics (continued)Asynchronous Timing Analysis Conventional Timing Analysis Transitional Timing Analysis(continued)Sample period accuracy ±(250 ps + 0.01% of sample period) ±(250 ps + 0.01% of sample period)Channel-to-channel skew < 1.5 ns < 1.5 nsTime interval accuracy ±[sample period + (channel-to-channel skew) + ±[sample period + (channel-to-channel skew) +(0.01% of time interval)] (0.01% of time interval)]Minimum data pulse width 1.5 ns for data capture 3.8 ns for data capture5.1 ns for trigger sequencing 5.1 ns for trigger sequencingMaximum trigger sequencer speed 200 MHz 200 MHzTrigger resources 16 Patterns evaluated as =, ≠, >, ,

State/Timing Modules Specifications andCharacteristicsAgilent Technologies 16760ASupplemental Specifications and Characteristics (continued)Eye scan mode 1.5 Gb/s mode 800 Mb/s modeMaximum clock rate 1.5 Gb/s 800 Mb/sSample position range relative +5ns to 10 ns -4 ns to +4 nsto clockSample (time) position resolution 12 ps 12 psSample position (time) accuracy +/- (50 ps + 0.01 * sample position) +/- (50 ps + 0.01 * sample position)Number of channels 16*(number of modules) 34*(number of modules)-1Input dynamic range -3.0 Vdc to +5.0 Vdc -3.0 Vdc to +5.0 VdcThreshold range -3.0 Vdc to +5.0 Vdc -3.0 Vdc to +5.0 VdcThreshold resolution 2 mV 2 mVThreshold accuracy +/-(30 mV + 1% of setting) +/-(30 mV + 1% of setting)Equivalent rise time [1] 150 ps 150 psEquivalent bandwidth [1] 2.33 GHz 2.33 GHzMinimum detectable pulse width 500 ps 750 psat minimum signal amplitude [1]Jitter 10 ps RMS 10 ps RMSNoise floor 25 mV p-p 25 mV p-pChannel-to-channel skew, maximum 100 ps 100 psbetween any two channels[1] E5378A, E5379A, and E5382A probes only.Qualified eye scan modeIn the qualified eye scan mode, asingle qualifier input defines whatclock cycles are to be acquired andwhat cycles are to be ignored in eyescan acquisition.Qualified eye scan is supported inthe 16760A in 800 Mb/s eye scanmode only. Qualified eye scan isonly available for double-edged clock(double-data-rate).100Channels availableThe following channels are notavailable for qualified eye scanmeasurements.Master module, Pod 1Master module, Pod 2, Bit 0, Bit 14,Bit 1, Bit 15, Bit 2, K-clock(the qualifier input itself).All channels on all boards other thanthe master board are available forqualified eye scans.TimingThe analyzer samples the qualificationsignal at the beginning of eachclock cycle (i.e. at the first of eachpair of data transfers). The analyzercan be configured to treat either therising edge or the falling edge of theclock as the first edge of each clockcycle. The qualifier should remainstable for the entire duration ofeach burst.The qualifier must be pipelined(delayed) by one clock cycle beforetransmittal to the analyzer.

Oscilloscope Modules Specifications andCharacteristics16534A Specifications*Bandwidthdc offset accuracydc voltage measurement accuracyTime interval measurementaccuracy at maximum sampling rate,on a single scope card, on a singleacquisitionTrigger sensitivity (See notes)• dc to 50 MHz• 50 MHz to 500 MHzdc to 500 MHz±(1% of offset + 2% of full scale)±(1.5% of full scale + offset accuracy)±[(0.005% of D T) + (2E–6 x delay setting) + 100 ps]• 0.06 full scale• 0.13 full scaleInput resistance 1 MΩ ±1% 50 Ω ±1%* Specifications refer to the input to the BNC connectorNotes:• Specifications apply only within ± 10° C of the temperature at which the most recent calibration was performed.• Specifications apply only after operational accuracy calibration is performed in the frame in which theoscilloscope module is installed.• Display magnification is used below 56 mV full scale. For sensitivities from 16 mV to 56 mV full scale, full scale isdefined as 56 mV.CharacteristicsGeneralMaximum sampling rateNumber of channelsWaveform record length2 GSa/s• 2 to 8 using the sametime base and trigger.• Up to 10 channels may be installed in a single16700 frame, or up to 20 in a single system using a16701 expansion frame.32768 points101

Oscilloscope Modules Specifications andCharacteristics16534A Characteristics*Vertical (Voltage)Vertical sensitivity rangeVertical resolutionRise time (calculated from bandwidth)dc gain accuracydc offset rangeVertical sensitivity• 16 mV full scale to 400 mV full scale• 400 mV full scale to 2.0 V full scale• 2.0 V full scale to 10 V full scale• 10 V full scale to 40 V full scaleProbe attenuation16 mV full scale to 40 V full scale8 bits full scale700 ps±(1.25% of full scale + 0.08% per °C difference fromcalibration temperature)Offset range• ±2 V• ±10 V• ±50 V• ±250 VAny ratio from 1:1E-9 to 1:1E+6Channel-to-channel isolation (with channel sensitivities equal)• dc–50 MHz• 40 dB• 50 MHz–500 MHz• 30 dBMaximum safe input voltage• 1 MΩ• 50 Ω• ±250 V dc + peak ac (

Oscilloscope Modules Specifications andCharacteristics16534A CharacteristicsHorizontal (Time)Time base rangesTime base resolutionDelay range• pretrigger• posttriggerTime interval measurement accuracyforsampling rates other than maximum,for bandwidth-limited signals [signalrise time > 1.4/(sampling rate)], on asingle card, on a single acquisitionTime interval measurement accuracyfor 2, 3, or 4 Agilent 16533As or 16534Asoperating on a single time base, formeasurements made between channelson different cards, at maximumsampling rate0.5 ns/div to 5 s/div10 ps• -32 K x sample period• 320 ms or 1.6E7 x sample period, whichever is greater±{(0.005% of ∆ T) + (2E–6 x delay setting)+ [0.15/(sample rate)]}± [(0.005% of ∆T) + (2E–6 x delay setting) + 300 psTriggerTrigger level range (See notes)Trigger modes• Immediate• Edge• Pattern• Auto condition• Events delay• Intermodule±1.5 x full scale from center of screen• Triggers immediately after arming condition is met• Triggers on rising or falling edge on channel 1 orchannel 2• Triggers on entering or exiting a specified patternacross both channels• Self-triggers if trigger is not satisfied withinapproximately 50 ms after arming• The trigger can be set to occur on the nth occurrenceof an edge or pattern, n ≤ 32000• Arms another measurement module or activates theport out BNC connector when the trigger condition ismetNotes:• Specifications apply only within ± 10° C of the temperature at which the most recent calibration was performed.• Specifications apply only after operational accuracy calibration is performed in the frame in which theoscilloscope module is installed.• Display magnification is used below 56 mV full scale. For sensitivities from 16 mV to 56 mV full scale, full scale isdefined as 56 mV.103

Pattern Generation Modules Specificationsand Characteristics16720A Pattern Generator CharacteristicsMaximum memory depth16 MVectorsNumber of output channels at ≤ 300 MHz clock 24Number of output channels at ≤ 180 MHz clock 48Number of output channels at ≤ 200 MHz clock 24Number of output channels at ≤ 100 MHz clock 48Number of different macros 100Maximum number of lines in a macro 1024Maximum number of parameters in a macro 10Maximum number of macro invocations 1000Maximum loop count in a repeat loop 20000Maximum number of repeat loop invocations 1000Maximum number of "Wait" event patterns 4Number of input lines to define a pattern 3Maximum number of modules in a system 5Maximum width of a vector (in a 5 module system)Maximum width of a label240 bits32 bitsMaximum number of labels 126Maximum number of vectors in binary format16 MVectorsMinimum number of vectors in binary format 4096Lead Set CharacteristicsAgilent 10474A 8-channelprobe lead setAgilent 10347A 8-channelprobe lead setAgilent 10498A 8-channelprobe lead setProvides most cost effective lead set for the 16522A and16720A clock and data pods. Grabbers are not included.Lead wire length is 12 inches.Provides 50 Ω coaxial lead set for unterminated signals,required for 10465A ECL Data Pod (unterminated).Grabbers are not included.Provides most cost effective lead set for the 16522A and16720A clock and data pods. Grabbers are not included.Lead wire length is 6 inches.104

Pattern Generation Modules Specificationsand CharacteristicsData Pod CharacteristicsNote: Data Pod output parametrics depend on the output driver and the impedance load of the targetsystem. Check the device data book for the specific drivers listed for each pod.Agilent 10461A TTL Data PodOutput typeMaximum clockSkew [1]Recommended lead set10H125 with 100 Ω series200 MHztypical < 2 ns; worst case = 4 nsAgilent 10474AECL/TTL10H125100 ΩAgilent 10462A 3-State TTL/CMOS Data PodOutput type 74ACT11244 with 100 Ω series; 10H125 on non 3-state channel 7 [2]3-state enableMaximum clockSkew [1]Recommended lead setnegative true, 100 KΩ to GND, enabled on no connect100 MHztypical < 4 ns; worst case = 12 nsAgilent 10474A74ACT11244100 ΩAgilent 10464A ECL Data Pod (terminated)Output typeMaximum clockSkew [1]Recommended lead set10H115 with 330 Ω pulldown, 47 Ω series300 MHztypical < 1 ns; worst case = 2 nsAgilent 10474A10H115348 Ω– 5.2 V42 Ω105

Pattern Generation Modules Specificationsand CharacteristicsAgilent 10465A ECL Data Pod (unterminated)Output typeMaximum clockSkew [1]Recommended lead set10H115 (no termination)300 MHztypical < 1 ns; worst case = 2 nsAgilent 10347A10H115Agilent 10466A 3-State TTL/3.3 volt Data PodOutput type 74LVT244 with 100 Ω series; 10H125 on non 3-state channel 7 [2]3-state enableMaximum clockSkew [1]Recommended lead setnegative true, 100 KΩ to GND, enabled on no connect200 MHztypical < 3 ns; worst case = 7 nsAgilent 10474A100 Ω74LVT244[1] Typical skew measurements made at pod connector with approximately 10 pF/50 KΩ load to GND; worst caseskew numbers are a calculation of worst case conditions through circuits. Both numbers apply to any channelwithin a single or multiple module system.[2] Channel 7 on the 3-state pods has been brought out in parallel as a non 3-state signal. By looping this output backinto the 3-state enable line, the channel can be used as a 3-state enable.106

Pattern Generation Modules Specificationsand CharacteristicsAgilent 10469A 5 volt PECL Data PodOutput typeMaximum clockSkew [1]Recommended lead set100EL90 (5V) with 348 ohm pulldown to ground and 42 ohm in series300 MHztypical < 500 ps; worst case = 1 nsAgilent 10498A100EL9042 Ω348 ΩAgilent 10471A 3.3 volt LVPECL Data PodOutput typeMaximum clockSkew [1]Recommended lead set100LVEL90 (3.3V) with 215 ohm pulldown to ground and42 ohm in series300 MHztypical < 500 ps; worst case = 1 nsAgilent 10498A100LVEL9042 Ω215 ΩAgilent 10473A 3-State 2.5 Volt Data PodOutput type3-state enableMaximum clockSkew [1]Recommended lead set74AVC16244negative true, 38 KΩ to GND, enabled on no connect300 MHztypical < 1.5 ns; worst case = 2 nsAgilent 10498A74AVC16244[1] Typical skew measurements made at pod connector with approximately 10 pF/50 KΩ load to GND; worst caseskew numbers are a calculation of worst case conditions through circuits. Both numbers apply to any channelwithin a single or multiple module system.[2] Channel 7 on the 3-state pods has been brought out in parallel as a non 3-state signal. By looping this output backinto the 3-state enable line, the channel can be used as a 3-state enable.107

Pattern Generation Modules Specificationsand CharacteristicsAgilent 10476A 3-State 1.8 Volt Data PodOutput type3-state enableMaximum clockSkew [1]Recommended lead set74AVC16244negative true, 38 KΩ to GND, enabled on no connect300 MHztypical < 1.5 ns; worst case = 2 nsAgilent 10498A74AVC16244Agilent 10483A 3-State 3.3 Volt Data PodOutput type3-state enableMaximum clockSkew [1]Recommended lead set74AVC16244negative true, 38 KΩ to GND, enabled on no connect300 MHztypical < 1.5 ns; worst case = 2 nsAgilent 10498A74AVC16244Agilent E8141A LVDS Data PodOutput type3-state enableMaximum clockSkewRecommended lead set:Recommended lead set65LVDS389 (LVDS data lines)10H125 (TTL non-3-state channel 7)positive true TTL; no connect=enabled300 MHztypical < 1 ns; worst case = 2 nsE8142AAgilent 10498A65LVDS389ENABLE°LVDS DATA OUT3.3 V10 KΩ3-STATE IN TTL[1] Typical skew measurements made at pod connector with approximately 10 pF/50 KΩ load to GND; worst caseskew numbers are a calculation of worst case conditions through circuits. Both numbers apply to any channelwithin a single or multiple module system.108

Pattern Generation Modules Specificationsand CharacteristicsData Cable Characteristics Without a Data PodThe Agilent 16720A and 16522A data cables without a data pod provide an ECL terminated (1 KΩ to–5.2V) differential signal (from a type 10E156 or 10E154 driver). These are usable when received bya differential receiver, preferably with a 100 Ω termination across the lines. These signals shouldnot be used single ended due to the slow fall time and shifted voltage threshold (they are not ECLcompatible).16720A–3.25 V470 Ω10E156or10E154DifferentialOutput470 Ω–3.25 V16522A–5.2 V1 kΩ10E156or10E154DifferentialOutput1 kΩ–5.2 V109

Pattern Generation Modules Specificationsand CharacteristicsClock Cable Characteristics Without a Clock PodThe Agilent 16720A and 16522A clock cables without a clock pod provide an ECL terminated(1 KΩ to –5.2V) differential signal (from a type 10E164 driver). These are usable when received by adifferential receiver, preferably with a 100 Ω termination across the lines. These signals should not beused single ended due to the slow fall time and shifted voltage threshold (they are not ECL compatible).710E116100 Ω Clock In811, 13, 1510H125100 Ω Wait 1, 2, 3 IN12, 14, 16–3.25 V215 Ω10E164Clock Out215 Ω–3.25 V110

Pattern Generation Modules Specificationsand CharacteristicsClock Pod Characteristics10460A TTL Clock PodClock output typeClock output rate10H125 with 47 Ω series; true & inverted100 MHz maximumClock out delay approximately 8 ns total in 14 steps (16720Aonly); 11 ns maximum in 9 steps (16522Aonly)Clock input typeClock input rateTTL – 10H124dc to 100 MHzPattern input type TTL – 10H124 (no connect is logic 1)Clock-in to clock-outapproximately 30 ns10H12547ΩCLKoutPattern-in to recognitionapproximately 15 ns + 1 clk periodRecommended lead setAgilent 10474A10H124WAITCLKin10463A ECL Clock PodClock output type10H116 differential unterminated; and differentialwith 330 Ω to –5.2V and 47 Ω seriesClock output rate300 MHz maximumClock out delay approximately 8 ns total in 14 steps (16720Aonly); 11 ns maximum in 9 steps (16522Aonly)Clock input typeECL – 10H116 with 50 KΩ to –5.2vClock input ratedc to 300 MHzPattern input typeECL – 10H116 with 50 KΩ (no connect islogic 0)10H116CLKinClock-in to clock-outapproximately 30 nsVBB–5.2 V50 kΩPattern-in to recognitionRecommended lead setapproximately 15 ns + 1 clk periodAgilent 10474A–5.2 V330 Ω10H11647 Ω CLKout111

Pattern Generation Modules Specificationsand Characteristics10468A 5 volt PECL Clock PodClock output typeClock output rate100EL90 (5V) with 348 ohm pulldown toground and 42 ohm in series300 MHz maximumClock out delay approximately 8 ns total in 14 steps (16720Aonly); 11 ns maximum in 9 steps (16522Aonly)Clock input type100EL91 PECL (5V), no terminationClock input ratedc to 300 MHzPattern input type100EL91 PECL (5V), no termination (noconnect is logic 0)100EL9042 ΩCLKoutClock-in to clock-outapproximately 30 ns348 ΩPattern-in to recognitionapproximately 15 ns + 1 clk periodRecommended lead setAgilent 10498A100EL91CLKin10470A 3.3 volt LVPECL Clock PodClock output typeClock output rate100LVEL90 (3.3V) with 215 ohm pulldown toground and 42 ohm in series300 MHz maximumClock out delay approximately 8 ns total in 14 steps (16720Aonly); 11 ns maximum in 9 steps (16522Aonly)Clock input type100LVEL91 LVPECL (3.3V), no terminationClock input ratedc to 300 MHzPattern input type100LVEL91 LVPECL (3.3V), no termination(no connect is logic 0)100LVEL9042 ΩCLKoutClock-in to clock-outapproximately 30 ns215 ΩPattern-in to recognitionapproximately 15 ns + 1 clk periodRecommended lead setAgilent 10498A100LVEL91CLKin112

Pattern Generation Modules Specificationsand Characteristics10472A 2.5 volt Clock PodClock output typeClock output rate74AVC16244200 MHz maximumClock out delay approximately 8 ns total in 14 steps (16720Aonly); 11 ns maximum in 9 steps (16522Aonly)Clock input typeClock input rate74AVC16244 (3.6V max)dc to 200 MHzPattern input type 74AVC16244 (3.6V max; no connect is logic 0)Clock-in to clock-outapproximately 30 ns74AVC16244CLKoutPattern-in to recognitionapproximately 15 ns + 1 clk periodRecommended lead setAgilent 10498A74AVC16244WAITCLKin10475A 1.8 volt Clock PodClock output type74AVC16244Clock output rate200 MHz maximumClock out delay approximately 8 ns total in 14 steps (16720Aonly); 11 ns maximum in 9 steps (16522Aonly)Clock input typeClock input rate74AVC16244 (3.6V max)dc to 200 MHzPattern input type 74AVC16244 (3.6V max; no connect is logic 0)Clock-in to clock-out approximately 30 nsPattern-in to recognition approximately 15 ns + 1 clk period74AVC16244CLKoutRecommended lead setAgilent 10498A74AVC16244WAITCLKin113

Pattern Generation Modules Specificationsand Characteristics10477A 3.3 volt Clock PodClock output typeClock output rate74AVC16244200 MHz maximumClock out delay approximately 8 ns total in 14 steps (16720Aonly); 11 ns maximum in 9 steps (16522Aonly)Clock input type74AVC16244 (3.6V max)Clock input ratedc to 200 MHzPattern input type 74AVC16244 (3.6V max; no connect is logic 0)Clock-in to clock-out approximately 30 ns74AVC16244CLKoutPattern-in to recognitionRecommended lead setapproximately 15 ns + 1 clk periodAgilent 10498A74AVC16244WAITCLKinE8140A LVDS Clock PodClock output type65LVDS179 (LVDS) and 10H125 (TTL)Clock output rate200 MHz maximum (LVDS and TTL)Clock out delayapproximately 8 ns total in 14 stepsClock input type65LVDS179 (LVDS with 100 ohm)Clock input ratedc to 150 MHz (LVDS)Pattern input type 10H124 (TTL) (no connect = logic 1)Clock-in to clock-outPattern-in to recognitionRecommended lead setapproximately 30 nsapproximately 15 ns + 1 clk periodAgilent 10498A10H125CLK OUT TTL65LBDS179°CLK OUT LVDSCLK IN LVDS65LVDS179100 Ω°CLK IN LVDS10H124WAIT IN TTL114

Trade-In, Trade-UpAdvance to the Latest Technology with Agilent’s “Trade-Up” ProgramComprehensive Economical Convenient• Purchase from an extensive • Upgrade for less • Simply call your local Agilentlist of Agilent test and • Stretch your test sales officemeasurement products equipment budget • Mention Agilent Promotion 4.65• Trade in a wide variety of • Reduce support costs for • Let us evaluate your savingstest equipment for aging equipment opportunitiessubstantial creditHow to Upgrade for Less:Purchase... Trade in... Receive...Eligible New Agilent Product Similar[1] Agilent Product Agilent’s “buy-back” price[2][1] A “similar” product is considered to be part of the same product family (for example, oscilloscope foroscilloscope) with comparable functionality and application.[2] Agilent’s “buy-back” price varies based on the model, option configuration, and age of the trade-in product.Terms and Conditions• This offer is void where prohibited.• This offer applies to end-user customersonly. Rental companiesand equipment brokers are excluded.• This offer is applicable to thereturn of fewer than 10 productsor $100,000 (U.S. dollars) in tradeincredit.• The total trade-in credit may notexceed 100% of the cost of the eligiblenew product(s). Any credit inexcess of that amount may not beapplied toward a later purchase.• Trade-in credit amounts and producteligibility are subject to changeat any time without advancenotice.• Refurbished Agilent equipment isnot eligible for purchase underthis program.• All trade-in products must be inworking condition and have nointerior, exterior, or performancemodifications.• To ensure timely release of credit,all trade-in products must bereturned to Agilent within 30 daysafter receipt of the newly purchasedAgilent product.• Customer is responsible for allcosts associated with shipping thetrade-in product(s) to Agilent.• Additional requirements mayapply. Please contact yourlocal Agilent sales office forinformation.115

Ordering InformationMainframes and Mainframe AccessoriesProduct Number Description Includes16700B Modular mainframe with five measurement • One DIN keyboardmodule slots and one emulation or multiframe • One three-button DIN mousemodule slot • One ten-conductor, flying lead cable for target control port• Training kit• One internal CD ROM drive• One internal 3.5" floppy drive16702B Modular frame with built-in 800x600 LCD display Same as 16700B plus:with touchscreen. Includes five measurement • 12.1” touchscreen displayslots and one emulation or multiframe • Display knobsmodule slot • Dedicated hot keys16701B Expansion frame with five measurement module 1 ft. and 3 ft. interface cablesslots and two emulation module slots. Requires a16700A/B or 16702A/B1184A Testmobile 4 wheeled equipment cart specifically designed Drawer, keyboard tray, mouse tray, strap forto carry the 16700 Series logic analyzer,stabilizing monitorexpansion frame, and monitorMainframe OptionsOption Description 16700B or 16700A or 16701B 16701ANumber 16702B 16702A001 Add 17-inch 1280x1024 monitor √ √003 Performance option. Up to 256 MBytes total system √ √RAM, 4 MBytes total video RAM. (256 MB) (160 MB)004* Add external CD-ROM drive and cable √008 External, auxiliary 18 GByte hard disk drive √ √009 Removable internal hard disk √ √012 Multiframe option √0B3 Add service guide √1CM Add rack-mount kit (all but 16702B) √ √ √ √AXC Equipment shelf (16702B only) √ABJ Japanese localization √W17 Convert standard warranty to one year on-site warranty √ √ √ √W30 Extend standard warranty to three year return-to-Agilent warranty √ √ √ √W50 Extend standard warranty to five year return-to-Agilent warranty √ √ √ √* Built-in CD-ROM drive standard on 16700B Series116

Ordering InformationE5850A Logic Analyzer - Infiniium Oscilloscope Correlation Time FixtureProduct Number Description IncludesE5850A Logic analyzer - Infiniium oscilloscope time All BNC cables needed to connect to logic analyzer andcorrelation fixtureoscilloscopeAgilent 1184A TestmobileThe Agilent 1184A testmobile givesyou a convenient means of organizingand transporting your logic analysissystem mainframes and accessories.The testmobile includes the following:• Drawer for accessories (probes,cables, power cords)• Keyboard tray with adjustable tiltand height• Mouse extension on keyboardtray for either right or left handoperation• Locking casters for stability onuneven surfaces• Strap to stabilize the monitor• Load limits: Top tray: 68.2 kg(150.0 lb.) Lower tray: 68.2 kg(150.0 lb.) Total: 136.4 kg(300.0 lb.)WeightFigure 7.1. Agilent 1184A testmobile cart.Max Net Max Shipping1184A 48.0 kg (106.0 lb) 59.0 kg (130.0 lbs)584.2(23.0)243.8(9.6)774.7(30.5)469.9(18.5)190.5(7.5)772.2(30.4)482.6(19.0)254(10.0)866.1(34.1)652.8(25.7)Dimensions: mm (inches)594.4(23.4)116.8(4.6)Figure 7.2. Agilent 1184A testmobile cart dimensions.117

Ordering InformationMeasurement Module Compatibility TableMeasurement Model Description 16700 16600A 16500C* 16500A/B*Module Category Number Series SeriesState and Timing 16510A* 25 MHz State; 100 MHz Timing; 1 K memory depth √ √* Discontinued products.11816510B* 35 MHz State; 100 MHz Timing; 1 K memory depth √ √16540A/16541A* 100 MHz State; 100 MHz Timing; 4 K memory depth √ √16540D/16541D* 100 MHz State; 100 MHz Timing; 16 K memory depth √ √16542A* 100 MHz State; 100 MHz Timing; 1 M memory depth √ √16550A* 100 MHz State; 500 MHz Timing; 4/8 K memory depth √ √ √ √16554A* 100 MHz State; 250 MHz Timing; 512 K/1 M memory depth √ √ √16555A/16555D* 110 MHz State; 500 MHz Timing; 2/4 M memory depth √ √ √16556A/16556D* 100 MHz State; 400 MHz Timing; 2/4 M memory depth √ √ √16557D 140 MHz State; 500 MHz Timing; 2/4 M memory depth √ √ √16710A 100 MHz State; 500 MHz Timing; 8 K memory depth √ √16711A 100 MHz State; 500 MHz Timing; 32 K memory depth √ √16712A 100 MHz State; 500 MHz Timing; 128 K memory depth √ √16715A 167 MHz State; 667 MHz Timing; 2/4 M memory depth √16716A 167 MHz State; 667 MHz Timing; 2 GHz Timing Zoom; √512 K/1 M memory depth16717A 333 MHz State; 667 MHz Timing; 2 GHz Timing Zoom; √2/4 M memory depth16718A* 333 MHz State; 667 MHz Timing; 2 GHz Timing Zoom; √8/16 M memory depth16719A* 333 MHz State; 667 MHz Timing; 2 GHz Timing Zoom; √32/64 M memory depth16740A 200 MHz State; 800 MHz Timing; 2 GHz Timing Zoom √2/1 M memory depth16741A 200 MHz State; 800 MHz Timing; 2 GHz Timing Zoom √8/4 M memory depth16742A 200 MHz State; 800 MHz Timing; 2 GHz Timing Zoom √32/16 M memory depth16750A 400 MHz State; 800 MHz Timing; 2 GHz Timing Zoom; √4/8 M memory depth16751A 400 MHz State; 800 MHz Timing; 2 GHz Timing Zoom; √16/32 M memory depth16752A 400 MHz State; 800 MHz Timing; 2 GHz Timing Zoom; √32/64 M memory depth16760A 1.25 Gb/s State; 800 MHz Timing; 34 channel; √64 M memory depth

Ordering InformationMeasurement Module Compatibility Table (continued)Measurement Model Description 16700 16600 16500C* 16500A/B*Module Category Number Series SeriesOscilloscope 16530A/16531A* 2 Channel; 100 MHz Bandwidth; 400 MSa/s; √ √4 K memory depth16532A* 2 Channel; 250 MHz Bandwidth; 1 GSa/s; √ √8 K memory depth16533A* 2 Channel; 250 MHz Bandwidth; 1 GSa/s; √ √ √32 K memory depth16534A 2 Channel; 500 MHz Bandwidth; 2 GSa/s; √ √ √32 K memory depthHigh Speed Timing 16515A/16516A* 1 GHz Timing; 8 K memory depth √ √16517A/16518A 4 GHz Timing; 1GHz Synchronous State; √ √ √ √64 K memory depthPattern Generator 16520A/16521A* 50 MV/s; 4 K memory; 12 Channel √ √16522A* 200 MV/s; 258 K memory; 100 MHz in 40 Channel; √ √ √200 MHz in 20 Channel16720A 300 MV/s; 180 MHz in 48 Channel, 16 MV memory; √300 MHz in 24 Channel, 8 MV memoryEmulation E5901A Emulation Module Products √ √* Discontinued products.E5901B Emulation Module Products √Options for Agilent 16700 Series State/Timing ModulesAgilent Module Product Numbers Option Option Description16517A/16518A 0B3 Add service manual16710A 1BP MIL-STD-45662A calibration with test data16711A W17 Convert standard warranty to one-year on-site warranty16712A16715A16716A16717A16750A16751A16752A16760A 010 add one E5378A, single-ended, 34-channel probe011 add one E5379A, differential, 17-channel probe012 add one E5380A, Mictor-compatible probe013 add one E5382A, single-ended flying lead probe set0B3 Add service manual (available April 2001)A6J MIL-STD-45662A calibration with test data (available April 2001)W17Convert standard warranty to one-year on-site warranty119

Ordering InformationAgilent Wedge Probe AdaptersIC Leg Spacing Number of Quantity of Probe ModelSignals Probes Shipped Number0.5 mm 3 1 E2613A0.5 mm 3 2 E2613B0.5 mm 8 1 E2614A0.5 mm 16 1 E2643A0.65 mm 3 1 E2615A0.65 mm 3 2 E2615B0.65 mm 8 1 E2616A0.65 mm 16 1 E26144AAgilent Elastomeric Probing SolutionsPackage Type IC Leg Spacing Probe Model Number240-pin PQFP/CQFP 0.5 mm E5363A Probe. E5371A 1/4 flexible cable208-pin PQFP/CQFP 0.5 mm E5374A Probe. E5371A 1/4 flexible cable176-pin PQFP 0.5 mm E5348A Probe. E5349A 1/4 flexible cable160-pin QFP 0.5 mm E5377A Probe. E5349A 1/4 flexible cable160-pin PQFP/CQFP 0.65 mm E5373A Probe. E5349A 1/4 flexible cable144-pin PQFP/CQFP 0.65 mm E5361A Probe. E5340A 1/4 flexible cable144-pin TQFP 0.65 mm E5336A Probe. E5340A 1/4 flexible cable120

Ordering InformationOptions and Accessories for Agilent 16534A Oscilloscope ModulesAgilent OptionOption Description• 001 • Add one Agilent 1145A, dual, active 750 MHz probe• ABJ • Japanese user's reference• 0B0 • Delete manuals• 1BP • MIL-STD 45662A calibration with test data• 0B3 • Add service manual• 0BF • Add programming manual set for a 16500 (not required for a 16700)• W17 • Convert standard warranty to one-year-on-site warranty• W03 • Convert standard warranty to 90-day-on-site warrantyAgilent Model Number1144AAccessory Description800 MHz active probe (power for two Agilent 1144A active probes is provided by theAgilent 16533A and 16534A) (requires 01144-61604 power splitter to operate two 1144As)01144-61604 Power splitter. Allows operation of two Agilent 1144A active probes from one Agilent 16533A or 16534A1145A 750-MHz dual, active probe (power for Agilent 1145A active probes is provided by the Agilent 16533A and 16534A)1141A1142A10442A10443A200 MHz differential probe (requires an Agilent 1142A power supply)Probe power supply10:1, 500-ohm 1.2pF oscilloscope probe20:1, 1000-ohm, 1.2pF oscilloscope probeOptions for Agilent 16720A Pattern Generator ModulesAgilent OptionOption Description• 011 • TTL clock pod and 6” lead set (10460A and 10498A)• 013 • 3-state TTL/CMOS data pod and 6” lead set (10462A and 10498A)• 014 • TTL data pod and 6” lead set (10461A and 10498A)• 015 • 2.5 V clock pod and 6” lead set (10472A and 10498A)• 016 • 2.5 V 3-state data pod and 6” lead set (10473A and 10498A)• 017 • 3.3 V clock pod and 6” lead set (10477A and 10498A)• 018 • 3-state TTL/3.3 V data pod and 6” lead set (10483A and 10498A)• 021 • ECL clock pod and 6” lead set (10463A and 10498A)• 022 • ECL terminated pod and 6” lead set (10464A and 10498A)• 023 • ECL unterminated pod and 50 Ω shield coaxial lead set (10465A and 10347A)• 031 • 5 V PECL clock pod and 6” lead set (10468A and 10498A)• 032 • 5 V PECL data pod and 6” lead set (10469A and 10498A)• 033 • 3.3 V LVPECL clock pod and 6” lead set (10470A and 10498A)• 034 • 3.3 V LVPECL data pod and 6” lead set (10471A and 10498A)• 041 • 1.8 V clock pod and 6” lead set (10475 and 10498A)• 042 • 1.8 V 3-state data pod and 6” lead set (10476 and 10498A)• 051 • LVDS clock pod and 6” LVDS lead set (E8140A and E8142A)• 052 • LVDS data pod and 6” LVDS lead set (E8141A and E8142A)• 0B3 • Add service manual• W17 • Convert to one-year on-site warranty• W30 • 3 years return for repair service• W50 • 5 years return for repair service121

Ordering InformationAccessories for Agilent 16720A Pattern Generator ModulesAccessoriesModel NumberDescriptionAccessoriesModel NumberDescription10460ATTL clock pod10476A3-state 1.8 volt data pod10461ATTL data pod10477A3.3 volt clock pod10462A3-state TTL/CMOS data pod10483A3-state TTL/3.3 volt data pod10463A10463A ECL clock pod10498A8-channel probe lead set, 6" long10464AECL data pod (terminated)10347A8-channel 50-ohm shielded coaxial probe lead set10465A10466AECL data pod (unterminated)3-state TTL/3.3V data pod5090-4356 Grabbers, surface mount, package of 205959-0288 Grabbers, through hole, package of 2010468A5 volt PECL clock pod10211AIC probe clip, 24-pin dual in-line package10469A5 volt PECL data pod10024AIC probe clip, 16 pin dual in-line package10470A10471A3.3 volt LVPECL clock pod3.3 volt LVPECL data podE2421A SOIC clip adapter test kit (Pomona 5514)E2422A Quad clip adapter test kit (Pomona 5515)10472A2.5 volt clock podE8140ALVDS clock pod10473A3-state 2.5 volt data podE8141ALVDS data pod10474A8-channel probe lead set, 12" longE8142ALVDS lead set10475A1.8 volt clock podProduct Numbers and Option(s) for Agilent 16700 SeriesPost-Processing Tool SetsProduct or Option NumberB4600BB4601BB4605BB4620BB4640BDescription• System Performance Analysis (SPA) Tool Set• Serial Analysis Tool Set• Tool Development Kit• Source Correlation Tool Set• Data Communications Tool SetAvailable for all Tool Sets#0D4 Do not install tool set (instructs factory to ship tool setseparately from any 16700 Series system on the order)122

Third-Party SolutionsOur solutions partners offer a widearray of accessory products for theAgilent Technologies logic analysissystems. Agilent's solution partnersoffer complementary products coveringprobing clips, specialized analysisprobes for over 200 microprocessors,and software tools for ASIC emulationand test system design.See the Processor and Bus SupportFor Agilent Technologies LogicAnalyzers (p/n 5966-4365) documentfor contact information concerningthese vendors.Solutions Partner Application Focus Contact InformationAdvanced Logic Design (ALD) Product design services (digital) www.ald.comAptix ASIC emulation www.aptix.comJM Engineering (JME) Probing (solutions for www.jmecorp.comSMT parts)American Arium Intel emulators and probes www.arium.comAdvanced RISC Machines Microprocessor core IP www.arm.com(ARM)CAD-UL Software programming tools www.cadul.comCorelis Analysis probes for various www.corelis.commicroprocessors and busesDiagonal Manufacturing test suite www.diagonal.comsoftwareEmulation Technologies (ET) Probing www.emulation.comEurope Technologies Embedded system design www.europe-technologies.comtools and servicesFuturePlus Systems Analysis probes for computer www.futureplus.combusesGreen Hills Software, Inc Debugger and compiler www.ghs.com(GHS)software for MotorolamicroprocessorsIronwood High-density VLSI www.ironwoodelectronics.cominterconnect solutionsLital Electronics, Inc. Mil-spec computer boards www.lital.comMobile Media Research PCMCIA focused development www.mobmedres.comtoolsMicrotec (Mentor Graphics Debuggers and compilers www.mentor.com/embeddedEmbedded Software Division)Pomona Electronics Supplier of accessories for www.pomonaelectronics.comelectronic test instrumentsDIAB-SDS Debuggers, compilers www.diabsds.comSkyline Probing and manufacturing phone only: 719-390-9425servicesSynaptiCAD Waveform simulation www.syncad.comanalysis softwareWindRiver Embedded RTOS www.windriver.comdevelopment tools123

Support, Warranty and Related LiteratureSupport and ServicesAgilent's support services complementyour logic analysis system toprovide a complete solution to yourdigital design and debug problems.By taking advantage of Agilent'sexpertise you can concentrate onyour particular design projects andapplications, rather than your debugtools, resulting in increased productivity.WarrantyAgilent hardware products are warrantedagainst defects in materialsand workmanship for a period of oneyear from date of shipment. Somenewly manufactured Agilent productsmay contain remanufactured parts,which are equivalent to new in performance.If you send us a notice ofsuch defects during the warrantyperiod, we will either repair orreplace hardware products that proveto be defective.Agilent software and firmware productsthat are designated by Agilentfor use with a hardware product arewarranted for a period of one yearfrom date of shipment to executetheir programming instructions whenproperly installed. If you send usnotice of defects in materials orworkmanship during the warrantyperiod, we will repair or replacethese products, so long as the defectdoes not result from buyer suppliedhardware or interfacing. Thewarranty period is controlled by thewarranty statement included withthe product and begins on the dateof shipment.Related LiteraturePublication Title Publication Type Publication NumberProcessor and Bus Support For Configuration Guide 5966-4365EAgilent Technologies Logic AnalyzersProbing Solutions for Product Overview 5968-4632EAgilent Technologies Logic Analysis SystemsEmulation and Analysis Solutions for Product Overview 5966-2866Ethe Motorola MPC 8XX MicroprocessorsEmulation and Analysis Solutions for Product Overview 5966-2868Ethe Motorola/IBM PowerPC 6XX MicroprocessorsEmulation and Analysis Solutions for the Product Overview 5966-2867EMotorola/IBM Power PC 740/750 MicroprocessorsAgilent E2487C Analysis Probe & Agilent E2492B/C/E Product Overview 5968-2421EProbe Adapter for Intel Celeron Pentium II/III andPentium II/III Xeon ProcessorsEmulation and Analysis Solutions for Product Overview 5966-3442EARM7 and ARM9 Microprocessors124

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