Design Low Power 32-Bit Barrel Shifter using Efficient Charge ...

International Journal of Engineering and Advanced Technology (IJEAT)ISSN: 2249 – 8958, Volume-2, Issue-3, February 2013Design Low Power 32-Bit Barrel shifter usingEfficient Charge Recovery LogicShweta Chawla, Ramanand Harijan, Harpal singhAbstract— Today power dissipation has become the mainconcern as the circuit size become larger and larger. Especially inthis paper we presented the reduction of the power dissipationwhich shows an increasing growth as the technology is scaleddown. Various theories have been formulated regarding thisproblem. Out of which Adiabatic Logic is gaining much attentionbecause of its exemplary results. By adiabatic technique, powerdissipation in transistors can be minimized as well as energystored in load capacitance can be reused instead of dissipation asheat. In these circuits we can reduce the energy dissipation duringswitching process as well as reuse the energy from the loadcapacitance by making a feedback path from load capacitance tothe supply.In this paper we first study of various adiabatictechniques and will lay emphasis on one of its widely usedtechnique called the Efficient Charge Recovery Logic (ECRL). Wewill study how ECRL technique is better than the rest and howcircuits are implemented using it.Using this technology we willdesign a 32 bit barrel shifter and perform various tests on thecircuit. We will also compare the results of this adiabatictechnology with the normal CMOS technology and show thedrastic reduction in power dissipation. All the design structuresbased on Adiabatic Switching Logic are designed and simulatedusing standard TSMC 0.18 μm CMOS technology and 5 V voltagesupply at an operating temperature of 27º C. Mentor GraphicsCorporation based tool known as IC Design Architect have beenused for all the design and analysis.Keywords- Low power, Adiabatic, ECRL, Fully Adiabatic.,Partially Adiabatic Circuit (Quasi),Barrel shifter, MultiplexorI. INTRODUCTIONNow days the portable electronics has made low powercircuit design extremely desirable. All efforts eventuallyconverge on decreasing the power consumption entailed byever shrinking size of the circuits enabling the portablegadgets. Reducing power supply voltage is a straightforwardmethod to achieve low power consumption. The low powerand low voltage CMOS techniques were applied extensivelyin analog and mixed mode circuits for the compatibility withthe present IC technologies. Designing high – performanceanalog circuits is becoming increasingly challenging with thepersistent trend towards reduced supply voltages The desirefor portability of electronic equipment generated a need forlow power systems in battery operated products like hearingaids, implantable cardiac pacemakers, cell phones, and handheld multimedia terminals. Low power dissipation isattractive, and perhaps even essential in these applications tohave reasonable battery life and weight. The ultimate goal indesign is close to having battery- less systems, because theManuscript received on February, 2013.Shweta Chawla, Department of ECE & EEE, BM Group of Institution,Gurgaon, India.Ramanand Harijan, Department of ECE & EEE, BM Group ofInstitution,Gurgaon,India.Harpal Singh, Department of ECE, SGTIET, Gurgaon, India.battery contributes greatly to volume and weight. [1],[ 3],[4],[9].The low-power requirements of present electronic systemshave challenged the scientific research towards the study oftechnological, architectural and circuital solutions that allow areduction of the energy dissipated by an electronic circuit.One of the main causes of energy dissipation in CMOScircuits is due to the charging and discharging of the nodecapacitances of the circuits, present both as a load and asparasitic. Such part of the total power dissipated by a circuit iscalled dynamic power. In order to reduce the dynamic power,an alternative approach to the traditional techniques of powerconsumption reduction, named adiabatic switching [1][2], hasbeen proposed. In such approach, the process of charging anddischarging the node capacitances is carried out in a way sothat a small amount of energy is wasted and a recovery of theenergy stored on the capacitors is achieved.II. ADIABATICThe term “adiabatic” describes a thermodynamic process inwhich there is no energy exchange with the environment, andtherefore no dissipation of energy or power occurs. But inVLSI, as the transfer of the electric charge takes placebetween the nodes of a circuit, various techniques can beapplied to minimize this energy loss during this chargetransfer process. [2]Adiabatic technology is basically used toreduce the energy or power dissipation during the switchingprocess and further reuse some of the energy by recycling itfrom the load capacitance. For recycling, the adiabaticcircuits use the constant current source power supply and forreduce dissipation it uses the trapezoidal or sinusoidal powersupply voltage. Adiabatic logic works on the principal ofreversible logics. Reversible logic means when a systemerases a bit of information, it dissipates heat and today‟scomputers erase a bit of information every time they performa logic operation. These are called irreversible logics. And incontrast to it, the logic operations that do not eraseinformation these are called reversible logics. Today mostresearch has focused on building adiabatic logic out ofCMOS. However, current CMOS technology, though fairlyenergy efficient compared to similar technologies, dissipateenergy as heat, mostly when switching. To reduce this thereare two fundamental rules:-1. Never turn on a transistor when there is voltagedifference between drain and source.2. Never turn off a transistor that has current flowingthrough it [2].logic and the energy flows through the transistor in acontrolled manner. As the second rule states that the transistormust not be turned off when there is current flowing throughit, reason behind this is that the transistors are not perfectswitches. The change from one state to another is directlyproportional to the speed at which the gate voltagechanges.[2]140

as inputs for the evaluation of the next stage. After the holdphase, pwr falls down to a ground level, /out node returns itsenergy to pwr so that the delivered charge is recovered. Thus,the clock pwr acts as both a clock and power supply. Forinstance if we consider a circuit of a two input(x, y) AND gatewith output(y).output , y = x.y (1)And, = = + (2)International Journal of Engineering and Advanced Technology (IJEAT)ISSN: 2249 – 8958, Volume-2, Issue-3, February 2013Figure 6. Implementation Schematic 4.1 multiplexer usingECRL technologyFigure 4. ECRL and gate circuitSo by substituting the value of y and at the positions of Fand F/ n tree positions in the Fig. 1 respectively we get theAND circuit implementation using ECRL technology.[5]Similarly in the 4*1 Multiplexer having inputs(D0,D1,D2and D3) along with select lines(S1 and S2), we get the outputY, Where(3)(4)(5)Figure 7. Implementation schematic 4.1 multiplexer usingCMOS technologyIV. 32 BIT BARREL SHIFTERA barrel shifter may be defined as a digital circuit that shiftsa data word by a specified number of bits in one clock cycle. Itis a bit-rotating shift register. The bits shifted out the MSBend of the register are shifted back into the LSB end of theregister. In a barrel shifter, the bits are shifted the desirednumber of bit positions in a single clock cycle. For example,an eight-bit barrel shifter could shift the data by threepositions in a single clock cycle. If the original data was11110000, one clock cycle later the result will be10000111.Functionally, since any bit can end up in any bitposition, multiplexers are used to place the bits correctly forproper storage. Thus, a barrel shifter is implemented byfeeding an N-bit data word into N, N-bit-wide multiplexers.An eight-bit barrel shifter is built out of eight flip-flops andeight 8-to-1 multiplexers; a 32-bit barrel shifter requires 32registers and thirty-two, 32-to-1 multiplexers, and so on.Working of a barrel shifter can be explained with the help of a4 bit barrel shifter. A four bit barrel shifter may require four,input multiplexer shown in figure 8 below.Figure5. ECRL multiplexer circuitFigure 8. 4-bit barrel shifter circuit142

Design Low Power 32-Bit Barrel shifter using Efficient Charge Recovery LogicThe above figure shows the block diagram of a shift rotatebarrel shifter. The bits enter the barrel shifter through the fourinputs(d0,d1,d2,d3) , and the rotated output is received at(s0,s1,s2,s3). The amount of rotation depends upon the selectlines of the multiplexer (c0, c1).The inputs are received onlyon the least significant bit of the multiplexer and rest of thepins are all interconnected. Which can be further explainedwith the help of a truth Table II the rotation always takes placewith respect to the input pattern, i.e W3,W2,W1,W0, and theamount of rotation depends upon the binary equivalent of theinputs at the select lines.Table II. Truth table of Barrel shifterC0 C1 S3 S2 S1 S00 0 W3 W2 W1 W00 1 W0 W3 W2 W11 0 W1 W0 W3 W21 1 W2 W1 W0 W3Figure12. Input multiplexor symbolAnd second we design the 4-input multiplexer usingadiabatic switching shown above figure and then combinedboth the design 32- input multiplexor and finally we design32-bit barrel shifter shown figure.As discussed above, for the design of a 32 bit barrel shifter,we require 32 input multiplexers and all the design structuresbased on Adiabatic Switching Logic are designed. So now Iwill demonstrate step by step procedure followed for thedesign of 32 bit barrel shifter. First we design two inputmultiplexor shown in figure below.Figure13. 32 input multiplexer SchematicFigure 9 input multiplexor schematicFigure 10. Input multiplexor symbolFigure 11. 4 input multiplexor schematicFigure14.32 input multiplexer Symbol143

Figure15. 32 Input Barrel shifter using ECRL technologySchematicV. SIMULATION RESULTFirst we design 4:1 multiplexor using ECRL technologyand CMOS technology. all the design structures based onAdiabatic Switching Logic are designed and simulated usingstandard TSMC 0.18 μm CMOS technology and 5 V voltagesupply at an operating temperature of 27º C. Mentor GraphicsCorporation based tool known as IC Design Architect havebeen used for all the design and analysis and figure 8 showsthe 4:1 multiplexor output wave form and Table II shows thecomparison result of ECRL technology and CMOStechnology. From the below Table III it is clear that the PowerDissipation is reduced in ECRL technology when comparedwith the CMOS technology. Number of elements, nodes andinput signals are all reduced in this technology. In ECRL thereis only two PMOS used, no matter how large the circuit is. Butin CMOS technology it uses equal number of PMOS andNMOS. And as we know that PMOS is a greater source ofpower dissipation hence it is reduced in this technology.A. Comparison Result of ECRL and CMOS TechnologyTable III is clear that the Power Dissipation is reduced inECRL technology when compared with the CMOStechnology. Number of elements, nodes and input signals areall reduced in this technology. In ECRL there is only twopmos used, no matter how large the circuit is. But in CMOStechnology it uses equal number of pmos and nmos. And aswe know that pmos is a greater source of power dissipationhence it is reduced in this technology.Table III. Compression result ECRL and CMOS multiplexerBasisECRLmultiplexerCMOSmultiplexerMemory space 56631296 56635392allocated (Bytes)Elements 39 46Nodes 26 30Input Signals 13 14Temperature ( o C) 26 27Total PowerDissipation (Watts)4.4242N 6.2611NB. Comparison ECRL and CMOS Technology BarrelShifterFrom the above results it could be formulated that thepower dissipation in 32 bit barrel shifter made from ECRLtechnology has been reduced when compared with the CMOStechnology. The results show a drastic reduction in number ofInternational Journal of Engineering and Advanced Technology (IJEAT)ISSN: 2249 – 8958, Volume-2, Issue-3, February 2013nodes and number of elements used. Hence ECRL technologycan always be used when power dissipation is the concerningmatter.Table IV. Compression result ECRL and CMOS multiplexerBasisECRLBARRELSHIFTERCMOS BARRELSHIFTERMemory space 95240192 96174080allocated (Bytes)Elements 11014 12998Nodes 6374 7686Input Signals 2374 2374Temperature ( o C) 27 27Total PowerDissipation(Watts)379N 1.5169UC. ECRL Barrel shifter Variation of power dissipationwith temperature for 10 test vectorsTable V. Variation of power Dissipation with TemperatureTEMPERATUREDELAY(Ns)FREQUENCY(Meg Hz)POWERDISSIPATION( Watts)-50 404.68 49.860 49.4188N-40 402.40 49.888 54.8285N-20 411.59 49.911 80.4732N-5 412.92 49.931 124.6314N0 423.54 49.898 147.0092N5 421.08 49.937 174.4488N20 428.10 49.903 296.4472N40 435.89 49.917 595.8815N60 438.09 49.896 1.1561U75 447.18 49.917 1.9104UACKNOWLEDGMENTThis work has been carried out in department of VLSIDesign, Center For Development Advanced Computing,Noida and supported by Banasthali university. Authors wishto thank both the CDAC Noida, Scientific organization andthe University for providing all laboratory and equipmentssupport for the research work.REFERENCES[1] A. P. Chandrakasan, S. Sheng, and R. W. Brodersen, “Low PowerCMOS Digital Design,” IEEE Journal of Solid-state Circuits, Vol. 27,No. 04, pp. 473-484, April 1999.[2] J. S. Denker, “A Review of Adiabatic Computing”, 1994 IEEESymposium on Low Power Electronics, pp 94-97, 1994.[3] T. Indermauer and M. Horowitz, “Evaluation of Charge RecoveryCircuits and Adiabatic Switching for Low Power Design,” TechnicalDigest IEEE Symposium Low Power Electronics, San Diego, pp.102-103, October 2002.[4] W. C. AthaS, J. G. Koller, L. Svensson, “An Energy- Efficient CMOSLine Driver using Adiabatic Switching” Fourth Great Lakessymposium on VLSI, California, March 2005.[5] A. Kamer, J. S. Denker, B. Flower, et al., “2N2D-order AdiabaticComputation with 2N-2P and 2N-2N2P Logic Circuits,” In Proc. of theInternational Symposium on Low Power design, Dana Point, pp.191-196, 1995.[6] A. Blotti And R. Saletti, “Ultralow- Power Adiabatic CircuitSemi-Custom Design”, IEEE Transaction on VLSI system, vol. 12, no.11, pp. 1248-1253, November 2004.[7] Dragan Maksimovic´, G. Vojin, Oklobdžija, and et all, “ClockedCMOS Adiabatic Logic with Integrated Single-Phase Power-Clock144

Design Low Power 32-Bit Barrel shifter using Efficient Charge Recovery LogicSupply,” IEEE Transactions on VLSI Systems, Vol. 08, No. 04, pp.460-463, August 2000.[8] Y. Moon and D. K. Jeong, “An Efficient Charge Recovery LogicCircuit,” IEEE JSSC ,Vol.31, No. 04, pp. 514-522, April 1996.[9] S.S. Rajput and S.S. Jammuar, “Low Voltage Analog Circuit DesignTechniques”, IEEE Transactions on Circuits and System Magazine,Vol no.-2, pp. 24 -42, 2002.Ms. Shweta Chawla received the B.Tech degreein electronic & communication engineering fromMaharishi Dyanand University Rohtak andM.tech degree in VLSI Design from BansthaliUniversity Jaipur and her Research work done inScientific organization CDAC Noida.CurrentlyAssistant professor Department of electronic andcommunication at B.M. Group of institutionGurgaon .Her research interests are in low powercircuits and analog designMr. Ramanand Harijan received the B.Techdegree in ECE, and M.Tech degree in VLSIDesign from CDAC Mohali. He has been on theHOD department of ECE & EEE at B.M. Groupof Institution, Gurgaon. His research interests arein low power circuits, analog design, and digitaldesign and CMOS RF circuits.Mr. Harpal Singh received the B.Techdegree in ECE from Maharishi DyanandUniversity Rohtak, and M.Tech 2 ndsemester student in ECE from S.G.T.Institute of Engineering & Technology,Gurgaon. His research interests are in lowpower circuits, analog design145