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VHDL - Practical Example - Designing an UART

VHDL - Practical Example - Designing an UART

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Application ArchitectureRXFLEXNoted on PCB = CTSFlexRTSFLEX**RS232 InputsI15I54RawRxCLKRSTDRawRTSI218CLKCI306DQQSDout[7:0]LD_SDoutRXBaud[2:0]CLKRSTRTSDin[7:0]LDRxBaud[2:0]CLKRST<strong>UART</strong>SI320<strong>UART</strong> moduleTxTxBusyDout[7:0]RxRDYRxErrTXTxBusySDin[7:0]RxRDYRxErr* TXoutI14(0=active)TxBusySDout[7:0] SDout[7:0] * CTSFLEXSDin[7:0]I202LD_SDout LD_SDoutNoted on PCB = RTSFlexRxRDYRxErrRTSApplicationRS 232 OutputInversion neededRSTCI307External Baud Rate SelectionBaud[2]DIPSW[2] *I319Baud[1]DIPSW[1] *I318Baud[0]DIPSW[0] *I317CLK CLKRST RST© Bertr<strong>an</strong>d CUZEAU - info@alse-fr.com

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