Designing Operational Amplifier Oscillator Circuits for ... - Microchip

AN866Gain (dB)⎛C 3 ⎞20log 10⎜------⎟⎝C 4 ⎠F1z1= --------------------2πR 5C 3OscillationRangeAssumptions1. C 3 > C 42. R 3 < R 4 < R 53. R 3 < < R 5 and R 4 ≈ R 5-----100 Frequency (Hz)⎛ R20log 4 ⎞10⎜--------------------⎟⎝R 3+ R 5 ⎠1F p1= -------------------- F = --------------------1p22πR C 2πR 4 43C 3FIGURE 8:Bode Plot of Differentiator Amplifier.Voltage Limit CircuitThe ratio oscillator uses a limit circuit to accommodatethe varying gain requirement of the circuit. It may benecessary to add a voltage limit or clamp circuit to theoscillator to prevent the amplifiers from saturating andavoid slew rate limitations. The voltage limit circuitformed by PNP transistor Q 1 is used to create the maximumvoltage limit. The clamping voltage of the limitcircuit is provided below:EQUATION:V Max_Limit= V Q1_base+ V Q1_base-to-emitterV Max_Limit≅ V Q1_base+ 0.7VIn single-supply applications, it is not necessary to useboth maximum and minimum limit circuits. Only one ofthe limit circuits is required due to the symmetry of thesinewave that is centered around the virtual groundvoltage at the non-inverting terminal of the amplifiers(V DD /2). In the reference design of Figure 6, V DD isequal to 5V and V Q1-base is equal to 2.5V. Thus, theoscillation waveform at V 2 will swing from 1.8V to 3.2Vor 2.5V ±0.7V.Note that the transistor adds a small capacitance (C Q1 )to the integrator capacitor of the circuit (C 2 ). If C 2 is relativelysmall, the effective capacitance of the limit circuit(C Limit ) can be reduced by connecting a diode inseries between the emitter junction and the output ofthe amplifier (i.e. 1/C Limit = 1/C Q1 + 1/C Diode ).© 2003 Microchip Technology Inc. DS00866A-page 8