A 4 GHz Dual Modulus Divider-by 32/33 Prescaler in ... - LSI - USP

A 4 GHz Dual Modulus Divider-by 32/33 Prescaler in 0.35µmCMOS TechnologyFernando P. H. de MirandaEscola PolitécnicaUniversidade de São Paulo - BrasilAv. Prof. Luciano Gualberto, 158.Trav.3 CEP: 05508-900São Paulo - SP - Brasil.(55)(11) 3091 9721nando@lsi.usp.brJoão Navarro S.Jr.Escola PolitécnicaUniversidade de São Paulo - BrasilAv. Prof. Luciano Gualberto, 158.Trav.3 CEP: 05508-900São Paulo - SP - Brasil.(55)(11) 3091 5663navarro@lsi.usp.brWilhelmus A.M. Van NoijeEscola PolitécnicaUniversidade de São Paulo - BrasilAv. Prof. Luciano Gualberto, 158.Trav.3 CEP: 05508-900São Paulo - SP - Brasil.(55)(11) 3091 5668noije@lsi.usp.brABSTRACTThe design of a dual modulus prescaler 32/33 in a 0.35µm CMOStechnology is presented. The prescaler is a circuit employed inhigh frequency synthesizer designs. In the proposed circuit thetechnique called Extended True Single Phase Clock (E-TSPC), anextension of the True Single Phase Clock (TSPC) technique, wasapplied. Additionally some new structures to double the dataoutput rate are also employed. Simulations, based on the prescalerlayout, were carried out and the results indicate that the circuitcan reach up to 4 GHz with 4.38 mW of power consumption andpower supply of 3.3 V.Categories and Subject DescriptorsB.7.0 [Integrated Circuits]: General.General TermsDesign.KeywordsPrescaler, TSPC, High Speed Digital Circuit, Low Power1. INTRODUCTIONThe CMOS Technology has been the main integrated circuittechnology for at least 15 years due to its advantages in terms ofintegration level, power consumption, easiness of design, and lowcosts. With the continuous reduction of the transistor dimensions,some of these advantages, such as integration level, haveincreased and new ones have been added, such as the technologyspeed, extending the technology uses to areas where only fasterand more expensive technologies (Bipolar and GaAs) wereapplicable.Permission to make digital or hard copies of all or part of this work forpersonal or classroom use is granted without fee provided that copies arenot made or distributed for profit or commercial advantage and thatcopies bear this notice and the full citation on the first page. To copyotherwise, or republish, to post on servers or to redistribute to lists,requires prior specific permission and/or a fee.SBCCI’04, Sept. 7-11, 2004, Porto de Galinhas, Pernanbuco, Brazil.Copyright 2004 ACM 1-58113-000-0/00/0004…$5.00.One of these new application areas is RF circuits: circuits fortransmission and reception of information through radiofrequency waves. This area presents wide spectrum ofapplications varying from command devices for automatic gatesto sophisticate cellular phones.In the more complex RF systems, an important block is thefrequency synthesizer. This block is responsible for the generationof signals in specific frequencies that are used for channelmodulation and demodulation inside the transmission band [1]. Asynthesizer is composed of a voltage controlled oscillator (VCO),counters, phase comparators, and filters. Some architectures ofsynthesizer use, with the counters, a dual-modulus prescalerN/N+1: a frequency divider that can divide an input clock by N orN+1. In general the prescaler is a block with critical operation interms of speed and power consumption since it receives the clockdirectly from the VCO output, the fastest signal in the synthesizer.In this work, we will present the design and simulation results of adual-modulus prescaler 32/33. In the prescaler was used the E-TSPC technique, Extended True Single Phase Clock, that uses theTrue Single Phase Clock (TSPC, a logic technique that workswith one clock phase [2]), and enlarges the acceptable designblocks and their possibility of connections [3], [4], [5].Additionally, we applied some new structures that are conceivedto duplicate the circuit speed [6]. The design was developed usingthe AMS 0.35 µm CMOS technology, with four levels of metaland two of polysilicon. The paper is organized in five sections: insection two the E-TSPC technique and the new structures arepresented; in section three the prescaler 32/33 is discussed; insection four the results are drawn; in section five the conclusionsare summarized.2. THE E-TSPC TECHNIQUEThe E-TSPC technique, an extension of the TSPC, was proposedin [4]. A simplified presentation, with respect to the theorems andtheir demonstrations, is done in [3], and it serves as basis to whatis exposed here.The following blocks are used for this technique:• complementary static logic gates CMOS;• dynamic, n-dynamic and p-dynamic, logic gates;• latches, n-latches and p-latches.

Also N-MOS like blocks [5] can be used (see Figure 1). Theseblocks can be built starting from dynamic gates, n and p, or fromlatches, n and p. These blocks are faster although have higherpower consumption, and they should be used when high speed isnecessary.In the technique the concept of data chains [6], n-data chains andp-data chains also is introduced. An n-data chain is a portion ofthe circuit that evaluates the input signals when the clock is at theHIGH level, and that holds the output value, with the lastevaluated state, when the clock is at LOW level. The later state iscalled holding state and the former, evaluation state. In the case ofp-data chains occurs the inverse of the n-data chains, being nowthe evaluation executed at the clock LOW level and the holding,at the HIGH level.Formally we can define n-data chain as a data propagation pathwith the following characteristics:1. must contain at least one n-dynamic block or n-latch;2. must start in an external input of the circuit or in the output ofsome p-dynamic block or p-latch;3. must contain only static, n-dynamic, or n-latches blocks;4. do not matter the order or the number of these blocks;5. must finish in the input of a p-dynamic block, or a p-latch, orbe a circuit output.inputclockclockn-transis.logica) n-dynamicoutputinputclockn-transis.logicoutputb) NMOS liken-dynamicinputclockclockp-transis.logicoutputc) p-dynamicinputclockp-transis.logicoutputd) NMOS likep-dynamicblocks B A , B C , B E and B I ; other n-data chain is initiated at theinput i d and follows through the blocks B C , B E , B F , B H and B K .Some special data chains of the E-TSPC will be used to doublethe circuit speed. These data chains are called fo structures. Tounderstand how they can be used, we must observe an operationcharacteristic of certain data chains [6]. Consider data chains, n orp, that possess a single latch (it must be, due to the rules, the lastblock of the data chain). For these data chains, called as fo-datachains (data chains with the fusible outputs), the output stays in ahigh impedance state during the holding state.Table 1. Rule of the block connections inside of data-chains.N-MOS like blocks must obey the same rules of the normalinput signalof the datachainlatchoutputn-dynamicoutputp-dynamicoutputlatchinputblocksn-dynamicinputp-dynamicinputn.r. n.r. n.r.n.r. n.a. n.a.n.r. odd n.a.n.r. n.a. oddn.r.: no restrictions; n.a.: the connection is not allowed; odd:an odd number of blocks is required.in p u tclockp-transis.logicn-transis.logice) n-la tchoutputinputp-transis.logicoutputclockf) N M O S liken-la tchinputclockp-transis.logicn-transis.logicg) p-la tchoutputin p u tclockn-transis.logicoutputh) NMOS likep-la tchFigure 1. Conversion of blocks to N-MOS like.In the case of p-data chains, a similar definition can be applied,changing n for p and vice versa.For the correct operation of a data-chain, to make the evaluationin one clock phase and the holding in the other, it is necessary thatthe data chain presents one of these two configurations:• at least two blocks, one dynamic block and one latch;• at least two latches and an even number of blocks (inversions)between them.Additionally, the adjacent blocks in the propagation path of adata-chain need to have a number of blocks (inversion) inaccordance with the rules of table 1 (two blocks are calledadjacent if between them there are placed only static blocks).Examples of n-data chains are shown in Figure 2 [5] [6]: one n-data chain is initiated at the i a input and follows through theFigure 2. Examples of n-data chains.This high impedance state in fo-data chains can be used toincrease the processing speed, and implementations based on thatare proposed. The outputs of two fo-data chains, a p and an n,can be joined and, in this case, we can get new processed signalsto each half cycle of the clock, what implies in doubling the dataoutput speed. Consider, for example, the circuit of Figure 3;during the phase where clock is HIGH, the n-data chain is in theevaluation state and imposes the result at the output, while the p-data chain will be in high impedance state; during the phasewhere the clock is LOW, the p-data chain is in evaluation andimposes the result at the output, while the n-data chain will be inhigh impedance. This type of structure is used in the proposedcircuit.

Figure 3. Fo Structures to duplicate the output data rate.3. CIRCUIT DUAL-MODULUSPRESCALER 32/33Figure 4 presents a conventional dual-modulus prescaler 32/33circuit. It receives a clock signal and divides by 32 or 33,depending on the value of an external control signal called S M :when S M is at LOW logic level, the circuit divides the clock by 32(N); when S M is at HIGH logic level, it divides the clock by 33(N+1). This circuit is composed of two counters, a synchronouscounter and an asynchronous counter. In the crosshatched part wefind the synchronous counter that carries out the counting up to 4or 5, depending on the value of the signal div8. The synchronouscounter constitutes the critical element for good performance interms of speed, since it receives as its clock the signal from theVCO output and, thus, works in the highest speed of the system.The asynchronous part is composed of three D type flip-flops (D-FF) that carry out the counting up to 8. It is the synchronouscounter that generates the clock for the first D-FF of theasynchronous counter.clockin1in2DD-FF QD QD-FFC Qp-datachainp-datachainfo-n datachainn-datachainfo-p datachainDivider by 4/5 (counter)smDD-FFD QD-FFC QQdiv8Figure 4. The Dual-Modulus Prescaler schematic (divider by32/33).The implementation proposed here for the prescaler is based on anew synchronous counter circuit. This circuit is in fact a statemachine and, similar to any state machine, it can be implementedwith the fo-data chains previously defined. The desired output ofthe circuit, the clock divided by 4 or 5, is the state machine outputand will be produced by the combination of two other signals,which are generated with a rate equal to the half of the clock rate.The new implemented synchronous counter works as the statemachine whose diagram is in figure 5, and its clock, clk/2, has afrequency equal to the half of the original clock frequency (theclock that we desire to divide by 4 or 5). The output is formedfrom the combination of signals A and B: A during the phasewhere clk/2 is HIGH and B during the phase where clk/2 is LOW.We can exemplify the operation analyzing the state diagram offigure 5. When the logic value at the div8 (division control signal)is HIGH, there are two possible operations for the state machine:to be moving between states 000 and 110, or between 100 and010. Let us consider the case of moving between 000 and 110.The output signal will have the values LOW, A, LOW, B, HIGH,A, and HIGH, B (0011) during each half cycle of the clk/2. If weremember that the circuit works with half of the original clockoutDD-FFD QD-FFC QQoutput32/33signal rate, we can see that the AB combination is the originalclock signal divided by 4. When the logical value in div8 is LOW,the states will pass through the following states: 000, 110, 001,010 and 101 and the output will have the values LOW, A, LOW,B, HIGH, A, HIGH, B, LOW, A, LOW, B, LOW, A, HIGH, B,HIGH, A, and LOW, B, (0011000110), during each half cycle ofthe clk/2. In this case we can see that AB combination is the clocksignal divided by 5.Operation ofthe dividerby 4Operation of thedivider by 5Clock signalCounteroutputOUCounteroutputsinal div8Counteroutputsignal div8signal ATemporarystate 0001011 111011100001 101100signal A e Bsignal Bany valuesignal Bany valueStateABC1010input div8clock/2 signal = state machine clocksignal AFigure 5. State diagram of the circuit.Figure 6 presents the schematic diagram of the state machine thatimplements the Figure 5 state diagram, and Figure 7 presents thetransistor diagram of the complete synchronous counter for theAMS 0.35 µm technology (the transistor dimensions are alsoindicated). For the circuit implementation, TSPC D-FFs [2](similar to Figure 8 D-FFs) modified in accordance with the E-TSPC rules have been applied. The logic gates NOR and ANDhave been merged with D-FFs, forming the three blocks markedin the Figure 7 (BL A , BL B and BL C ). In addition to these blocks,we have two more, BL O1 and BL O2 , that are responsible formerging the A and B signals.State Machineclk/2DD-FFQADD-FFBL A div8 BL C BL BFigure 6. Schematic diagram for implementation of the statemachine of the figure 5.In the asynchronous counter configuration TSPC D-FFs (Figure8) were used. This counter presents a less critical operation interms of speed.Some comments must be done regarding the circuit transistordimensions:QC0DD-FFQB

• in most transistors, the minimum width value allowed in thetechnology, W=1µm, was used. With this choice we favor a lowpower consumption and sacrifice the speed;with Typical and Slow transistor parameters) present thesimulation results of the proposed and the conventional prescalerimplementations.• in N-MOS like blocks, where N and P transistors need obeycertain relations, dimensions different from the minimum wereapplied.BLO1BLO2clk/21.0 3.0clk/21.4 1.73.01.0 clk/21.0 1.0clk/2 clk/21.0 1.0clock of thedivide by 8counterclk/21.3 1.551.0 1.0clk/21.0 1.0clk/2clk/2 clk/2 clk/21.5clk/2 clk/2 clk/21.5 1.0 3.01.0 3.01.03.01.0BAC1.0 1.01.0 1.0 4.0 1.0 1.04.0clk/2 clk/2clk/2 clk/2clk/2 clk/22.0 2.0 1.0 1.0 3.0 3.0 1.0 1.0 4.0 1.0 1.0BLAdiv8Figure 7. Transistor diagram of the new synchronous counterimplementation. The width dimension of the transistors, W,are indicated in the figure. All the channel lengths are equal tothe minimum of the technology (L=0.35µm).The critical node in the circuit, in terms of speed, is the C node(see Figure 7). At this point, a relatively large load capacitance ispresent.1.01.01.0BLC1.01.01.03.01.01.0BLBFigure 8. Configuration of TSPC D flip-flops (D-FF) for theasynchronous circuit. The transistor widths are indicated inthe figure (the length is 0.35 µm).4. RESULTSThe complete layout of the dual-modulus prescaler 32/33 circuitwas implemented in a 0.35 µm CMOS technology. The circuitoccupies an area of 65µm x 38µm and is presented in Figure 9.Several simulations based on the netlist extracted from the layoutwere carried out. These simulations have been done through theprogram HSPICE, using BSIM3v3 model with typical (Ty) andslow (Sl) foundry parameters. In order to evaluate the proposedprescaler, the simulation results are compared with simulationresults of a conventional prescaler, figure 4, implemented with E-TSPC blocks (without fo structures) in the same technology0.35µm [1] and, later, with results from other prescalers presentedin literature.The graphics in Figure 10, Operation Frequency versus Powersupply, in Figure 11, Power consumption versus OperationFrequency (for different power supply values), and in Figure 12,Power consumption versus Operation Frequency (for V DD = 3.3V2.03.0Figure 9. Layout of the new dual modulus prescaler 32/33.The circuit has the dimensions of 65µm x 38µm.43.5OperationFrequency 3(GHz)2.521.51PD=0.26 mWPD=0.24 mWPD=0.91 mWPD=0.69 mWPD=1.84 mWPD=1.46 mWPD=3.31 mWPD=2.55 mWPD= 4.3PD=3.370.51.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4Power Supply (V)new(Ty)old(Ty)Figure 10. Operation frequency versus Power supply (Typicalmodel). The power consumption of each point is alsoindicated.In Figure 10, we can observe that the proposed circuit is fasterthan the conventional circuit, being 900 MHz faster for V DD of 3V. Notice that the power consumption in the proposedimplementation is higher for the same power supply conditionsdue to the fact that in such conditions it works at a higherfrequency.4.54Power3.5Consumption(mW) 32.521.5new (Ty)old (Ty)VDD =3.0V1VDD =2.0VVDD =2.0V0.50VDD =1.5V0.5 1 1.5 2 2.5 3 3.5 4Operation Frequency (GHz)VDD =3.3VVDD =2.5VVDD =2.5VVDD=3.3VVDD =3.0VFigure 11. Power consumption versus Operation frequency(for different values of power consumption and Typicalmodel). The power supply of each point is also indicated.

In Figure 11, we can observe that, if the power supply could beadjusted, the proposed prescaler consumes less power for thesame operation frequencies. As the power supply value isreduced, this advantage deteriorates, indicating that the newcircuit is less effective at low power supply conditions.In Figure 12, the behavior of the new and the conventionalcircuits are observed for Typical and Slow parameters. Analyzingthe curves for typical parameters, we observe that for frequenciesabove 2 GHz the conventional circuit consumes lower power thanthe new one; however the new circuit can reach higher operationfrequencies. For operation frequencies below this value, thesituation changes, favoring the new implementation in all aspects.Analyzing the curves for slow model, similar conclusions can bedrawn: for operation frequencies above 1.5 GHz, the conventionalcircuit consumes lower power, however the new circuit presentshigher operation frequency. For operation frequencies below thisvalue, the situation changes.4.543.5PowerConsumption 3(mW)2.521.51new (Ty)old (Ty)new (SI)old (Sl)0.5 1 1.5 2 2.5 3 3.5 4Operation Frequency (GHz)Figure 12. Power consumption versus Operation frequency(for V DD = 3.3V, using Typical and Slow model).For a better evaluation of the proposed circuit, results fromliterature of different prescaler implementations are presented intable 2.Two implementations pointed out in table 2 are particularlyinteresting: the prescaler of [5], a 132/133 dual modulus, issimilar to the implementation called here as conventional versionand uses a 0.8µm technology; the prescaler of [6], a 132/133 dualmodulus, is similar to the implementation of this work and uses0.8µm technology. Additionally, both [5] and [6] implementationswere done with small width transistors. Comparing the results intable 2 we can find some important results:• the implementation in [5] shows that the E-TSPC techniqueproduces high speed and low power consumption circuits;• the implementation in [6] and in this new work show that thenew fo structures increase the speed of the prescaler withoutadditional power costs;• the speed improvement from the conventional to the newimplementations in a 0.35 µm technology is similar to thespeed improvement from the conventional, [5], to the newimplementations, [6], in a 0.8 µm technology (comparingsimulations only). This indicates that the improvements donot really depend on the technology;• the power consumption obtained in 0.35 µm technology isvery low. This indicates that the circuit is excellent for lowpower applications.Table 2 – Different prescaler performance from the literature.The crosshatched results are from simulationsPrescalerTech.(µm)Powersupply(V)53[5] 0.8 53[6] 0.853[7] 0.853Maximumfrequency(GHz)1.590.781.460.812.191.351.220.64Powerconsump.(withoutclock buffer)(mW/GHz)8.03.511.23.9--20.99.35 1.8 29.4[8] 0.83 1.34-[9] 0.8 3 1.3 7.5[10] 0.75 2.65-3 1.75 13.7 *Conven.divider [1]0.35 3 2.86 0.89divider ofthis paper0.35 3 3.74 0.88* For this circuit, it is not clear if the measured power consumptionincludes or not the clock buffer power.5. CONCLUSIONIn the transmission and reception of RF signals, an importantblock is the dual-modulus divide by N/N+1 prescaler. Thisdivider is applied in the design of frequency synthesizers thatgenerates different frequency signals used in transceivers.In this work was proposed a 32/33 divider, implemented with theE-TSPC technique, an extension of the TSPC that considers newtopologies, using new configurations of logic gates and registers,and with structures that allow doubling the speed at the data-chainoutput. The proposed prescaler combine high speed and lowpower consumption. From the simulation results we obtained anoperation frequency of 4 GHz and power consumption of 4.4mW, at 3.3V power supply in a 0.35 µm CMOS technology.6. ACKNOWLEDGMENTSWe thank CNPq and FAPESP for their partial support for thiswork.

7. REFERENCES[1] Argüello. A.M.G. Estudo e Projeto de um sintetizador defreqüência para RF em tecnologia CMOS de 0,35µm. Ms.Dissertation, Department of Eletronic Systems Engineering,University of São Paulo, São Paulo, Brazil, 2003 (inportuguese)[2] Yuan, J.-R and Svensson. C. High speed CMOS circuittechnique. IEEE J. Solid-State Circuits, 24, 1 (Feb 1989), 62-70.[3] Navarro, J. and Van Noije, W. E-TSPC: Extended True SinglePhase Clock CMOS circuit technique for high speedapplications. SBMICRO J. Solid-State Devices and Circuits,5, 2 (1997), 21-26.[4] Navarro, J. Técnicas para projetos de ASICs CMOS de altavelocidade. PhD. Thesis, Department of Eletronic SystemsEngineering, University of São Paulo, São Paulo, Brazil. 1998(in portuguese).[5] Navarro, J. and Van Noije, W. A 1.6-GHz dual modulusprescaler using the Extended True-Single-Phase-Clock CMOScircuit tecnique (E-TSPC). IEEE J. Solid-State Circuits. 34, 1(Jan. 1999), 97-102.[6] Navarro, J., and Van Noije, W. Extended TSPC structureswith double input/output data throughput for GigahertzCMOS circuit design. IEEE Trans. on VLSI Systems, 10, 3(June 2002), 301-308.[7] Chang, B., Park, J., and Kim, W. A 1.2 GHz CMOS dualmodulusprescaler using new dynamic D-type flip-flops. IEEEJ. Solid-State Circuits, 31, 5 (May 1996), 749-752.[8] Yang, C.-Y., Dehng, G.-K., Hsu, J.-M., and Liu, S.-I. Newdynamic flip-flops for high-speed dual-modulus prescaler.IEEE J. Solid-State Circuits, 33, 10 (Oct. 1998), 1568-1571.[9] Yan, H, Biyani, M., O, K. K. A high-speed CMOS dual-phasedynamic-pseudo NMOS ((DP) 2 latch and its application in adual-modulus prescaler. IEEE J. Solid-State Circuits, 34, 10(Oct. 1999), 1400-1404.[10] Craninckx, J., and Steyaert. M.S.J. A 1.75-GHz/3-V dualmodulusdivide-by-128/129 prescaler in 0.7 µm CMOS. IEEEJ. Solid-State Circuits, 31, 7 (July, 1996), 890-897.