The Midterm Solution - Suraj @ LUMS - Lahore University of ...

Lahore University Of Management SciencesSchool of Arts and SciencesRoll No :Course Title :Computer Organization& Assembly LanguageTotal Pages: 16 (including this page)Quarter: SpringAcademic Year: 2002–2003Course Code : CS 223/ CMPE 221 Date: 12 th April, 2003Instructors :Shahid Masud &Tariq JadoonTime Allowed: 1½ hrsExam: Mid Term Total Marks: 90The instructions below must be followed strictly. Failure to do so can result in serious grade loss.⇒ DO NOT OPEN THIS EXAM UNTILTOLD TO DO SO.⇒ Read all questions very carefully before answeringthem.⇒ Check the number of papers in the question sheetand make sure the paper is complete.⇒ Keep your eyes on your own paper.⇒ You may not• talk to anyone once the exam begins.• leave the examination room and then return.Specific instructions:Open book/notes, help sheet:Calculator usage:Write in pen/pencil:Closed Book/Closed Notes/ No Help SheetDesirableAnything legible, but neatly pleaseAny other instruction(s): Attempt all questions ON this questionnaire.Be concise and answer in accordance to the allocated marks.Try to avoid overwriting/ cutting, etc.1 7 13 19 252 8 14 20 263 9 15 21 274 10 16 22 285 11 17 23 296 12 18 24Page 1 of 16

The solution shows the marking scheme for section III only)Part A [20 marks]Please encircle the correct answers. Each question carries 1 mark1. Which of the following is a memory that can only hold its charge for a short time andmust be refreshed periodically?a. DRAMb. SRAMc. SDRAMd. EPROMe. EEROM2. Which of the following non-volatile memory is electrically erasable and programmableat the block level (multiple bytes at a time)?a. EPROMb. SRAMc. SDRAMd. Flashe. EEPROM3. Which of the following ranks highest (smallest, most expensive, fastest access, mostfrequently accessed) in the memory hierarchy?a. hard driveb. cachec. CD-ROMd. RAMe. registers4. Which of the following ranks second in the memory hierarchy?a. hard driveb. cachec. CD-ROMd. RAMe. registers5. Which of the following ranks third in the memory hierarchy?a. hard driveb. cachec. CD-ROMd. RAMe. registers6. Which of the following ranks the lowest (largest, least expensive, slowest access, leastfrequently accessed) in the memory hierarchy?a. hard driveb. L1-cachec. L2-cached. RAMe. registersPage 2 of 16

S. Masud & T. Jadoon Computer Organization & Assembly Language (Mid Term Exam) 12 th April 20037. The concentric set of rings on a disk platter are called:a. gapsb. headsc. sectorsd. trackse. worms8. The conducting coils that read and write data on a disk platter are called:a. gapsb. headsc. sectorsd. trackse. worms9. The block-size regions that typically hold about 512 bytes of data on a disk platter called:a. gapsb. headsc. sectorsd. trackse. worms10. The areas of separation on a disk platter that break up the areas of physical data storageare called:a. gapsb. headsc. sectorsd. trackse. worms11. Which member of the memory hierarchy is regarded as the lowest-cost, slowest speedmedia?a. magnetic diskb. CD-ROMc. DVDd. magnetic tapee. Zip Drive12. This technology, popular for storing digitized video information, has a capacity of over 5gigabytes:a. magnetic diskb. CD-ROMc. DVDd. magnetic tapee. Zip Drive13. The time that it takes the read/write head of a disk drive to position under the desiredsector once it is positioned on the right track is called the:a. access timePage 3 of 16Page 3 of 17

The initial state of the memory (in hexadecimal notation) is detailed on page 6.Suppose the program counter is initialized so that the instruction at location 100h isexecuted first.Step through the program, updating the appropriate registers and memory locations,until the Halt instruction is reached.Answer the questions using the table provided on the next page detailing the initial contents ofmemory. You may also use the reverse side for rough work if necessary.a) What is the value of memory location 11Ah?_________0003 h_________b) What is the value of memory location 11Ch?_________0008 h or 0005 h______c) What is the value of memory location 11Eh?_________0003 h_______________d) What is the value of memory location 120h?_________000A h_______________e) What is the value of memory location 122h?_________0002 h_________________________f) What is the value of memory location 124h?_________0004 h_________________________PTOPage 6 of 16

Initial Contents of Memory in hex:Rough WorkLocation Contents100 011C102 3122104 1120106 011A108 211E10A 111A10C 411210E 1120110 1124112 011C114 211A116 111C118 700011A 0000Step No:1. AC= 00052. AC= 000A3. location 120: 000A4. AC= 00005. AC= 00036. location 11A: 00037. PC = 1128. AC= 00059. AC= 000810. location 11C = 0008OR Alternatively7. PC = 11C8. Can not continue, as we don’tknow the contents of location00511C 000511E 0003120 0000122 0002124 0004Page 7 of 16

Q22. [10 marks] An 8-bit microprocessor has a total addressable space of 64 kBytes.Organize the memory space so that the first 16 kBytes is ROM. The next 8 kBytes isempty for future expansion. This is followed by 16 kBytes RAM. The remaining spaceis once again empty for future expansion.(a) Label the starting and ending addresses of each region in hexadecimal. [4]16 k Bytes (ROM)8 k Bytes (free)16 k Bytes (RAM)0000 h3FF F h4000 h5FFF h6000 h9FFF hA000 hfreeFFFF hRough WorkIf the available ROM chips are (16k x 8) and RAM chips are (16k x 8). Draw ablock diagram of a suitable memory design implementing the memory mapdescribed in part (a) on the reverse side of this sheet. Label the address,data, and control lines on the microprocessor and memory chips. You mayuse additional logic chips if required. [6]Page 8 of 16

OR GateA15A14OR GateA133X8 DecoderA0-A12ReadCSRead/ WriteCS16 K x 8 16 K x 8ROMRAMD0-D7MicroprocessorPage 9 of 16

Q 23. [15 marks] A microprocessor has an on-chip 2-way set associative cache with a totalcapacity of 8 kByte. Each line in cache can store sixteen 8-bit words. It has a totaladdressable space of 16 MBytes.Consider the following CPU instruction:Load AB1234ha) Which set number will this request be stored in cache? [2]Number of lines in a set (k) = 2Total capacity of the cache = 8 k ByteBlock size = 2 w = line size = sixteen 8 bit words = 16 bytesNumber of sets (v) = 2 d = Total capacity /( k x line size) = 256Total addressable space = = 2 s+w = 16 M bytesAddress length = (s + w) bits = 24 bitsThus, in the main memory address:Size of set = d = 8 bitsSize of a word = w = 4 bitsSize of a tag = (s-d) bits = 12 bitsTherefore, Load AB1234h will store the result in set number:23 hb) What will be its corresponding tag number? [2]The corresponding tag number will be : AB1 hIf the microprocessor had a direct mapped cache with half the capacity of the setassociative cache. Then,c) Which line number would the request be saved in? [2]If a microprocessor had a direct mapped cache with half the capacity of the set ofthe two –way set associative cache, then it would have a capacity of 4 kbytes andeffectively the same number of lines as the number of sets in the set associativecache, i.e.Number of lines in cache = m = 2 r = 256Thus, in the main memory address:Size of a line = r = 8 bitsSize of a word = w = 4 bitsSize of a tag = (s- r) bits = 12 bitsTherefore, Load AB1234h will store the result inline number:23 hPage 10 of 16

d) What will be the corresponding tag number [2]The corresponding tag number will once again be : AB1 hNow consider the case if the microprocessor had an associative cache with four times thecapacity of the direct mapped cache.e) Which line number would the request be saved in? [1]In associative mapping any block can be stored in any line depending upon the currentoccupancy and replacement algorithms. Thus, we cannot say for sure which linenumber the request will be saved in.f) What will be the corresponding tag number? [2]Address length = (s + w) bits = 24 bitsThus, in the main memory address:Size of a word = w = 4 bitsSize of a tag = s bits = 20 bitsTherefore, Load AB1234h will store the result with a tag number: AB123 hg) Which of the above caches will have the fastest access time.Justify your answer. [2]The direct cache will have the fastest access time, given a hit, i.e. the presence of therequested block in cache as only one comparison of the tag will determine whether therequisite block is present or absent. Whereas, in associative memory one would haveto compare the required tag with all tags in cache and in a set associative cache onewould have to compare the required tag with all tags in the set.h) Which of the above caches has the best overall performance consideringreplacement. [2]Of the three schemes under consideration, the set-associative cache will have the bestoverall performance considering replacement. Access time from main memory istypical much larger than the access time from cache. Thus, if a situation where morethan one block was alternatively required that mapped to the same line number.Direct mapping would require us to overwrite the blocks alternatively and this wouldbe highly inefficient (thrashing). Associative mapping overcomes this but one has togo through the entire cache comparing tags to search for a block. Set-associativecache requires a relatively short time to access a block because one only checks for arequired block by comparing tags within a set usually of size 2 or 4 whilst avoidingthrashingPage 11 of 16

24. [15 marks]a) Convert the binary number 1001011.101 to decimal [2]1001011.101 = 1×2−3+ 1×2+ 1×2+ 1×2+ 1×2= 0.125 + 0.5 + 1 + 2 + 8 + 64= 75.625b) Convert the hexadecimal number AC to decimal: [1]−1013+ 1×26AC = 12 × 16= 1720+ 10 × 161What are the smallest and largest numbers that you can represent in a 10-bit register using:c) Unsigned notation [2]smallest number = 0largest number = 210−1= 1024 −1=1023d) Two’s complement notation (using the left-most bit as the sign-bit) [2]9smallest number = - 29largest number = + 2= −512−1= + 511e) Consider the following data definitions in a program: [2].datalist WORD 13, 11o, 42h, 00101011bFill out the corresponding values in HEX in the following table. The offsets arefrom the data segment.OffsetValue0000 00 h0001 0D hPage 12 of 16

0002 00 h0003 09 h0004 00 h0005 42 h0006 00 h0007 2B hUsing the Little Endian formatf) Under what conditions are the following flags set:i) overflow flag [1]Two positive operands were added and their sum is negativeTwo negative operands were added and their sum is positiveii) carry flag [1]If the result of an unsigned addition is too large (or too small) for the destinationoperand the carry flag is set.g) Would the following instruction set the zero flag? Explain. [1]MOV AX, 0000h;clear the AX registerThis MOV instruction does not affect the zero flag. Flags are affected by ALUoperationsh) Is it possible for a NEG instruction to set the Overflow flag? [1]The NEG instruction can set the overflow flag if we try to negate the smallest signedinteger in a register. The NEG instruction results in a positive integer, whichcannot fit into the same register. For example moving –128 to AL and trying tonegate it results in +128, which cannot fit in AL and consequently causes theoverflow, flag to be set.Page 13 of 16

i) Consider the following code:mov ax, 0hmov cx, 0AhdoLoop:dec axloop doLoopWhat is the value of the ax register after the completion of the doLoop? [2]The value of the ax register after completion of the loop is:FFF6 hRough WorkPage 14 of 16

Part C [15 marks]26. Which technique frees up the CPU by transferring data directly between the I/O deviceand memory: [1]a. Programmed I/Ob. Interruptsc. I/O Channeld. I/O Registerse. I/O Processorf. DMA27. In which technique, does the CPU issue an I/O command, continues to executesubsequent instructions, and is interrupted by the I/O module when the latter hascompleted its work: [1]a. Programmed I/Ob. Interruptsc. I/O Channeld. I/O Registerse. I/O Processorf. DMA28. When an interrupt occurs, arrange the following operations in their order of occurrence?[3]a) interrupt service routine executedb) the registers are restored by popping their values off of the stackc) the processor identifies the source of the interruptd) the program counter and other registers' values are pushed onto the stacke) the address of the interrupt service routine is placed in the program counterOrder of Occurrence:1. ____c_____2. ____d____3. ____e____4. ____a____5. ____b____PTOPage 15 of 16

29.[10 marks]SP(StackPointer)Consider that an interrupt takes place when themicroprocessor is executing an instruction stored atlocation N. The status flags at this instant contain thevalue ABCDh. The corresponding interrupt serviceroutine (ISR) is stored in memory starting from location Xand X + C (both inclusive)a) What is the address of the instruction that will beexecuted after the interrupt occurs. [2]XXstartb) Where will the program branch to after the completionof the interrupt? [2]N + 1c) How will the microprocessor know where to branchafter the completion of the interrupt? [3]X+C endPrior to branching to the ISR the microprocessorstores the address of the current value of theInstruction pointer onto the stack. On completion ofthe subroutine it pops this address off the stack andloads this into the instruction pointer and thusbranches back to the correct location.UserProgramNMAINMEMORYd) What will happen if a second interrupt takes placewhile the first one is being serviced? [3]If a second interrupt took place, then if it were ofhigher priority and the interrupt process was enabledthe microprocessor would once again push the currentcontext onto the stack and branch to the new ISR andon completing it branch back and complete the firstISR by popping off the context from the stack. If theinterrupt process was disabled or if the new interruptwas of a lower or the same priority as the currentinterrupt it would remain pending.Page 16 of 16