MOS Logic and Gate Circuits

MOS Logic and Gate CircuitsAAABAABYWired OR

ContentsIntroductionNMOS LogicResistive LoadSaturated Enhancement LoadLinear Enhancement LoadDepletion LoadSome GatesTransient in NMOS CircuitPseudo-NMOSCMOS LogicStatic CMOS Logic Gates• NOT• NAND• NOR• Realization of More Complicated Gate CircuitsTransmission Gates Family• NMOS Only Switch• CMOSDifferential Cascode Voltage Switch LogicRules of ThumbSummary

IntroductionThe MOS inverter is the basic circuit exhibits all of theessential features of MOS Logic. Extension of MOS inverterconcepts to NOR and NAND Gate is very simple. In thislecture we will analysis for VTC, NM, PD,… . Both NMOSand CMOS circuits are considered. Digital MOS circuits canbe classified into two categories: Static Circuits: require no clock or other periodic signal foroperation. Clocks are required for static circuit in sequentiallogic Dynamic Circuits: require periodic clock signals, synchronizedwith data signals, for proper operation even in combinationallogic

NMOS LogicResistive Load⎛ W ⎞⎜ VoL C SpeedL⎟ ↑⇒ ↓⇒ ↑⇒ ↓⎝ ⎠P↓⇒ RL↑⇒ Area ↑VoVddVi+VddRLVoV OLoVi

NMOS LogicResistive Load Properties N transistors + Load V OH= Vdd V OL= Vdd ( rN/(rN + RL)) Assymetrical response Static power consumption t PL= 0.69RLCL

NMOS LogicSaturated Enhancement LoadVds2 = Vgs2 ⇒+ Vdd + VddVds2 > Vgs2 −V⇒VoV OHδVoδVi= −1T2M2 is in saturationViM2M1Vo∝β RV OLoV ILViV IH

NMOS LogicSaturated Enhancement Load V ILV ≥V ⇒ M1, M2 are in saturationILT1⇒ K(Vgs1− V ) = K(Vgs2−V ),V ≈Cte2 21 T1 2 T2δVoVgs1 = Vi, Vgs2 = Vdd −Vo ⇒ = − βR, βR> 1δViδVo⇒ ≠ −1⇒ VI L≈ VT1δViT2VoV OHV OLoδVoδViV ILV IH= −1∝ β RVi

NMOS LogicSaturated Enhancement Load V OL• V OL is difficult to obtainbecause it is the outputvoltage when input equal toV OH , the resulting expressionis a fourth order polynomial!VoV OHδVoδVi= −1∝ β RV OLoV ILViV IH

NMOS LogicSaturated Enhancement Load V IH• M1 is in triode and M2 in saturationδVoδi1=−δViδViδVords1 rds2 ≈ rds1 = δ i( rds1 rds2)( )⎡⎣1i2 = K2(Vgs2−V T2)2δiKVo1δVi2i1 = K1 Vgs1−VT1Vo−Vo 21⇒ =12⎤⎦δiδVoK ( Vgs1 V Vo)δVoKVoδVi K (Vgs1 −V −Vo)1⇒ =1−T1−1⇒ =− = −⇒ Vo =Vi − V2V1 T1T1− VIH T1Vi = VIH⇒ = Vo21

NMOS LogicSaturated Enhancement Load V IH• M1 is in triode and M2 in saturationi= i ⇒1 21K ⎡⎣( V −V ) Vo− Vo 2⎤⎦= K (Vdd−Vo−V )22(Vdd − V )VT13β + 12 21 IH T1 2 T2T2⇒ VIH= +R

NMOS LogicSaturated Enhancement Load NMNML = V −V ≈Some tenth of voltILOLNMH = V − V = Vdd −V −VOH IH T2 IH PowerP ≈ 0, P = I VdddisH disL d⇒ P = 1 2I Vdddisd

NMOS LogicLinear Enhancement LoadVGG ≥ Vdd + V T2⇒ M2 is in triodeLinear Enhancement LoadVGGVi+VddM2VoM1

NMOS LogicLinear Enhancement Load VTC• By this circuit the V OHcan be increased (or Vddcan be decreasedbecause Vo max = Vdd )VoVddV OLoV ILVddViV TV IH

NMOS LogicLinear Enhancement Load V IL• M1 is in saturation and M2 in triodeδVoδi1 δi1δVds2=− rds2 =−δVi δVi δVi δi( )⎣⎡⎤⎦δi2= K2( VGG −Vo −VT2δVds2−Vds2)2i2 = K2 Vgs2 −VT2Vds2 −Vds2 2112i1 = K1(Vi−V T1)2δi1= K1( Vi−VT1)δViδVo−K(Vi 1−V T1)=− 1 =δVi K (VGG −Vo −V −Vds2)⇒ V = f(Vo)IL2 T2 V IH• M1 and M2 are in trioderds2 → rds1 rds2

NMOS LogicLinear Enhancement Load Disadvantages:• More chip area is required (since an extra voltage source VGG)• Additional interconnection on the chip is neededβ R• The required value of is even larger than a saturated load+VddVGGM2VoViM1

NMOS Logic Depletion Load Ion implantation processing step is needed to createdepletion device, but overcome the disadvantages ofthe previous circuit+VddM2VoViM1

NMOS Logic Depletion Load VTCVi = Low ⇒ i = 0, M1 in cutoff ⇒ i = i = 01 1 2K22if M2 is in saturation then i2= (Vgs2 − VT2) ,Vgs2 = 0 ⇒ i2> 02 Therefore M2 is in triodeVoVddV OLoV ILV TV IHVddVi

NMOS Logic Depletion Load V OL , V IL , V IH2 K22K ⎡1⎣( VOH −VT1)VOL − VOL 2 ⎤⎦= (0−V T2) ⇒ VOL= ?2δVoK(Vgs1−V )=− ⇒ =− = ⇒ =δVi K (Vgs2 −V −Vds2)1 T11 1, i1 i2 VIL?2 T22 K22 δVoi1 = K ⎡1⎣( VIH −VT1)Vds1− Vds1 2⎤⎦= i2= (0− VT2) , =−1⇒ VIH= ?2 δVi

NMOS Logic Some Gates In all previous structures which different only in load,the following Gates can be implemented. Note that theNMOS Gates are not available as separately packagedindividual circuits, but they are used extensively in LSIsystems• NOR Gates• NAND Gates

NMOS Logic Some Gates NOR Gate+VddAM1BRLM2YABY

NMOS Logic Some Gates NAND Gate+VddARLM2YABYBM1

NMOS Logic Some Gates In NOR Gate two transistors are paralleled but inNAND Gate two transistors are in series. Because ofthe need for increased area when adding NAND inputs,NAND logic with more than 2 inputs is noteconomically be attractive in NMOS. NOR logic ispreferable In NAND the M2 has body effect In NOR we need the less interconnection (this can beshown from layout)

NMOS LogicTransient in NMOS Circuits Saturated Enhancement Load+VddM2Cgs2Cgd1+VddCs − sub2CLVoViM1Cd − sub1C = C + Ceq + Ceq + Cgs2 + 2×Cgd1tot L d−sub1 s−sub2

NMOS Logic Super Buffer (1)If Fan-out is very large thenC tot will be large. Forreduction it and decrease theswitching time the SuperBuffer circuit is usedIn this circuit if Vi is Lowstate then V1 will be highvery more rapid than Vo.Thus the Gate of M2 is inhigh state very rapidly.Therefore M2 will be insaturation which result thereduction of switching time(t on )+Vdd +VddM4M2V1VoM1M3ViSuper Buffer (1) Circuit

NMOS Logic Super Buffer (2) It is non-Inverting Describe the operation ofthis circuit!M4+Vdd+VddM2ViV1M1M3VoSuper Buffer (2) Circuit

NMOS LogicPseudo-NMOS What makes a circuit fast?• I = C dV/dt -> tpd ∝ (C/I) DV• low capacitance• high current• small swing Logical effort is proportional to C/I PMOS are the enemy!• High capacitance for a given current Can we take the PMOS capacitance off the input? Various circuit families try to do this…

NMOS LogicPseudo-NMOS In the old days, NMOS processes had no PMOS• Instead, use pull-up transistor that is always ON In CMOS, use a PMOS that is always ON• Make PMOS about ¼ effective strength of pulldownnetwork

NMOS LogicPseudo-NMOS Uses a p-type as a resistive pullup, n-type network forpulldowns+VddM2VoViM1

NMOS LogicPseudo-NMOS Characteristics Compared to CMOS, thisfamily has higher packingdensity, since for n inputs onlyn+1 transistors are required The main disadvantages withPseudo-NMOS Gates is thelarge static power dissipationthat occurs whenever a pulldownpath is activated Has much smaller pullupnetwork than static gate Pulldown time is longerbecause pullup is fightingVi+VddM2VoM1

NMOS LogicPseudo-NMOS Output Voltages Logic 1 output is always at Vdd Logic 0 output is above Vss V OL= 0.25 (Vdd - Vss) is oneplausible choice+VddM2VoViM1

NMOS LogicPseudo-NMOS Design Topics For logic 0 output, pullup andpulldown form a voltage divider Must choose n, p transistorsizes to create effectiveresistances of the requiredratio Effective resistance ofpulldown network must becomputed in worst case—series n-types means largertransistorsVi+VddM2VoM1

NMOS LogicPseudo-NMOS Transistor Ratio Calculation MOSFET sizing is important Need to have reasonable W/L ratios for circuit to workcorrectly V OL>VSS but must be low enough to turn off/on nextMOSFET in the chain Static current drain when “on” Vout is a function of the number of parallel and series Nchannels in the pull down network

NMOS LogicPseudo-NMOS Transistor Ratio CalculationFor single supplyVOH= Vdd, For the worst case one NMOS to be on2⎡V ⎤ KK ⎢ Vdd V V Vdd V⎣2 ⎦ 2OL P( − ) − ⎥ = ( − )n Tn OL TP⎡ KV = K (Vdd−V ) ⎢1− 1−K⎣OL n T 2⎢nAssuming that V = V = VV →0⇒ K

NMOS Logic Pseudo-NMOS VTC ( W/L n =1)3.02.52.0W/L p = 4V out[V]1.51.0W/L p= 20.5W/L p= 0.5W/L p = 0.25W/L p= 10.00.0 0.5 1.0 1.5 2.0 2.5V in[V]

NMOS LogicPseudo-NMOS Gates Design for unit current on output PMOS fights NMOSinputsfY

NMOS LogicPseudo-NMOS Power Pseudo-NMOS draws power whenever Y = 0• Called static power P = I•VDD• A few mA / gate * 1M gates would be a problem• This is why NMOS went extinct! Use Pseudo-NMOS sparingly for wide NORs Turn off PMOS when not in useenABCY

NMOS LogicPseudo-NMOS ( NAND) Layout ExampleOutIn1 In2 In3 In4

CMOS Logic Static CMOS Logic Family All of the circuits described in the previous sectionshave a large static power dissipation. Thisdisadvantage can be overcome by using Static CMOSLogic Family

CMOS Logic Static CMOS Logic Family NOT+VddViM2M1Vo

CMOS Logic Static CMOS Logic Family Two inputs NAND+VddM3M4YBM2AM1

CMOS Logic Static CMOS Logic Family Two inputs NOR+VddABY

CMOS Logic Static CMOS Logic Family NAND is more suitable for CMOS because by supposethe equal W/L for NMOS and PMOS transistors, thePMOS transistor has more resistance respect toNMOS, therefore it is better to design circuit byparalleling the PMOS and cascading the NMOS The better Technology for digital circuit is N-Well,because in this Technology the NMOS transistors aremade in the Sub. Which result better characteristic fortransistor

CMOS LogicRealization of More Complicated Gate Circuits a) Y = A(B+C) It can be implemented in three levels:• Gate Level• Transistor Level• Layout Level

CMOS LogicRealization of More Complicated Gate Circuits a) Y = A(B+C)• Gate Level– It consists of 10 transistors, 4 transistors for NOR, 2 for NOT and 4 forNANDBCAY

CMOS LogicRealization of More Complicated Gate Circuits a) Y = A(B+C)• Transistor Level– It need only 6 transistorsAB+VddCYABC

CMOS LogicRealization of More Complicated Gate Circuits a) Y = A(B+C)• Layout Level– By proper construction of layout, the parasitic capacitors are alsoreduced and area can be saved

CMOS LogicRealization of More Complicated Gate Circuits b) XNOR (Y = AB + AB)• Gate Level– 16 transistors are neededAYB

CMOS LogicRealization of More Complicated Gate Circuits b) XNOR (Y = AB + AB)• Transistor Level (1)» How many transistors are» needed?+VddABBAY = AB+ABBBAA

CMOS LogicRealization of More Complicated Gate Circuits b) XNOR• Transistor Level (2)– Previous circuit can besimplified by eliminatingtwo wiring linesAB+VddBAY = AB+ABBABA

CMOS LogicRealization of More Complicated Gate Circuits b) XNOR• Transistor Level (3)– In this circuit we havestatic power dissipationin the state of (A=0,B=1)or (A=1,B=0)+VddM3Y = AB+ABM1M2AB

CMOS LogicRealization of More Complicated Gate Circuits b) XNOR• Transistor Level (4) (For less dissipation)– Note to the state of A = B = VddABY+Vdd000VddVdd0M4M3Y = AB+ABVdd00M1M2VddVddVdd-VthAB

CMOS LogicRealization of More Complicated Gate Circuits c) XOR• As Previous the Source and Drain of M3 (or M4) arereplaced by each other in different states, for example instate of A=0, B=0 the b connection of M3 is SourceABY+ Vdd000VddVthVdd-VthAM2BaM3Y = AB+ABa b bVdd0VddM1M4VddVdd0A

CMOS LogicRealization of More Complicated Gate Circuits d) Tri-State Outputs• A floating state at the output is needed– Non-Inverting⎧En = 1 ⇒ Y = D⎨⎩En = 0 ⇒ Y = Hi −ZEn+VddDEnYDY

CMOS LogicRealization of More Complicated Gate Circuits d) Tri-State Outputs• A floating state at the output is needed– Inverting⎧⎪ En = 1 ⇒ Y = Hi −Z⎨⎪⎩ En = 0 ⇒ Y = DD YEnEn+VddYD

CMOS LogicRealization of More ComplicatedGate Circuits e) Schmitt Trigger• M3 and M6 have minimum sizedgeometries• With Vin = 0 , the transistors M1 andM2 will be on but conductingnegligible Drain current since M4and M5 are offVinVxVy+VddM1M3M2Y⇒Vy ≈Vx ≈ VddM4Vy ≈ Vdd ⇒M6 ≅on ⇒ Vz = Vy −VTNVzM6M5+Vdd

CMOS LogicRealization of More ComplicatedGate Circuits e) Schmitt Trigger• When Vin rise to V TN, M5 turns on,but M4 is off. M5 and M6 form anNMOS amplifier. Thus as Vin rises,Vz is falling and in the certainvoltage M4 turns on. With both M4and M5 conducting, Vy rapidly goesto zero turning off M6. With Vy=0, M3turns on, which aids in turning offM2 as Vx goes from Vdd to Vy-V TP• As Vin decrease from Vdd to zerothe operation is essentially similar.But now M1 turns on, in differentvoltage and …VinVxVyVz+VddM1M3M2M4M6M5Y+Vdd

CMOS LogicTransmission Gates Family Use pass transistors like switches to do logic Inputs drive diffusion terminals as well as gates N transistors instead of 2N No static power consumption Ratioless Bidirectional

CMOS LogicTransmission Gates Family NMOS Only SwitchVddXIn3.0InVoltage [V]2.01.0Outx0.00 0.5 1 1.5 2Time [ns]

CMOS LogicTransmission Gates FamilyNMOS Only Switch• V Bdoes not pull up to 2.5V, but 2.5-V TN• Threshold voltage loss causes (M 2may be weaklyconducting forming a path from Vdd to GND)• NMOS has higher threshold than PMOS (body effect)

CMOS LogicTransmission Gates FamilyNMOS Only Switch• Pass transistor gates should never be cascaded as onthe left• Logic on the right suffers from static power dissipationand reduced noise margins

CMOS LogicTransmission Gates Family NMOS Only Switch• Solution1: Level Restoring TransistorLevel RestorerBV ddM rV ddM 2AMnXOutM 1

CMOS LogicTransmission Gates FamilyNMOS Only Switch• Solution1: Level Restoring TransistorAdvantages• Full swing on x (due to Level Restorer) so no static powerconsumption by inverter• No static backward current path through Level Restorer and PTsince Restorer is only active when A is high• Restorer adds capacitance, takes away pull down current at XFor correct operation Mr must be sized correctly (ratioed)

CMOS LogicTransmission Gates Family NMOS Only Switch• Solution2: Multiple V T Transistorslow V TtransistorsIn 2 = 0VA= 2.5VonOutIn 1 = 2.5Voff butleakingB= 0Vsneak path

CMOS LogicTransmission Gates FamilyNMOS Only Switch• Solution2: Multiple V T Transistors Technology solution: Use (near) zero V Tdevices for theNMOS TGs to eliminate most of the threshold drop (bodyeffect still in force preventing full swing to Vdd) Impacts static power consumption due to subthresholdcurrents flowing through the TGs (even if VGS is below V T)In 2 = 0VA= 2.5Vonlow V TtransistorsOutIn 1 = 2.5Voff butleakingB= 0Vsneak path

CMOS Logic Transmission Gates Family NMOS Only Switch• Disadvantage:– It can be bad because the signal can be degraded– We do not allow a few gates in series for one signal (Pure TG logicis not regenerative, the signal gradually degrades after passingthrough a number of TGs)• Advantage:– Allow us to save transistor or less stage of logicAZB

CMOS Logic CMOS Transmission Gates Family PMOSAYC CMOSCCAYAYCC

CMOS LogicCMOS Transmission Gates Family There are many symbols for transmission gateBBBAZAZAZORB'BOOKB'MEAB'Z Be careful, because it is bi-directional

CMOS LogicCMOS Transmission Gates FamilyThis circuit performs a function similar to that of the well known diode bridgeC = Vss, C = 0 ⇒ Both transistor are on ⇒ A = YThe input voltage VA (which must be between Vss and Vdd) is thenconnected to the output through the parallel on resistance of the channels ofthe two transistors. As VA approaches Vdd, the N-channel device cuts off butthe P-channel device remains non saturated, as VA approaches Vss, the P-channel device cuts off but the N-channel device remains non saturated.Therefore there is always a non saturated transistor between input and outputCCA YA YCC

CMOS LogicCMOS Transmission Gates Family For more understanding note to this circuit We assume:−Vy(0 ) = 0, C = Vdd, C = 0, V < Vdd −VTPTNVACVddVyASDI PI NYCLtC

CMOS LogicCMOS Transmission Gates Family⎧N= sat0 ≤ t ≤ t ⇒ I I IVy=V⎨ ⇒ = +TP⎩P= satCL N P⎧N= satt ≤ t ≤ t ⇒ rVy VPCL= TPVy= Vdd−V⎨ ⇒τ≈TN⎩P= triode⎧N= offt ≤ t ≤ t ⇒ rVy Vdd VPCL= − TNVy=Vdd⎨ ⇒τ≈⎩P= triodeACI PI NCYCL

CMOS LogicCMOS Transmission Gates Family It is normally assumed as a resistorV (t)A=Vddu(t)C⎡ ⎛ −t⎞⎤Vy(t) = Vdd ⎢1 −exp⎜⎟⎥u(t)⎢⎣⎝τTG⎠⎥⎦τ = R CLTGTGR = r rTG N PAI PI NCYCL

CMOS LogicCMOS Transmission Gates Family r Nand r Pare approximately as follow (In saturation region)rrANN 2N(Vdd − VTN)APP 2P(Vdd − VTP)A≈ β≈ β2V2VV is Early VoltageRrPVTPRTG = rN rPr NVdd − VTNVddVy

CMOS LogicCMOS Transmission Gates Family What to note about TG• The inputs must be able to give high current because they areconnected directly to Drain and Source of transistors• Since each input is connected to an RC circuit, The delay canbe considered directly• Limited Fan-in• Excessive Fan-out• Noise vulnerability (not restoring)• Supply voltage offset/bias vulnerability• Poor high voltage levels if NMOS-only• Body effect

CMOS LogicCMOS Transmission Gates FamilyRules of Thumb• Pass-Logic may consume half the power of static logic. But becareful of V T drop resulting in static leakage• Pass-Gate Logic is not appropriate when long interconnectsseparate logic stages or when circuits have high Fan-out load(use buffering)

CMOS LogicCMOS Transmission Gates FamilyAND

CMOS LogicCMOS Transmission Gates Family ORY = A+ AB = (A+ A)(A+ B) = A+BAAABAABYWired OR

CMOS LogicCMOS Transmission Gates Family MUX⎧A S = 1Y = ⎨⎩B S = 0SABSYS

CMOS LogicCMOS Transmission Gates Family MUXF = (In1S+In2S)S S FV ddIn 1 In 2GNDSS

CMOS LogicCMOS Transmission Gates Family XORBABY = A⊕BB

CMOS LogicCMOS Transmission Gates Family XNORBABY = AB+ABB

CMOS LogicCMOS Transmission Gates Family D Latch1) Load Q = D2) Hold Q = Qnnn n-1DLDQQLDDLDLDQLD

CMOS LogicCMOS Transmission Gates Family D Latch1) Load LD = 1D Q = DD=Q2) Hold LD = 0QQ

CMOS LogicCMOS Transmission Gates Family D Latch (Simpler Realization)• If in Load Mode a level voltage opposite to the output of weakinverter is applied to the input by TG, Q = D and weak inverteris not damaged!LDDQLDQWeak Inverter

CMOS Logic Delay in Transmission GateInV1V2ViVi + 1V n−1C C C C C CV nInReqRV eq1V2ReqV eq eqiVi + 1V n−1C C C C C CRRReqV nInm644474448ReqReqReqReqReqReqC C C C C C

CMOS LogicDelay Optimization Delay of RC chainn∑t = 0.69 C R k = 0.69C RP eq eqk=1 Delay of Buffered chainn(n + 1)2⎡ n m(m+1) ⎤ ⎛ n ⎞tP= 0.69 ⎢ C Re q1 tbufm 2⎥+ ⎜ −m⎟⎣ ⎦ ⎝ ⎠⎡ n(m + 1) ⎤ ⎛ n ⎞= 0.69 ⎢C Re q1 tbuf2⎥+ ⎜ −m⎟⎣ ⎦ ⎝ ⎠tPbufmopt= 1.7 CReq

CMOS LogicTG Points to Remember Stored charge leaks away due to reverse-bias leakagecurrent Stored value is good for about 1 ms Value must be rewritten to be valid If not loaded every cycle, must ensure that latch isloaded often enough to keep data valid Capacitance comes primarily from inverter’s gate logic

CMOS LogicTG Layout

CMOS LogicTG Properties Strong pull-up Strong pull-down May be difficult to design into a circuit (layout) becauseof close proximity of N and P devices (design ruleseparation) Always requires 2N transisitors for any N x TG design Many logic functions (multiplexers in particular) areeasily implemented using TG based designs

CMOS LogicComplementary Pass-transistor Logic (CPL) orDifferential (+) TG Logic Dual-rail form of pass transistor logic Avoids need for ratioed feedbackAABBAABBPT NetworkInverse PTNetworkFFFFABABSSSSLLYY

CMOS LogicCPLBBABABAND/NAND

CMOS Logic4 Input NAND in CPL

CMOS LogicCPL Advantages Differential so complementary data inputs and outputsare always available (so don’t need extra inverters) Still static, since the output defining nodes are alwaystied to Vdd or GND through a low resistance path Design is modular, all gates use the same topology,only the inputs are permuted Simple XOR makes it attractive for structures likeadders Fast (assuming number of transistors in series is small)

CMOS LogicCPL Disadvantages Additional routing overhead for complementary signals Still have static power dissipation problems V OH is very weak! Then we need an inverter at theoutput

CMOS LogicDifferential Cascode Voltage Switch Logic (DCVSL)Compute both true and complementary outputs using a pair ofcomplementary NMOS pull-down network The PMOS transistors are driven by the output of thecomplementary network No static power consumption Fast responseYYInputsff

CMOS LogicDifferential Cascode Voltage Switch Logic (DCVSL) Example: NAND/ANDY=ABY= A+BABA⎫⎬SeriesB⎭

CMOS LogicDifferential Cascode Voltage Switch Logic (DCVSL) General DesignA00001111B00110011C01010101F10010111CBA0 1_+_+_+_+_+_+_+

CMOS LogicDifferential Cascode Voltage Switch Logic (DCVSL) General Designababx_+≡xxx_+≡uu = ax+bxuuuabababx_+_+≡x_+u 1u 2u 1u 2

CMOS LogicDifferential Cascode Voltage Switch Logic (DCVSL) General Design0 1C0 1_+_+_+_+C_+_+BA_+_+_+BA_+__++

CMOS LogicDifferential Cascode Voltage Switch Logic (DCVSL) Example: XOR/XNOR

CMOS LogicRules of ThumbStep-up (alpha) ratio of 2.7 (“e”) produces minimum powerdelayproductP vs. N (beta) ratio of 2 balances pull-up and pull-downtimes and noise marginsApproximately 75% of static logic are NAND stacks (limitstack to 3-4, use ordering and tapering for speed)Glitches consume approximately 15% of overall chip powerCrossover (short-circuit) current consumes ~ 10% of astatic chip’s total power (but is a function of input/outputslews, ie sizing)

Summary This lecture describes the basic MOS LogicGates which require no clock or other periodicsignal for operation and also implementation ofthem in three following levels Gate Level Transistor level Layout Level

Contents Introduction Dynamic CMOS Logic CMOS Domino Logic CD Domino Logic Dynamic CVSL Sample-Set Differential Logic (SSDL) Summary

IntroductionAs mentioned before Digital MOS circuits can be classifiedinto two categories: Static Circuits: require no clock or other periodic signal foroperation (except sequential logic). In these circuits at everypoint in time (except when switching) the output is connectedto either GND or Vdd via a low resistance path fan-in of N requires 2N devices (n N-type + n P-type) Dynamic Circuits: require periodic clock signals, synchronizedwith data signals, for proper operation even in combinationallogic. These circuits rely on the temporary storage of signalvalues on the (parasitic) capacitance of high impedance nodes requires only N + 2 transistors (n+1 N-type + 1 P-type) takes a sequence of precharge and conditional evaluationphases to realize logic functions

IntroductionWhy Dynamic Logic?In the area of high speed, higher Fan-in, extremely lowpower dissipation, other digital logic circuit have beenconsidered. In this lecture, two of these alternatives toCMOS are described. The circuits are basically NMOS orCMOS Gates with slight improvements. These are: Dynamic CMOS Logic CMOS Domino LogicEach of them have specific operating advantages overNMOS or CMOS, but exhibit disadvantages in other areas

Dynamic CMOS LogicDynamic Gates use a clocked PMOS pullupTwo modes: precharge and evaluateφ Precharge EvaluatePrechargeY

Dynamic CMOS LogicThe Foot What if pulldown network is ON during precharge? Use series evaluation transistor to prevent fightφAYprecharge transistorfoot

Dynamic CMOS LogicDynamic CMOS Logic To make the gate dynamic, aclock pulse is applied to the gateof complementary P and Nchannel devices. This gateconsists of an NMOS Logic circuitwhose output node is prechargedto Vdd by the PMOS, when theclock is zero. The output node isdischarged by the NMOStransistor connected to groundwhen the clock is highCLKP CLKNMOSLogicCircuitN CLK

Dynamic CMOS LogicDynamic CMOS LogicM p1L23M ePrecharge (Clk = 0)Evaluate (Clk = 1)

Dynamic CMOS LogicOnce the output of a dynamic gate is discharged, it cannotbe charged again until the next precharge operationInputs to the gate can make at most one transition duringevaluationOutput can be in the high impedance state during and afterevaluation (PDN off), state is stored on C L

Dynamic CMOS LogicCanonical Forms

Dynamic CMOS LogicProperties of Dynamic Gates Logic function is implemented by the PDN only• should be smaller in area than static complementary CMOS Full swing outputs (V OL= GND and V OH= V DD) Nonratioed - sizing of the devices is not important for properfunctioning (only for performance) Faster switching speeds• reduced load capacitance due to lower number of transistors pergate (C int ) so a reduced logical effort• reduced load capacitance due to smaller fan-out (C ext )• no I sc , so all the current provided by PDN goes into dischargingC L• Ignoring the influence of precharge time on the switching speedof the gate, t pLH = 0 but the presence of the evaluation transistorslows down the t pHL

Dynamic CMOS LogicProperties of Dynamic Gates Power dissipation should be better• consumes only dynamic power – no short circuit powerconsumption since the pull-up path is not on when evaluating• lower C L - both C int (since there are fewer transistors connectedto the drain output) and C ext (since there the output load is oneper connected gate, not two) But power dissipation can be significantly higher due to• higher transition probabilities• extra load on CLK PDN starts to work as soon as the input signals exceed V Tn,so set V M, V IHand V ILall equal to V Tn• low noise margin (NM L ) Needs a precharge/evaluate clock

Dynamic CMOS LogicLeakage Sources Subthreshold conduction Transistors can’t abruptly turnON or OFF Reverse-biased PN junctiondiode current• I sdepends on doping levels And areaand perimeter of diffusion regions,typically < 1 fA/µm 2 Gate Leakage• Carriers may tunnel thorough very thingate oxides• Negligible for older processes10 9 t ox10 6 V DD trend0. 6 nm0. 8 nm10 31. 0 nm1. 2 nm10 010 -310 -610 -90 0.3 0.6 0.9 1.2 1.5 1.8V DD1. 5 nm1. 9 nm

Dynamic CMOS LogicLeakage SourcesOutput settles to an intermediate voltage determined by a resistivedivider of the pull-up and pull-down networksOnce the output drops below the switching threshold of the fan-outlogic gate, the output is interpreted as a low voltage2.5CLKVoltage (V)1.50.5Out-0.50 20 40Time (ms)

Dynamic CMOS Logic Leakage Sources Subthreshold leakage is dominant in modern transistorsCLKpLeV OutPrechargeEvaluateLeakage sources

Dynamic CMOS Logic Solution to Charge LeakageM p M kpLM e

Dynamic CMOS LogicCharge SharingCharge stored originally on CY is redistributed (shared) over CXleading to static power consumption by downstream gates andpossible circuit malfunctionWhen ∆Vout = - Vdd (CX / (CX + CY )) the drop in Vout is largeenough to be below the switching threshold of the gate it drivescausing a malfunctionφφAB = 0xC xxYC YYACharge sharing noiseCYV = V = VC + Cx Y ddx Y

Dynamic CMOS LogicSolution to Charge Redistribution Add secondary precharge transistors (at the cost ofincreased area and power)• Typically need to precharge every other node• Secondary precharge transistors should be small because theirdiffusion capacitance slows the evaluation (increase delay)• Big load capacitance C Y helps as wellABxYsecondaryprechargetransistor

Dynamic CMOS LogicCharge Sharing Example What is the worst case voltage drop on y? (Assume allinputs are low during precharge and that all internal nodesare initially at 0V)

Dynamic CMOS LogicCharge Sharing Example⎡⎣( a c) ( a c y)( ( ))∆ Vout = − Vdd C + C C + C + C=− 2.5V 30 30 + 50 =−0.94V⎤⎦CLKy = A B CLoadinverteraAAC y =50fFyC a =15fFB B BcbBdC b =15fFC c =15fFCCC d =10fFCLK

Dynamic CMOS Logic Backgate Coupling Susceptible to crosstalk due to• High impedance of the output node• Capacitive coupling– Out2 capacitively couples with Out1 through the gate-source and gatedraincapacitances of M4CLKA=0B=0CLKM pM 1M eC L1Out1 =1M 6M 2M 3M 4M 5C L2Out2 =0InDynamic NANDStatic NAND

Dynamic CMOS Logic Backgate Coupling Capacitive coupling means Out1 drops significantly so Out2doesn’t go all the way to ground3Due to clk feedthroughVoltage21ClkOut1Due to backgate0InOut2-10 2 4 6Time, ns

Dynamic CMOS Logic Clock Feedthrough A special case of capacitivecoupling between the clockinput of the precharge transistorand the dynamic output nodedue to the gate to draincapacitance So voltage of Out can rise aboveVdd. The fast rising (and fallingedges) of the clock couple toOutM pM eL

Dynamic CMOS Logic Clock FeedthroughClock feedthrough2.51.5Voltage0.5In &ClkOut-0.50 0.5 Time, ns 1Clock feedthrough

Dynamic CMOS Logic Other Effects Capacitive coupling Substrate coupling Minority charge injection Supply noise (Ground bounce) Floating output nodes

Dynamic CMOS Logic Floating output nodes Solutions:• Only connect to gates• Add staticizer to refresh the charges00s

Dynamic CMOS LogicAdvantages:For n inputs, dynamic logic requiresn+2 transistorshave small area, high speed andcompact layoutsCLKP CLKDisadvantages:Circuit operation is more complexdue to the required clockThe inputs can only change duringthe precharge phase and must bestable during the evaluate portion ofthe cycleNMOSLogicCircuitN CLKNeed Monotonicity• can not be cascaded

Dynamic CMOS LogicMonotonicity Dynamic gates require monotonically rising inputsduring evaluationAviolates monotonicityduring evaluationφφ Precharge EvaluatePrechargeAYOutput should rise but does not

Dynamic CMOS LogicMonotonicity Woes Dynamic gates produce monotonically falling outputs duringevaluation Illegal for one dynamic gate to drive another!A 1 =PrechargeEvaluatePrechargeXX monotonically falls during evaluationYY should rise but cannot

Dynamic CMOS Logic CascadingVClkInOut1V TnOut2∆VOnly 0 → 1 transitions allowed at inputs!t

Dynamic CMOS Logic Cascading Input going from high to low during evaluation• a is 5V when precharge b = 5V, c = 5V• During evaluation:– Wanted: b 0V, c 5V– But, b takes some time to drop to 0V– Consequently, c may fall to some unknown value Solution NP-CMOS NORA Logic Domino logicabc

Dynamic CMOS Logic NP-CMOS Only 0 → 1 transitions allowed at inputs of PDN Only 1 → 0 transitions allowed at inputs of PUNClkIn 1In 2In 3ClkM pPDNM e1 11 0Out1ClkIn 4In 5ClkM eM pPUN0 00 1Out2(to PDN)

Dynamic CMOS Logic NORA Logic WARNING: Very sensitive to noise!ClkIn 1In 2In 3ClkM pPDNM e1 11 0Out1ClkIn 4In 5ClkM eM pPUN0 00 1Out2(to PDN)to otherPDN’sto otherPUN’s

Dynamic CMOS LogicAn example

Dynamic CMOS Logic Dynamic 4 Input NAND GateV DDOutIn 1In 2In 3In 4φGND

Dynamic CMOS LogicPower Consumption Power only dissipated when previous Out = 0p1L23e

Dynamic CMOS LogicPower Consumption Dynamic Power Consumption is Data Dependent• Assume signal probabilities (Dynamic 2-input NOR Gate)• P A=1 = 1/2• P B=1 = 1/2A B Out• Then transition probability• P 1→0 = P out=0 = ¾0 0 1011101000Switching activity can be higher in dynamic gates!

Dynamic CMOS LogicRules of ThumbDynamic logic is best for wide OR/NOR structure (e.g. bitlines),providing 50% delay improvement over static CMOSDynamic logic consumes 2x power due to its phase activity(unconditional pre-charging), not counting clock power

Dynamic CMOS Logic Notes No need to implement the complement of the function,leading to smaller area We can avoid the long PMOS chains Handle the charge sharing problem and floating outputnodes Input transistors should not change from on to offduring evaluation

CMOS Domino LogicIt is an extension of dynamic CMOS gates that allowcascading of stagesThe simple modification entails incorporating a staticCMOS inverter at the output of each logic gateIn 1In 2ClkM pPDN1 11 0Out1Clk0 00 1In 4M p M kpPDNOut2ABdomino ANDWX Y ZCIn 3In 5φClkM eClkM edynamicNANDstaticinverter

CMOS Domino Logic Stage A should be precharged in Φ 1 and evaluate in Φ 2 Stage B should be precharged in Φ 2 and evaluate in Φ 1

CMOS Domino LogicDuring precharge (clk=0), the output node of the dynamicgate is precharged high and the output node of the CMOSinverter is low. Then subsequent stages will be turned offduring the precharge phaseWhen the clk=1, the output of the driving gate willconditionally discharge, allowing the output of the inverterto conditionally go high. Each connected gate output canthen make a transition from low-to-high, in sequenceThere is no restriction on the number of logic stages thatcan be cascaded provided that all stages can evaluateduring one clock pulse

CMOS Domino Logic pc = Φ 1 and ev = Φ 2pcpc = 1 ev = 2cycleVWn- networkXY11ev22prechargeinput latchedhereevaluateoutput latchedhere

CMOS Domino Logic Won’t work! If pc = Φ 2 and ev = Φ 1pc = 2 ev = 1cycle12evaluateprechargeinput latchedhereevaluateoutput latchedhereprecharge

CMOS Domino Logic Why Domino? Like falling dominos!

CMOS Domino LogicProduces monotonic outputsφ Precharge EvaluatePrechargedomino ANDWWX Y ZXABCYφZdynamicNANDstaticinverterABφWHCXφYHφA XZ = BCφZ

CMOS Domino LogicDomino OptimizationsEach domino gate triggers next one, like a string of dominos topplingoverGates evaluate sequentially but precharge in parallel Thus evaluationis more critical than prechargeHI-skewed static stages can perform logicStatic inverter can be optimized to match fan-outφS0S1S2S3D0D1D2D3φHYS4S5S6S7D4D5D6D7

CMOS Domino LogicLeakage Dynamic node floats high during evaluation• Transistors are leaky (I OFF ≠ 0)• Dynamic value will leak away over time• Formerly miliseconds, now nanoseconds! Use keeper to hold dynamic node• Must be weak enough not to fight evaluationweak keeperφA1 k2XHY2

CMOS Domino LogicNoise Sensitivity Dynamic gates are very sensitive to noise• Inputs: V IH≈ V tn• Outputs: floating output susceptible noise Noise sources• Capacitive crosstalk• Charge sharing• Power supply noise• Feedthrough noise• And … !

CMOS Domino Logic Designing with Domino LogicIf all the inputs come from other domino gates, then all the inputs will be lowduring the precharge. You don’t need to explicit evaluate transistorNeed to be a little careful. When precharge begins, the first gate’s output mustprecharge before the next gate can precharge. Both evaluate and prechargeripple in this scheme. But, if there is already a tall stack, transistor ratioing willlet precharge win anyway. (but you waste power until the precharge ripples)

CMOS Domino Logic Example During precharge, x, y, z = 1, x, y = 0 During evaluation, x = 0 when a = b = 1 Therefore, z = abcdaxxyyzbcd

CMOS Domino LogicAdvantages: Large Fan-in, fewer transistors (n+4 transistors, whereas CMOSrequires 2n) Single clock can be used to precharge and evaluate all stages at thesame time It is attractive for high-speed circuits 1.5 – 2x faster than static CMOS Widely used in high-performance microprocessorsDisadvantages: Each logic block must incorporate a separate inverter Each block performs only non-inverting logic Monotonicity Leakage Charge sharing Noise

CMOS Domino LogicDual Rail DominoDomino only performs noninvertingfunctions• AND, OR but not NAND, NOR, or XORDual-rail domino solves this problem• Takes true and complementary inputsY_linputsfφφfY_h• Produces true and complementaryoutputssig_h0011sig_l0101MeaningPrecharged‘0’‘1’invalid

CMOS Domino LogicExample AND/NAND Given A_h, A_l, B_h, B_l Compute Y_h = A * B, Y_l = ~(A * B)Pulldown networks are conduction complementsY_l= A*BφA_hY_h= A*BA_lB_lB_hφ

CMOS Domino LogicExample XOR/XNOR Sometimes possible to share transistorsY_l= A xnor BA_hA_lφA_lA_hY_h= A xor BB_lB_hφ

CMOS Domino LogicRules of ThumbTypical domino keepers have W/L = 5-20% of effective widthof evaluate treeTypical domino output buffers have a beta ratio of ~ 6:1 topush the switch point higher for fast rise-time

CD Domino Logic We noted that dynamic inputs never make 1 to 0transitions while in evaluation Two solutions: Precharge outputs low using an inverting gate(standard domino) Delay the evaluate clock until inputs settle (CDdomino)

CD Domino Logic Self-timed dynamic logic family Consists of a dynamic gate, and an optionaldelay element for the clock signalMpreOut = a+babclk(i)Mevaldelayclk(i+1)

CD Domino Logic Advantages Uses single-rail circuits, rather than dual-rail forstandard domino Provides both inverting and non-inverting functions High-speed, large fan-in NOR and OR circuits

CD Domino Logic Delay Matching CD domino requires delay matching between theslowest dynamic gate at a level and a delay element A 20% margin is typically added to the delay of thefixed delay element to account for PVT variations Thus, 20% of the speed gain possible with CD dominois not realized Average speed gain of (60+20)% is theoreticallypossible Use digitally programmable delay elements(PDEs) to reduce the margin and attain a speedimprovement without affecting the reliability inthe presence of variations

CD Domino Logic Clocking Scheme The circuits are fully levelized The delay element on each level is tuned to theslowest gate at its level, plus a 20% margin(other gates).dynamicgate(other gates).dynamicgate(other gates).dynamicgateprimaryinputsdynamicgatedynamicgatedynamicgateclk1 fixed delayclk2 fixed delayclk3 fixed delayclk4gate levelgate levelgate level123

Dynamic CVSLPositive feedback does not existFFCIn {NMOSLogic Array}InC

Sample-Set Differential Logic (SSDL)It is one type of Dynamic CVSL with positive feedbackBy this logic the low level output is guaranteed to zero inevaluation phaseFCCFIn {NMOSLogic Array}In

Summary This lecture describes many basics CMOS LogicGates which require clock or other periodicsignal for operation These circuits rely on the temporary storage ofsignal values on the (parasitic) capacitance ofhigh impedance nodes