<strong>24AA32A</strong>/<strong>24LC32A</strong>3.6 Device AddressingFIGURE 3-2:CONTROL BYTE FORMATA control byte is the first byte received following theStart condition from the master device (Figure 3-2).The control byte consists of a four-bit control code. Forthe 24XX32A, this is set as ‘1010’ binary for read andwrite operations. The next three bits of the control byteare the Chip Select bits (A2, A1, A0). The Chip Selectbits allow the use of up to eight 24XX32A devices onthe same bus and are used to select which device isaccessed. The Chip Select bits in the control byte mustcorrespond to the logic levels on the corresponding A2,A1 and A0 pins for the device to respond. These bitsare in effect the three Most Significant bits of the wordaddress.The last bit of the control byte defines the operation tobe performed. When set to a ‘1’, a read operation isselected. When set to a zero, a write operation isselected. The next two bytes received define theaddress of the first data byte (Figure 3-3). Becauseonly A11 to A0 are used, the upper four address bits are“don’t care” bits. The upper address bits are transferredfirst, followed by the Less Significant bits.Following the Start condition, the 24XX32A monitorsthe SDA bus checking the device type identifier beingtransmitted and, upon receiving a ‘1010’ code andappropriate device select bits, the slave device outputsan Acknowledge signal on the SDA line. Depending onthe state of the R/W bit, the 24XX32A will select a reador write operation.SStart BitControl Code1 0 1 0 A2 A1 A0Slave AddressRead/Write BitChip SelectBitsR/WAcknowledge Bit3.7 Contiguous Addressing AcrossMultiple DevicesACKThe Chip Select bits A2, A1 and A0 can be used toexpand the contiguous address space for up to 256Kbits by adding up to eight 24XX32A devices on thesame bus. In this case, software can use A0 of the controlbyte as address bit A12; A1 as address bit A13; andA2 as address bit A14. It is not possible to sequentiallyread across device boundaries.FIGURE 3-3:ADDRESS SEQUENCE BIT ASSIGNMENTSControl Byte Address High Byte Address Low Byte1 0 1 0A2A1A0 R/W x x x xA11A10 A 9A A A8 7• • • • • • 0ControlCodeChipSelectBitsx = “don’t care” bitDS21713F-page 6© 2005 Microchip Technology <strong>Inc</strong>.
<strong>24AA32A</strong>/<strong>24LC32A</strong>4.0 WRITE OPERATIONS4.1 Byte WriteFollowing the Start condition from the master, thecontrol code (4 bits), the Chip Select (3 bits), and theR/W bit (which is a logic low) are clocked onto the busby the master transmitter. This indicates to theaddressed slave receiver that the address high bytewill follow once it has generated an Acknowledge bitduring the ninth clock cycle. Therefore, the next bytetransmitted by the master is the high-order byte of theword address and will be written into the AddressPointer of the 24XX32A. The next byte is the LeastSignificant Address Byte. After receiving anotherAcknowledge signal from the 24XX32A, the masterdevice will transmit the data word to be written into theaddressed memory location. The 24XX32A acknowledgesagain and the master generates a Stopcondition. This initiates the internal write cycle and,during this time, the 24XX32A will not generateAcknowledge signals (Figure 4-1). If an attempt ismade to write to the array with the WP pin held high,the device will acknowledge the command, but nowrite cycle will occur. No data will be written and thedevice will immediately accept a new command. Aftera byte Write command, the internal address counterwill point to the address location following the one thatwas just written.4.2 Page WriteThe write control byte, word address and the first databyte are transmitted to the 24XX32A in the same wayas in a byte write. However, instead of generating aStop condition, the master transmits up to 31 additionalbytes which are temporarily stored in the on-chip pagebuffer and will be written into memory once the masterhas transmitted a Stop condition. Upon receipt of eachword, the five lower Address Pointer bits are internallyincremented by ‘1’. If the master should transmit morethan 32 bytes prior to generating the Stop condition, theaddress counter will roll over and the previouslyreceived data will be overwritten. As with the byte writeoperation, once the Stop condition is received, aninternal write cycle will begin (Figure 4-2). If an attemptis made to write to the array with the WP pin held high,the device will acknowledge the command, but no writecycle will occur, no data will be written, and the devicewill immediately accept a new command.Note:Page write operations are limited to writingbytes within a single physical page,regardless of the number of bytesactually being written. Physical pageboundaries start at addresses that areinteger multiples of the page buffer size (or‘page size’) and, end at addresses that areinteger multiples of [page size – 1]. If aPage Write command attempts to writeacross a physical page boundary, theresult is that the data wraps around to thebeginning of the current page (overwritingdata previously stored there), instead ofbeing written to the next page as might beexpected. It is therefore necessary for theapplication software to prevent page writeoperations that would attempt to cross apage boundary.4.3 Write ProtectionThe WP pin allows the user to write-protect the entirearray (000-FFF) when the pin is tied to VCC. If tied toVSS the write protection is disabled. The WP pin issampled at the Stop bit for every Write command(Figure 3-1). Toggling the WP pin after the Stop bit willhave no effect on the execution of the write cycle.© 2005 Microchip Technology <strong>Inc</strong>. DS21713F-page 7