2090 PCI Express

2090 PCI EXPRESSPhotos courtesy of the U.S. Air ForcePCI EXPRESS MODEL 2090 RECEIVER-TUNER IFPROCESSING, DATA ACQUISITION, PACKET PROCESSINGThe DRS 2090 PCI Express allows users to capture analogor network data into a host computer for additionalprocessing. The 2090 can be configured with various I/Oand processing modules to pre-process external data beforeit is transferred to the host. Currently the 2090 supportsthree main market areas: Analog Receiver/Tuner IF, Digital IFand Gigabit Ethernet (1 GbE and 10 GbE) data processing.Analog IF can be digitized by the 2090’s two high-resolution(16-bit) converters or the 8-bit wideband converter (up to 3gigahertz sample rate). Packetized digital IF can also becaptured and processed. IF data can be streamed to thehost or sent to a 2090 FPGA processing module foradditional processing (IF-to-BB, digital down converters,demodulators). Data reprocessing can be accomplished byDRS supplied FPGA signal processing cores or usercores/code.PCI Express Model 2090

HIGHLIGHTS• Provides high-performance data transfers betweenexternal data sources and the host computer• The card is PCIe (x8) and supports bus transfer rates upto 2 gigabytes per second in each direction• Pre-process external data to free up the host CPU forother functions• Analog/digital IF data processing• Tune, filter, decimate• High channel count digital down conversion• Full line rate 10 GbE data processingPCI EXPRESSForm factorDevice driversExample code with CAPIMemory usageUp front memory set asideA/D MODULEWideband A/DPCIe (x8)Redhat®Enterprise/FedoraProvidedScatter/gatherNone requiredNational ADC083000Wideband bits 8Wideband sample rate Adjustable up to 1.5 GHzor 3 GHzHigh-resolution A/D’s x 2 Linear tech LTC2208High-resolution bits 16High-resolution sample rate Adjustable up to 130 MHzA/D DSPIndependent tuners/IF-to-BBconvertersIF-to-BB Decimation 2, 4, 8, 16Delay buffer locationDelay buffer sizeDelay buffer minimumadjustmentTIME STAMPING A/D DATAExternal inputsTime stamp resolutionFormatReconstructionAfter IF-to-BB512 MB, expandable to1 GB128 sample increments10 MHz Ref, 1 PPS, IRIG±5 nsecTOY, plus very fine timeSample and index pointersDUAL 1 GBE/10 GBE MODULE10 GbE line rate Supports full line rate I/OTransceiversSFP (1 GbE), SFP+ (10 GbE)FiberSingle mode, 1310 nm, LCProtocolUDPPort optionsx2 1 GbE, x2 10 GbEor x3 10 GbECapture/generateIndependent on each linkFPGA MODULE DSP DRS DIGITAL DOWN CONVERTER(DDC) CORECores per FPGA 5Maximum DDC channels 320 (input BW dependent)Output channel maximum Bandwidth (BW)1.5625 MHzOutput channel CF and BW Independent for all channelsOutput channel decimation 4 - 8192, 4 - 16 mayrequire upsample modeSpecifications subject to change without notice. Copyright © DRS ICAS, LLC 2011. All Rights Reserved.Export of DRS ICAS, LLC products may be subject to U.S. Export Controls. U.S. Export licenses may be required.All trademarks and registered trademarks are the property of their respective owners.DRS ICAS, LLC.2601 Mission Point Blvd., Suite 250 Beavercreek, OH 45431 Tel: 937.429.7408 Fax 937.429.7176 www.drs-ds.com marketing@drs-ds.com(ISO 9001:Registered Company)Cleared by US DoD/OSR for Public Release under OSR case number 08-S-0543 dated 12.28.2007.Cleared for Public Release – DS FSO Dated 19 October 2011.DRS BEA V7 10/20/11