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Paper - IDAV: Institute for Data Analysis and Visualization

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16 · Lefohn, Kniss, Strzodka, Sengupta, <strong>and</strong> OwensAddrTransCitation Domains Mapping Loc MCmplx ACmplx ACons Mut? Notes[Binotto et al. 2003] 4D→2D C A GPU n 1 U Y2-level page table + hash ontime dimension1D→2D C U GPU 1 1 U N Streams: 1D-to-2D mapping[Buck et al. 2004]{1–4}D→Arrays: ND-to-1D-to-2D mappingC U GPU 1 1 U N2D[Carr <strong>and</strong> Hart 2004] 3D→2D S A CPU logn logn NU Y Quad-tree on CPU[Coombe et al. 2004] 3D→2D C A CPU logn logn NU Y Quad-tree on CPU[Foley <strong>and</strong> Sugerman2005]3D→2D C A GPU logn logn NU N Static k-d tree on GPU[Harris et al. 2003] 3D→2D C U GPU 1 1 U N 3D-to-2D page-based[Johnson et al. 2005] 2D→2D S A GPU⋆ n ∝ list size NU Y 1-level page table[Kraus <strong>and</strong> Ertl 2002]{2,3,4}D→{2,3}DS A GPU n 1 U N 1-level page table[Lefebvre et al. 2004] 3D→3D S A GPU logn logn NU N Variable-level 3D page table[Lefohn et al. 2004] 3D→2D S U CPU n 1 U Y 1-level 3D page, 2D pages[Purcell et al. 2002] 3D→2D C U GPU n ∝ list size NU Y1-level 3D page table. Grid oflists[Purcell et al. 2003] 3D→2D C U GPU n ∝ list size NU Y1-level 3D page table. Grid oflists1-level page table, 2 VQ code[Schneider <strong>and</strong> Westermann2003]3D→3D C A GPU n 1 U N book lookups, decompressionmathNon-linear warp map to de<strong>for</strong>m[Sen 2004] 2D→2D C A GPU n 1 U Yuni<strong>for</strong>m physical memoryto represent an adaptive virtualspace1-level 3D page table, 3D-to-[Tarini et al. 2004] 3D→2D S U GPU n 1 U N 3dPolyCube, 3dPolyCube-to-2D[Thrane <strong>and</strong> Simonsen2005]Static GPU bounding volume3D→2D C A GPU logn logn NU NhierarchyTable II: Characterization of previous GPU data structures expressed in terms of address translator characteristics. The purposeof this table is to identify similarities between structures <strong>and</strong> illuminate gaps in the existing body of research. For each work, wedescribe the virtual <strong>and</strong> physical address domains <strong>and</strong> the six characteristics described in Section 2.2.3. Mappings are described ascomplete or sparse (C/S) <strong>and</strong> uni<strong>for</strong>m or adaptive (U/A). The address translation column indicates if the implementation uses theCPU or the GPU to per<strong>for</strong>m the address translation (Loc), the memory complexity (MCmplx), the access complexity (ACmplx), theaccess consistency (ACons), <strong>and</strong> if the structure is updatable on the GPU (Mut). The last column provides a high-level descriptionof the data structure. ⋆ indicates “proposed”.Page tables have the disadvantage of requiring O(N) memory, where N is the size of the virtual address space;however, multilevel page tables can dramatically reduce the required memory. In fact, the multilevel page table idiomprovides a continuum of structures from a 1-level page table to a full tree. This was explored by Lefebvre et al. [2004],who began with a full tree structure <strong>and</strong> found the best per<strong>for</strong>mance was with a shallower-branching multilevel pagetable structure. Section 6.3 describes a new dynamic, multiresolution, adaptive GPU data structure that is based on apage table design.The basic address translation calculation <strong>for</strong> an N-D page table translator is shown below:✞vpn = va / pageSize // va: virtual address// vpn: virtual page numberpte = pageTable.read( vpn ) // pte: page table entryACM Transactions on Graphics, Vol. 25, No. 1, January 2006.☎

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