A 2-Slot Time-Division Multiplexing (TDM) Interconnect ... - SLIP

Outline!Motivation!TDM technique for wire sharing!System level impact!Conclusion2 SLIP 2004

Inter-clock Period Idleness (contd..)ClockACInterconnect 1EInterconnect 2A E CShared interconnect8 SLIP 2004

Source/Sink ProximitySet of sourcesSet of sinks!Sources andsinks need tobe in theneighborhood!r

Layout Example 1 – Source/Sink ProximityDriverReceiverRepeaters (Inverter pair)DriverReceiverRepeaters (Inverter pair)LatchLatchDriverReceiver2:1Mux1:2DemuxDriverclkRepeaters (Inverter pair)clkReceiverLatchLatch11 SLIP 2004

Run Length ProximitySource!TDM techniqueapplied to multiplewiresSourcedABSinkSourcedCSinkSink!d

Layout Example 2 – Run Length ProximityDriverReceiverRepeaters (Inverter pair)Driver Receiver Driver ReceiverRepeaters (Inverter pair)Repeaters (Inverter pair)LatchDriverLatchReceiver2:1Mux1:2Demux2:1Mux1:2DemuxDriverLatchclk clk clk clkLatchReceiverDriverReceiverLatchLatch13 SLIP 2004

System Level ModelTechnologyparameters(100 nm)MultilevelInterconnectNetworkDesignSimulator(MINDS)Wire lengthdistributionmodel(Rent’s rule)Chip size, #metal layers, dynamic power,max. operating frequency, interconnectdistribution on various layers15 SLIP 2004

System Level ModelLogicdescription of2-TDM networkCircuitdescription of 2-TDM techniqueTechnologyparameters(100 nm)MultilevelInterconnectNetworkDesignSimulator(MINDS)Wire lengthdistributionmodel(Rent’s rule)Chip size, #metal layers, dynamic power,max. operating frequency, interconnectdistribution on various layers16 SLIP 2004

Assumptions for Case Study!0.1µ technology!100M transistors distributed uniformly!Operating Frequency = 1.5 GHz!40% Wiring efficiency!60% Wire sharing efficiency!Rent’s exponent = 0.66!Rent’s coefficient = 4.018 SLIP 2004

Metal Layers% reduction in metal layers23.52322.52221.52120.52019.5Cut off = 400 gpCut off = 500 gpCut off = 600 gpCut off = 700 gpCut off = 800 gpCut off = 900 gpCut off = 1000 gpCut off = 1100 gpSaturation forhigher die areasOver 20%reduction inthe numberof metallayers190 1 2 3 4 5 6 7Wire-limited area (sq cm)19 SLIP 2004

Dynamic Power30% increase in dynamic power2520151050Cut off = 400 gpCut off = 500 gpCut off = 600 gpCut off = 700 gpCut off = 800 gpCut off = 900 gpCut off = 1000 gpCut off = 1100 gp15%averageincrease0 1 2 3 4 5 6 7Wire-limited area (sq cm)Interconnect elimination does not result in any power reduction20 SLIP 2004

Transistor-limited Area% increase in transistor-limited area35302520151050Average15%-20%increase intransistorlimitedarea0 200 400 600 800 1000 1200Cutoff length (in gatepitches)No increase in the die area !!6 sq.cm5 sq.cm4 sq.cm3 sq.cm21 SLIP 2004

Test Case30Area = 3 sq. cm.25% change20151050Metal layersreductionDynamic powerincreaseTransistor-limitedarea increase0 200 400 600 800 1000 1200 1400Cut off length (in gatepitches)Need to select an balanced design point where– Significant decrease in #metal layers– Marginal increase in dynamic power22 SLIP 2004

Results! Wire-limited area = 3 sq.cm! Cut-off length = 900 gatepitchesDesignmetricConventionalcaseAfter TDM isappliedMetal layers8.346.64Dynamicpower68.03 W72.81 WTransistorlimitedarea1.18 sq. cm.1.3 sq. cm.! 20.38% decrease in number of metal layers! 7.02% increase in dynamic power! 10.16% increase in transistor limited-area23 SLIP 2004

Conclusion!Simple wire sharing technique proposed!Takes advantage of the interconnectidleness!Over 20% reduction in the number of metallayers!15% average increase in the dynamic power24 SLIP 2004

Future Work!Circuit Level Analysis!Wire sharing efficiency!Impact of inter-clock period idleness onmicroarchitecture25 SLIP 2004