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How is NanotechnologyChanging the ElectronicsIndustry?NACK Centerwww.nano4me.org

The NACK Center was established at the PennsylvaniaState College of Engineering, and is funded in part by agrant from the National Science Foundation.Hosted by MATEC NetWorks www.matecnetworks.orgNACK Centerwww.nano4me.org

Welcome to NACK’s WebinarToday’s PresenterCenter for Nanotechnology Applications and Career Knowledge (NACK)Dr. Osama AwadelkarimAssociate Director, NACKProfessor Engineering Science and Mechanics, PennState Universityooaesm@engr.psu.eduNACK Centerwww.nano4me.org

Miniaturization in Microelectronics“Physics of Semiconductor Devices”, S.M. Sze, John Wiley & Songs publishing, 1981

1961 The first planar integrated circuit (IC)300 mm waferSource : Bob Trew, NCSU1965 “Cramming more components ontointegrated circuits” by Intel Co-FounderGordon Moore.

Moore’s Law (continued)ftp://download.intel.com/museum/Moores_Law/Printed_Materials/Moores_Law_2pg.pdf

Source : Bob Trew, NCSU

Why is Nanotechnology importantto Microelectronics?*• The “push” in microelectronics is constantly toward smallertransistors. This allows faster and more devices on a chipgiving more memory and more functionality; i.e., giving newproducts to sell.• The microelectronics industry has reached more than abillion transistors on a chip! Transistors in production aresmaller than 45nm!• Today’s advanced devices require that the microelectronicsindustry uses nanotechnology everyday to make thesetransistors.*Source : S. J. Fonash, class notes, Penn State UniversityCopyright 2012 Center for Nanotechnology Education and Utilization

Why is Nanotechnology importantto Microelectronics? (ctd.)*• According to Dr. Andrew Moore (afounder of Intel) the number oftransistors on a chip doubles aboutevery 18 months.• This observation is known asMoore’s Law.• It captures the speed with whichmicroelectronics companies havebeen pushing each other to smallerand smaller transistors.Source : Bob Trew, NCSUCopyright 2012 Center for Nanotechnology Education and Utilization

Why is Nanotechnology importantto Microelectronics? (ctd.)*• The microelectronics industry is using top-downnanofabrication to make its nano-scale advancedtransistors.• All the deposition, lithography, material modification, andetching steps required by top-down fabrication meancleanrooms and very expensive equipment are required.These equipment requirements get more stringent as thetransistors get smaller.Copyright 2012 Center for Nanotechnology Education and Utilization

Fab cost ($B US)Why is Nanotechnology importantto Microelectronics? (ctd.)*• The fabrication facilities (called “fabs”)for making these transistors get moreexpensive as the transistors getsmaller.• Dr. Moore also notice a trend in thiscost. His observation was that the costof building a new fab doubled everythree years.• This observation is called Moore`sSecond law.*Source : S. J. Fonash, class notes, Penn StateMoore’s Second Law100101Doubling time~ 3 years0.11990 1995 2000 2005 2010 2015Year of ConstructionSource : Bob Trew, NCSUCopyright 2012 Center for Nanotechnology Education and Utilization

Fab cost ($B US)Microelectronics is not a silicon technology somuch as it is a lithography technology• Problem:– Device down-scaling andthe prohibitive cost oflithographyMoore’s Second Law10010Doubling time~ 3 years• Fundamental issues:– Devices todaylithographically determined(top-down fabrication)– Interconnects (can not takeup all the real estate)1by 2025- 1.5 meter wafer- 27 level metal0.11990 1995 2000 2005 2010 2015Year of ConstructionSource : Bob Trew, NCSUCopyright 2012 Center for Nanotechnology Education and Utilization

Front-End of the Line IssuesSourseGateI 3 I 4Drainn + n +I 2I 6I 1p-wellI 5Substrate• Direct tunneling and gate leakage : Thermal SiO 2 is no longer a suitable gatedielectric– Problem : as t ox decreases below 30 Å quantum mechanical tunneling acrossSiO 2 is significantly enhanced.– Solution : use of high dielectric constant (high-k) materials for the gate dielectricinstead of SiO 2 .• Potential high-k are SiN x O y , TiO 2 , SrTa 2 O 6 , ZrSiO 4 , HfO 2 , BST etc. (k HKvalues between 4 and 100).Copyright 2012 Center for Nanotechnology Education and Utilization

High-k Materials for SiO 2 in GateDielectricsCkoxoxkoxotox 3.9AGateando 8.851014F/ cmCox CHKktHKHKoGateandEffective Oxide Thickness ( EOT ) A3.9kHKtHKCopyright 2012 Center for Nanotechnology Education and Utilization

Back-End of the Line Issues• Conventional (IC generations of L > 0.25mm) passivation and multilevelmetallization use Al for the metalinterconnects and SiO 2 (TEOS) for theinterlayer dielectric (ILD).• Problems :– RC interconnect delayRCdelaym k ILD– Power consumption2CVPower 2fkILDYasuo Wada, Prospects for Single Molecule Information Processing Devices, IEEE, Vol. 89 No. 8, August 2001 Pg. 1147-1171

Solutions• Al is replaced by Cu .r Al ~ 3 - 5 Wcm and r Cu ~ 1-2 Wcm• SiO 2 is replaced by a low-k ILD : present IC generationsuse low-k polymers.

Alternatives : NewArchitectural ApproachesLinda Geppert, The Amazing Vanishing Transistor Act, IEEE Spectrum, October 2002, Vol. 39, Number 10, pg. 28-33

Alternatives : New FabricationApproaches• Many people have suggested that themicroelectronics industry has to stop using topdownnanofabrication and must move to bottom-upor hybrid nanofabrication.• If this worked, it would stop the spiraling costs ofproducing nano-scale transistors.Copyright 2012 Center for Nanotechnology Education and Utilization

New Fabrication Approaches• Two approaches have been proposed:1. Microelectronics based on nanoparticles.This has been termed nanoelectronics.2. Microelectronics based on the ultimatenanoparticles-- molecules. This has beentermed molecular electronics(moletronics).Copyright 2012 Center for Nanotechnology Education and Utilization

Nanoelectronics• Devices start small– Nanoparticles are “born” small– No need for etching– Position with self-assembly; then no need forlithography• Possible new device physics– Very small structures possible—this givesrise to quantum confinement effects– New types of devices possible* Source : S. J. Fonash class notes, Penn StateCopyright 2012 Center for Nanotechnology Education and Utilization

Moletronics• Devices start very small– Molecules are inherently small– No need for etching– Position with self-assembly; then noneed for lithography• Possible new device physics and chemistry– New types of devices possibleCopyright 2012 Center for Nanotechnology Education and Utilization

Where are we with these alternatives?• Generic solution proposed:– Use bottom-up nanofabrication (lots of selfassembly)and avoid lithography• Present state-of-the-art:– Nanowire and nanotube demonstrations– Molecular device demonstrations• Challenge:– Make complex self-assembled circuitsCopyright 2012 Center for Nanotechnology Education and Utilization

Building Blocks forNanoelectronics• Nanowires• Nanotubes• Quantum dotsCopyright 2012 Center for Nanotechnology Education and Utilization

Vapor-Liquid-Solid Growth of SiNanowiresSi-source gas flowAu catalystSiSiSubstrateMolten eutectic alloy droplet at relatively lowtemperatures (363 o C)SubstrateLiquid alloy acts as a preferred sink orcatalyst for arriving vaporcatalystSiNWSubstrateEutectic liquid become supersaturated and Siprecipitates out at a solid-liquid interfaceSubstrateNanowire grown by VLSCopyright 2012 Center for Nanotechnology Education and Utilization

(J. Appl. Phys. 103, 2008, p. 024304)Copyright 2012 Center for Nanotechnology Education and Utilization

Carbon Nanotubes• Carbon nanotubes (CNTs) belong to the fullerenefamily. Fullerenes are composed of covalently bodedC atoms arranged to form a closed, convex cage.The first of these molecules C60 was reported inNature 1985 by Rice University team (Nobel Prize1996). C60 distinctive soccer ball structureresembled architect Buckminster Fuller’s geodesicdomes winning the name “buckminsterfullerene”.• CNT is accredited to Sumio Iijima from NEC Corp. in1991.Copyright 2012 Center for Nanotechnology Education and Utilization

Carbon Nanotubes: Geometry• SWNT can be imagined to be a sheet that has been wrappedinto a seamless cylinder.• A typical SWNT diameter is 1.5 nm. It is less common thatSWNT diameter is 1 nm or less, and larger tubes are generallymore stable than small ones.• SWNTs might be hundreds of nm long (aspect ratios is on theorder of 1000) and are closed at both ends by hemisphericalcaps. Half of a C60 molecule is the correct cap for large tubes.• MWNTs are typically tens of nanometers in diameter and thespacing between the layered shells in the radial direction of thecylindrical CNT is approximately ~ 0.3 nm.Copyright 2012 Center for Nanotechnology Education and Utilization

(A) The wrapping of a graphenesheet into a seamless SWNTcylinder.(B) and (C) show the aggregation ofSWNT in a supramolecular bundles.The cross-sectional view in (C)shows that the bundles havetriangular symmetry.(D) A MWNT composed of nestedSWNTs.(E) At the macromolecular scale,bundles of SWNTs are entangles.Copyright 2012 Center for Nanotechnology Education and Utilization

Selected Characteristics ofSWNTsTypical diameterTypical lengthIntrinsic bandgap(metallic/semiconducting)Work functionResistivity at 300 K(metallic/semiconducting)1-2 nm100-1000 nm0 eV/~5 eV~ 5 eV10 -4 -10 -3 Wcm/10 WcmTypical field emission current density 10-1000 mA cm -2Thermal conductivity at 300 K 20-3000 W m -1 K -1Elastic modulus1000-3000 GPaCopyright 2012 Center for Nanotechnology Education and Utilization

Carbon Nanotube Transistor(Pt)(Pt)Tans, et al., Nature, 393, 49, 1998Martel et al., APL, 73, 2447,1998

Measurement of Interface States inSilicon NW Transistors• Charge pumping (CP) is a very powerfultechnique for measuring interface states,D it , in transistors. This is the first time amodified 3-terminal CP version (3T-CP)is applied to SiNWFETs.• Axially doped (n + -p - -n + ) SiNWs are grownusing vapor-liquid-solid methods to adiameter ~ 46 nm as determined byFESEM.• Oxide ground thermally in O 2 ambient at800 °C for 45 mins to form a uniform 8-nm thick shell.• The n + ends of the NW are aligned ontoTi/Al contacts and a surround Al gate(200 nm) is deposited.K. Sarpatwari, O. O. Awadelkarim etal., IEEE Trans. Nanotechnology, 10(4), 871 (2011)

Colloidal Synthesis of Quantum DotsVacuumArgon flowThermometerTo hoodTemperaturecontrollerpowerJ. Xu, PSU Seminar, 2008

Semiconductor Quantum Dots:Device QualityGreenQDsYellowQDsOrangeQDsRedQDs3 nm 5.5 nm 7.5 nm 8.3 nm530 nm 570 nm 590 nm 620 nmCore/ShellstructureAbsorption(nm)CdSe/ZnSCdSe/ZnSCdSe/CdS/ZnS506 546 577 600PL (nm) 527 567 589 620FWHM(nm)QY: asprepared*QY purifiedfor QD-LED*25 28 22 21CdSe/CdS/ZnS>70% >70% >70% >70%10 % 30% 40 % 35%J. Xu, PSU Seminar, 2008

Absorbance (a.u.)Photoluminescence (a.u.)Solar Cells : Hybrid Infrared NQD-PolymerPhotovoltaic Devices2AbsorbancePhotoluminescence215.0nm6.0nm7.8nm101200 1500 1800 2100Wavelength (nm)0J. Xu, PSU Seminar, 2008

Building Blocks for Moletronics• Molecules that show--– Reconfiguration– Redox reactions– Electron transport– Tunneling– Mechanical stress effectsCopyright 2012 Center for Nanotechnology Education and Utilization

Moletronics Device Fabrication• Hopefully selfassembly• Probably hybridS. M. Lindsay, “Single Molecule Electronics”, The Electrochemical Society Interface, Spring 2004

How Can We Better Serve You?Whether you are joining us live or watchingthe recorded version of this webinar, pleasetake 1 minute to provide your feedback andsuggestions.http://questionpro.com/t/ABkVkZLohwNACK Centerwww.nano4me.org

Webinar RecordingsTo access this recording and slides visitwww.matecnetworks.orgKeyword Search:“NACK Webinar Nano in Electronics”NACK Centerwww.nano4me.org

Upcoming NACK Events – 2012March 30:WebinarApril 16-19:WorkshopApril 27:WebinarMay 1-3:WorkshopBuilding a NanotechnologyWorkforceNanotechnology CourseResource I: Safety, Processes,and MaterialsNanotechnology and MaterialsHands-on Introduction toNanotechnology for EducatorsVisit www.nano4me.org for more detailsabout these and other upcoming webinars and workshops.NACK Centerwww.nano4me.org

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