Technical Note 79_17 - EISCAT

- 8 -SI GNALTh e a ddres s -load o pe r a t ion sets the f o Ll owt ng signals c t t.hcbackwiri ng:NAMEsaURCE-ACTlVELE\'E1..SINK­TERHINl\LFUNCTIONENABLE LOAD CM2 , lC23 HIGH CM, l C 2 ] DISCONNCCTw-SEQUENCERCM5ASSOURCE FOR INI'ERNALADDRESS-BUSRESETS ALLINSTR UCTION­REGIS'!'ERS AND DJ 5­ABLES THE PC SHTF'f­REGISTER-CHAI N.ENABLI::S THE APHPRO CESSOR FORLOADING ON STROBE­SIGNALENABLE LOAD CM4CM2 ,2eSLOWCM4 ,2C5DISABLES " CORRElAIDRRL'N " S IGNAL (2C9) ,AND ENABLES LOADOF RAM-MODULES 0 ,1AND 2 .ZERO PCCM4 , 287LOWCM] ,2B6SETSZEROPC-VALUE TOCARRY~ - S E Q U E N C E RCM4 ,2B8LOWCM] ,2B8DISABLES CARRY TOMICRO SEQUENCER .ADDRESS LOf.DINDICATIONC2 ,2C6HIGHCANAL A­REG.EXENTRALx - RESPCl'JSEDISABLESON CA}~Cx - RESPO:-JSEA-REGISTER0111'PlJr FOR INDICATIONOF LOlID-ADDRESS .Th e address-load o pe r a t ion activates t h e f o llowing buslines f ordistribution o f the subaddress (6 bits) :BUS NAME SOURCE-TERMINALS SINK TERNl NAISADDRESS-LOAD I CM2 ,lA27 ,28 , 19 ,20 ,21 ,22 ,81(LSBiA DDRESS-LOAD II CM2,2C9 ,lO,1l ,12,13,14(LSB)CM 3,lA2 7, 28, 19,20 ,Zl, 2 2 ( LS B )CM5,lA2 7, 28, 19,20,21 , 2 2 ( LSB )CM5,2Cl, 2, 3, 4,5,6 (LS B )FUNCTI ONCONNECT LOAD ­ADDRES S TO RAM­MODULES O . l AND2 .CONNECT LOAD­ADDRESS TO RAt-l­MODULE ] ( 8 LS BBITS)CONNECT LOAD ­ADDRESS TO RAM ­MODULE 3