ECET 365 Week 3 Quiz
1. Question : (TCO #3) Which interrupt is non-maskable? Student Answer: Software interrupt (SWI) Interrupt from a device connected to IRQ pin of HCS12 microcontroller Both A and B Interrupt by multiple devices connected to IRQ pin of HCS12 microcontroller Comments: 2. Question : (TCO #3) Which of the following interrupts has the highest priority? Student Answer: TCNT timer overflow SCI0 ATD0 ATD1 Comments: 3. Question : (TCO #3) Which selection is connected to the reset module in the HCS12 microcontroller? Student Answer: Reset pin ADC0 ADC1 None of the above Comments: 4. Question : (TCO #3) Which bit can mask a maskable interrupt? Student Answer: S bit Z bit N bit None of the above Comments: 5. Question : (TCO #3) In the HCS12 microcontroller, the address range 0xFFFE – 0xFFFF in the interrupt vector table is assigned to which of the following? Student Answer: Clock monitor fail reset ATD0 Reset COP failure reset Comments: 6. Question : (TCO #3) Freescale utilizes BDM to _____. Student Answer: check each instruction of a program individually reset CPU by setting IRQ pin to high-level logic check changes in memory and CPU register for each instruction execution Both A and C Comments: 7. Question : (TCO #3) Watch dog timer is a utility that _____. Student Answer: can reset the microcontroller whenever a program locks up. can catch errors due to memory corruption makes sure that a program does go to an unintentional infinite loop sequence Both A and B Comments: 8. Question : (TCO #3) When an interrupt occurs, _____. Student Answer: in one stage, the contents of the CPU move to RAM memory the CPU finishes executing its current instruction before it starts running an interrupt thread all interrrupts will be ignored if the I bit is zero Both A and B Comments: 9. Question : (TCO #3) Which combination is an appropriate way of setting up the PORTJ interrupt to enabled? Student Answer: Pin I of CCR = 0 Pin I of CCR = 1 Pin I of CCR = 1 and PIEJ7 = 1 Pin I of CCR = 0 and PIEJ6 = 0 Comments: 10. Question : (TCO #3) Which of the following interrupts has the highest priority immediately after a microcontroller reset? Student Answer: Reset XIRQ COP All have the same level of priority.
1. Question : (TCO #3) Which interrupt is non-maskable?
Student Answer: Software interrupt (SWI)
Interrupt from a device connected to IRQ pin of HCS12 microcontroller
Both A and B
Interrupt by multiple devices connected to IRQ pin of HCS12 microcontroller
Comments:
2. Question : (TCO #3) Which of the following interrupts has the highest priority?
Student Answer: TCNT timer overflow
SCI0
ATD0
ATD1
Comments:
3. Question : (TCO #3) Which selection is connected to the reset module in the HCS12 microcontroller?
Student Answer: Reset pin
ADC0
ADC1
None of the above
Comments:
4. Question : (TCO #3) Which bit can mask a maskable interrupt?
Student Answer: S bit
Z bit
N bit
None of the above
Comments:
5. Question : (TCO #3) In the HCS12 microcontroller, the address range 0xFFFE – 0xFFFF in the interrupt vector table is assigned to which of the following?
Student Answer: Clock monitor fail reset
ATD0
Reset
COP failure reset
Comments:
6. Question : (TCO #3) Freescale utilizes BDM to _____.
Student Answer: check each instruction of a program individually
reset CPU by setting IRQ pin to high-level logic
check changes in memory and CPU register for each instruction execution
Both A and C
Comments:
7. Question : (TCO #3) Watch dog timer is a utility that _____.
Student Answer: can reset the microcontroller whenever a program locks up.
can catch errors due to memory corruption
makes sure that a program does go to an unintentional infinite loop sequence
Both A and B
Comments:
8. Question : (TCO #3) When an interrupt occurs, _____.
Student Answer: in one stage, the contents of the CPU move to RAM memory
the CPU finishes executing its current instruction before it starts running an interrupt thread
all interrrupts will be ignored if the I bit is zero
Both A and B
Comments:
9. Question : (TCO #3) Which combination is an appropriate way of setting up the PORTJ interrupt to enabled?
Student Answer: Pin I of CCR = 0
Pin I of CCR = 1
Pin I of CCR = 1 and PIEJ7 = 1
Pin I of CCR = 0 and PIEJ6 = 0
Comments:
10. Question : (TCO #3) Which of the following interrupts has the highest priority immediately after a microcontroller reset?
Student Answer: Reset
XIRQ
COP
All have the same level of priority.
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1. Question : (TCO #3) Which interrupt is non-maskable?<br />
Student Answer:<br />
Software interrupt (SWI)<br />
Interrupt from a device connected to IRQ pin of HCS12 microcontroller<br />
Both A and B<br />
Interrupt by multiple devices connected to IRQ pin of HCS12 microcontroller<br />
Comments:<br />
2. Question : (TCO #3) Which of the following interrupts has the highest priority?<br />
Student Answer:<br />
TCNT timer overflow<br />
SCI0<br />
ATD0<br />
ATD1
Comments:<br />
3. Question : (TCO #3) Which selection is connected to the reset module in the HCS12<br />
microcontroller?<br />
Student Answer:<br />
Reset pin<br />
ADC0<br />
ADC1<br />
None of the above<br />
Comments:<br />
4. Question : (TCO #3) Which bit can mask a maskable interrupt?<br />
Student Answer:<br />
S bit<br />
Z bit<br />
N bit<br />
None of the above<br />
Comments:
5. Question : (TCO #3) In the HCS12 microcontroller, the address range 0xFFFE –<br />
0xFFFF in the interrupt vector table is assigned to which of the following?<br />
Student Answer:<br />
Clock monitor fail reset<br />
ATD0<br />
Reset<br />
COP failure reset<br />
Comments:<br />
6. Question : (TCO #3) Freescale utilizes BDM to _____.<br />
Student Answer:<br />
check each instruction of a program individually<br />
reset CPU by setting IRQ pin to high-level logic<br />
check changes in memory and CPU register for each instruction execution<br />
Both A and C<br />
Comments:
7. Question : (TCO #3) Watch dog timer is a utility that _____.<br />
Student Answer:<br />
can reset the microcontroller whenever a program locks up.<br />
can catch errors due to memory corruption<br />
makes sure that a program does go to an unintentional infinite loop sequence<br />
Both A and B<br />
Comments:<br />
8. Question : (TCO #3) When an interrupt occurs, _____.<br />
Student Answer:<br />
in one stage, the contents of the CPU move to RAM memory<br />
thread<br />
the CPU finishes executing its current instruction before it starts running an interrupt<br />
all interrrupts will be ignored if the I bit is zero<br />
Both A and B<br />
Comments:<br />
9. Question : (TCO #3) Which combination is an appropriate way of setting up the<br />
PORTJ interrupt to enabled?
Student Answer: Pin I of CCR = 0<br />
Pin I of CCR = 1<br />
Pin I of CCR = 1 and PIEJ7 = 1<br />
Pin I of CCR = 0 and PIEJ6 = 0<br />
Comments:<br />
10. Question : (TCO #3) Which of the following interrupts has the highest priority<br />
immediately after a microcontroller reset?<br />
Student Answer:<br />
Reset<br />
XIRQ<br />
COP<br />
All have the same level of priority.
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