22.2 Design Consideration of the Active-Clamp Forward Converter ...

Design Consideration of the Active-Clamp Forward Converter with Current ModeControl during Large-Signal Transient †Qiong Li ‡Philips Research345 Scarborough RdBriarcliff Manor, NY 10510Fred C. LeeCenter for Power Electronics SystemsVirginia Polytechnic Institute and State UniversityBlacksburg, VA 24061Abstract - The design issues of the active-clamp forwardconverter circuit with peak current mode control in small signalstability and large-signal transients are discussed. A designprocedure is provided to solve circuit issues under theseconditions. It is the first time that with the aid of simulation, weare able to optimize the circuit design of the active-clampforward converter for large-signal transient behaviors.I. INTRODUCTIONThe forward converter with the active-clamp reset offersmany advantages over the forward converter with othertransformer reset methods [1]. However, during the largesignaltransients, the maximum magnetizing current of thetransformer and the peak voltage of the primary switch arestrongly affected by the active-clamp circuit dynamics.Although some design issues have been discussed [2-6], thedesign of active-clamp forward converter is still based onsteady state performance. The voltage and current stresses ofthe circuit are very hard to predict during the large-signaltransient and under abnormal conditions due to the nonlinearityof the circuit, and the conflict effect of the differentparameters makes it even harder to generate a design procedure[6-7].In this paper, the design issues of the active-clamp forwardconverter circuit with peak current mode control in small signalstability and large-signal transients are discussed. A designprocedure is proposed by using design curves that aregenerated by running a large amount of simulations. Thedesign procedure will cover all the problems related to largesignaltransient as well as small-signal stability. It shows thatthe dynamic performance and the robust of the circuit can beimproved by using this approach. It is the first time that withthe aid of simulation, we are able to optimize the circuit designof the active-clamp forward converter for the large-signaltransient behaviors.II. DESIGN ISSUES OF THE ACTIVE-CLAMP CIRCUITThe active-clamp forward converter circuit diagram isshown in Fig. 1. Fig. 2 shows the load transient waveforms ofthe active-clamp circuit, where v o is the output voltage, v ds_mainis the voltage across the main switch, and i m is the magnetizingcurrent of the transformer. From Fig. 2 we can see that themaximum voltage of the main switch and the maximummagnetizing current of the transformer during transient aremuch larger than that at the steady state. These could causecircuit problems such as voltage stresses, transformersaturation, and the diode reverse recovery problem [2, 3, 6],which are marked as dotted circles in Fig. 2.Besides the large-signal transient problems, circuit couldhave stability problem due to the interaction of the resonantnetwork of the active-clamp-reset circuit [4]. Fig. 3 showssmall-signal transfer function of the loop gain at Vin = 36 V.The phase margin of the loop gain at crossover frequency isnegative due to the additional pole in the active-clamp-resetcircuit near the resonant frequency. This paper is going todemonstrate how to design the circuit to solve these problems.C CI Mn = N P : N SD 1D 2L F V O_RV LV C MNP N IN +SD CS2FS 2 d’+dV ds_main_S 1Fig. 1 Active-clamp forward converter circuit diagram.I o† This work made use of ERC shared facilities supported by the National Science Foundation under award number EEC-9731677.‡ This work was done when author was in Center for Power Electronics Systems, Virginia Tech.0-7803-5867-8/00/$10.00 (c) 2000 IEEE

v oi mVin = 36 V, Io = 5 - 30 Av ds_main2 V/div100 V/divload to no load transient. Comparing the measurement andsimulation, it shows that the simulation is accurate enough toprovide the design information and predict the dynamicbehavior of the system.Time (s)1 A/divFig. 2 Active-clamp circuit problems during large-signaltransient.f (Hz)Vin = 36 V20 dB/div0 dB0 deg90 deg/divFig. 3 Stability problem due to the resonant network ofthe active-clamp reset circuit.III. CIRCUIT UNDER WORST CASE CONDITIONThe fist step before we start the design is to find the worstcase condition during large-signal transient, so we can designthe circuit under worst case condition. A virtual prototype testprocedure is used to detect the circuit worst case condition bysimulating the circuit dynamic performance under differentlines, loads, and the abnormal conditions [7].An active-clamp forward converter circuit with peakcurrent mode control is used as an example to demonstrate thedesign process. The circuit has input voltage 36 - 72 V and fullload 30 A. The duty cycle limit of the controller chip is 0.75.The control bandwidth of the current circuit design is 14 kHz.From the simulation, it shows that the worst condition occurswhen the circuit has a large load transient from no load to fullload at low line.In order to verify the accuracy of simulation, a circuitprototype was built to compare the circuit dynamicperformance. Fig. 4 shows the large-signal responsewaveforms at Vin = 36 V, Io from no load to full load to noload transient. The load step slew rate is 1 A/us. Fig. 4(a) is themeasured waveform from no load to full load transient. Fig.4(b) is the simulated waveform from no load to full loadtransient. Fig. 4(c) is the measured waveform from full load tono load transient. Fig. 4(d) is the simulated waveform from fullIV. DESIGN PROCEDURE OF THE ACTIVE-CLAMP CIRCUITAlthough it is possible to adjust the circuit parameters bytrials and errors to fix the problems, the problem's solution isnot straightforward. It may require a lot of time and effort butstill not come out a robust design, since these parameters arenot independent parameters and involve different circuit designissues.This section will demonstrate how to generate designinformation and optimize the design parameters related to thesedesign issues. The design parameters discussed here are themagnetizing inductance of the transformer L m , the clampcapacitance C c , the control bandwidth f c , and the maximumduty cycle limit Dmax. The design process focuses on solvingthe potential problems in the circuit: voltage stress of the mainswitch, transformer core saturation, diode reverse recovery ofthe active-clamp switch, small-signal instability due to theactive-clamp resonant network.A. NormalizationThe normalized peak voltage and peak current values willbe used in the design curve. The normalized switch voltage isVsand the normalized magnetizing current isV minin( )im⋅ Zo. The x-axis of the design curve uses resonantVin( min)frequency, f o as a parameter, and Z o is the character impedance.fo1=2 ⋅π⋅ Lcm⋅ Cc(1)LmZ o = (2)CB. Design constraintsThere are four design criteria: the voltage stress of the mainswitch, the transformer saturation, the reverse recoveryproblem of the body diode of the active clamp switch, and thesmall-signal stability problem.♦ Design constraint 1: switch voltage stressThe design constraint for the switch voltage stress is:V s (peak) < V s (rating) (3)Where, V s (peak) is the peak voltage during the transient,V s (rating) is the device voltage rating of the main switch.0-7803-5867-8/00/$10.00 (c) 2000 IEEE

MeasurementSimulationVds_main50 V/div50 V/divIo30 A/div40 A/divTime (2.5 us/div)(a)MeasurementTime (s)(b)SimulationVds_main50 V/div50 V/divIo30 A/div40 A/divTime (10 us/div)(c)Time (s)Fig. 4. Large-signal response waveforms at Vin = 36 V, Io from no load to full load to no load transient. Load step slew rateis 1 A/us. (a) measured waveform of no load to full load transient. (b) simulated waveform of no load to full load transient.(c) measured waveform of full load to no load transient. (d) simulated waveform of full load to no load transient.♦ Design constraint 2: small signal stabilityThe resonant frequency of the active-clamp circuit shouldmeet the following equation in order to have a stable systemand not affect the phase margin.2⋅f cfo> (4)d' limwhere d' lim is the duty cycle limit value of the controllerchip, f c is the control bandwidth.♦ Design constraint 3: transformer saturationFig.5 shows the relation between the flux and themagnetizing current, where, A e is the effective cross sectionalarea of the core, Lm is the magnetizing current. From Fig.5, wecan get:im( sat)(d)Bsat⋅ Ae⋅ Np= (5)LmWe can rewrite saturating magnetizing current into:Bsat⋅ Ae⋅ Np⋅ 2 ⋅π⋅ foim( sat)=(6)ZoThe design constraint for transformer saturation is:im( peak)⋅ Z Bsat⋅ Ae⋅ Np⋅ 2o

Φ5.0Bsat⋅ A ei m( sat )ΦN ⋅ ipmL=Nm2pNp⋅imIm(peak)*Zo/Vin(min)4.03.02.01.0Diode reverserecovery problemareaim( peak)⋅ Zon ⋅Vo⋅ 2 ⋅=Vin( min) fs⋅ Zoπ ⋅ foFig.5. Relation of the saturation flux to the saturationmagnetizing current.5.00.00.0E+00 1.0E+05 2.0E+05 3.0E+05 4.0E+05 5.0E+05 6.0E+05fo (Hz)Fig.7. The diode reverse recovery problem area.Im(peak)*Zo/Vin(min)4.03.02.01.0transformersaturation areaim( peak)⋅ Z Bsat⋅ Ae⋅ Np⋅ 2o=V ( min) V ( min)in0.00.0E+00 1.0E+05 2.0E+05 3.0E+05 4.0E+05 5.0E+05 6.0E+05fo (Hz)in⋅π⋅ foVs(peak)/Vin(min)6.05.04.03.02.01.0Small-signal unstable areaVoltage overstress areaDesign area forvoltage curveFig. 6 The transformer saturation area.The design constraint for the transformer saturation isshown as shaded area in Fig. 6. It is a straight line in thenormalized design curve.♦ Design constraint 4: diode reverse recovery problemThe magnetizing current to prevent the diode from reverserecovery problem is:im ( peak) < im( ripple)(8)where,im( ripple)V⋅ D ⋅Tn ⋅V⋅Tin so s= =( 9)LmLmThe ripple current can be written as:im( ripple)⋅ Zon ⋅Vo⋅ 2 ⋅π⋅ f=V ( min) f ⋅V( min)insino(10)The diode reverse recovery problem area is shown as inFig.7. It is a straight line in the normalized design curve.According to four design constraints, we can draw thefeasible operating regions for voltage and magnetizing currentas shown in Fig.8.Im(peak)*Zo/Vin(min)0.00.0E+00 1.0E+05 2.0E+05 3.0E+05 4.0E+05 5.0E+05 6.0E+055.04.03.02.01.0Small-signal unstable areafo (Hz)(a)Transformersaturation areaDiode reverserecovery problem areaDesign area for currentcurve0.00.0E+00 1.0E+05 2.0E+05 3.0E+05 4.0E+05 5.0E+05 6.0E+05fo (Hz)(b)Fig.8 Feasible operating regions for voltage andmagnetizing current. (a) design area for normalizedswitch voltage curve. (b) design area for normalizedmagnetizing current curve.C. Generating design curvesThe worst case happens at low line and load from low tohigh transient. In this example, Vin is 36 V, and Io changesfrom 0 A to 30 A. A set of design curves is generated by0-7803-5867-8/00/$10.00 (c) 2000 IEEE

varying L m and C c values with a fixed control bandwidth, 14kHz, and maximum duty cycle limit, 0.75. Each singlesimulation generates one point in the voltage design curve andone point in the magnetizing current curve. The normalizeddesign curve for peak voltage and magnetizing current areshown in Fig. 9 and Fig. 10, respectively. The shaded areas arethe design prohibited area. The total simulation CPU time isonly 9 minutes by using an adequate simulation and modelingapproach [7].D. The feasible Lm and Cc to meet the design constraintsAfter we generate the design curves with designconstraints, the feasible L m and C c to meet all the designcriteria can be easily determined.Assuming the device rating of the main switch is 180 V, sothe normalized boundary of the voltage stress is 5 whenV in (min) = 36 V. When the control bandwidth, f c = 14 kHz, andmaximum duty cycle limit, d lim = 0.75, the boundary of theresonant frequency for small-signal stability is 112 kHz. Thefeasible L m and C c can be determined by three steps.1. Find the desired parameter ranges for f o and L m in peakvoltagedesign curves.Fig. 9 is the peak-voltage design curves with f c 14 kHz andd lim 0.75. These is a big dot in Fig. 9, which corresponds to theoriginal design, L m = 80 uH and C c = 0.01 uF. The maximumvoltage is about 200 V, so the original design exceeds the 180V voltage rating of the switch under worst case condition.The dotted lines covered area is the desired design area tomeet voltage stress limitation and small signal stable criterionin the normalized peak switch voltage vs. f o curves. We can seethat only the curve at L m = 20 uH meets the constraints whenf o is at 112 kHz to 480 k Hz range.2. Within the defined ranges for f o and L m in step 1, we canfind the desired ranges for f o and L m that also meet themagnetizing current constraints.Fig. 10 is the peak magnetizing-current design curves withf c 14 kHz and d lim 0.75. These is a big dot in Fig. 10, whichcorresponds to the original design, L m = 80 uH and C c = 0.01uF. It shows that the original design has diode reverse recoveryproblem and is at the boundary of the transformer saturation.From the design curves, we can see that there are nofeasible parameters available within the desired areas fromstep1. It also means that there is no feasible L m and C c canmeet all the design constraints in the previous circuit condition.3. If we find the desired ranges for f o and L m from step 1and 2, C c can be calculated byCc=12( 2 ⋅π⋅ fo) ⋅ Lm(11)Within the desired parameter range, a smaller f o , thus asmaller C c is preferred to reduce the voltage and currentstresses.Vs(peak)/Vin(min)6.05.04.03.02.01.0small signal unstable areaVoltage overstress areaLm = 160 uHLm = 320 uHLm = 80 uHDesign areaLm = 40 uHLm = 20 uH0.00.0E+00 1.0E+05 2.0E+05 3.0E+05 4.0E+05 5.0E+05 6.0E+05fo (Hz)Fig. 9 Design curve of the normalized peak switch voltagevs. f o .Im(peak)*Zo/Vin(min)5.04.03.02.01.0small signal unstable areatransformer saturationareaLm = 160 uHLm = 320 uHDiode reverserecovery areaLm = 80 uHLm = 40 uHLm = 20 uH0.00.0E+00 1.0E+05 2.0E+05 3.0E+05 4.0E+05 5.0E+05 6.0E+05fo (Hz)Fig. 10 Design curve of normalized peak magnetizingcurrent vs. f o .V. DESIGN TRADE-OFFPrevious example shows that there is no adequate L m andC c to meet all the design criteria. There are several designtrade-off to solve the problem.A. Design trade-off 1: increasing device ratingFrom Fig. 9 and Fig. 10, we see that if we do not restrictthe device voltage rating to 180 V, there is a small area in Fig.10 which can meet all the design criteria with Lm = 20 uH. Thedisadvantages of this solution are the higher voltage ratingdevice and the high ripple current of the magnetizing currentdue to a small L m .It is worthwhile to mention that a very small magnetizinginductance could have a high ripple of the magnetizing currentwhich will increase the loss of the circuit and may affect the0-7803-5867-8/00/$10.00 (c) 2000 IEEE

main converter operation if the ripple of the magnetizingcurrent is not negligible to the reflected load.B. Design trade-off 2: getting rid of the constraint of thebody diode reverse recoveryFrom Fig. 10, we see that the diode reverse recoveryconstraint is the hardest one to meet in the parameter design.The design is more flexible without this constraint. This can bedone by connecting a Schottky diode in series with theauxiliary switch to block the conduction of the body diode, andthen to connect a fast-recovery anti-parallel diode around theseries connection of the Schottky and the auxiliary switch [56].The disadvantage is the additional components to increase thecost of the circuit.C. Design trade-off 3: decreasing control bandwidthA smaller bandwidth in the design can reduce the peakvoltage and current during load transients. The disadvantage isa slower recovery from transient in the output voltage of themain converter.D. Design trade-off 4: reducing maximum duty cycle limitvalueThe voltage and current stresses can also be reduced byreducing the maximum duty cycle limit value. Similar tosolution 3, the disadvantage is a slower recovery from transientin the output voltage of the main converter.E. Circuit redesign by using trade-off 4We will use design trade-off 4 as an example to show thecircuit redesign result. The design procedure is the same as inthe previous section.Fig.11 and Fig.12 shows the normalized voltage designcurve with reduced maximum duty cycle limit. The maximumduty cycle limit is reduced from 0.75 to 0.7. The design resultis L m = 40 uH, C c is less than 0.011 uF. A smaller C c has alarger voltage stress, but less current stress and more designmargin without saturation and diode reverse recovery problem.VI. VALIDATION OF THE DESIGN BY VIRTUAL PROTOTYPETESTFig. 15 shows the comparisons between the original circuitproblems and the circuit behavior after the final designmodification. The circuit parameters are modified by reducingthe maximum duty cycle limit from 0.75 to 0.7 andmagnetizing inductance from 80 uH to 40 uH. The clampcapacitance is 0.01 uF.Fig. 13 shows design verification of dc bias of magnetizingcurrent of transformer. The dc bias of the magnetizing currentdoes not shown any problems since the magnetizing currentripple is about 800 mA.Vs(peak)/Vin(min)6.05.04.03.02.01.0small signal unstable areaVoltage overstress areaLm = 160 uHLm = 40 uHLm = 80 uHLm = 20 uHLm = 320 uHDesign area0.00.0E+00 1.0E+05 2.0E+05 3.0E+05 4.0E+05 5.0E+05 6.0E+05fo (Hz)Fig.11 Normalized voltage design curve reducedmaximum duty cycle limit. The Dlim is reduced from0.75 to 0.7. The design area to meet voltage stresslimitation and small signal stable criteria is shown in thedotted area.Im(peak)*Zo/Vin(min)5.04.03.02.01.0small signal unstable areaDiode reversetransformer saturationrecovery boundaryboundaryLm = 320 uHLm = 80 uHLm = 40 uHDesign area forL m= 40 uH0.00.0E+00 1.0E+05 2.0E+05 3.0E+05 4.0E+05 5.0E+05 6.0E+05fo (Hz)Fig.12 Normalized magnetizing current design curve withreduced maximum duty cycle limit. The Dlim is reducedfrom 0.75 to 0.7. The design area without transformersaturation and diode reverse recovery problem shows inthe dotted line.Fig. 14 shows the design verification of the small signalanalysis under worst case condition. The resonant frequency ofthe active-clamp circuit has been pushed high enough and doesnot interfere with the crossover frequency of the loop gain.0-7803-5867-8/00/$10.00 (c) 2000 IEEE

Vin = 36 VVin = 48 V100 V/divIm (A)Vin = 72 V0.5 A/div40 A/divIo (A)Fig. 13. Design verification of dc bias of magnetizingcurrent of transformer at steady state.20 dB/divVin = 36 Vv ds_mainTime (s)(a)100 V/div0 dB0 deg0.5 A/divi oi m(b)40 A/div90 deg/divTime (s)Fig. 14 Design verification of the small signal analysis.Fig. 15 shows the design verification of the large-signaltransient analysis under worst case: Vin = 36 V, Io = 0 to 30 A.Fig. 15(a) shows the waveforms with original design. Fig.15(b) shows the waveforms after design modification. Theoriginal circuit problems during large-signal transient aresolved.VII.CONCLUSIONSThe design issues of the active-clamp forward convertercircuit with peak current mode control in small signal stabilityand large-signal transients are discussed. A design procedure isproposed to solve design issues. The circuit performances ofthe power supply system design are improved by redesign theactive-clamp reset circuit. It is the first time that with the aid ofthe virtual prototype, we are able to optimize the circuit designof the active-clamp forward converter for large-signal transientbehaviors.Fig. 15 Design verification of the large-signal transientanalysis with worst case: Vin = 36 V, Io = 0 to 30 A. (a)waveforms with original design. (b) waveforms afterdesign modification.REFERENCES[1] P. Vinciarelli, “Optimal resetting of the transformer’s core in singleended forward converters,” U.S. Patent, No. 4,441,146, Apr. 1984.[2] B. Carsten, “Design techniques for transformer active reset circuits athigh frequencies and power levels,” HFPC Conf. Proc., pp.235-246,1990.[3] D. Dalal and L. Wofford, “Novel control IC for single-ended activeclamp converters,” HFPC Conf. Proc., pp. 136-146, 1995.[4] Q. Li, F. C. Lee, and M. M. Jovanovic, “Design considerations oftransformer DC bias of forward converter with active-clamp reset,”IEEE APEC Proc., pp.553-559, March 14-18, 1999.[5] A. Fontan, S. Ollero, E. de la Cruz, and J. Sebastian, “Peak currentmode control applied to the forward converter with active clamp,”IEEE PESC Rec., pp. 45-51, 1998.[6] Q. Li, F. C. Lee, and M. M. Jovanovic, “Large-signal transient analysisof forward converter with active-clamp reset,” IEEE PESC Rec.,pp.633-639, May 1998.[7] Q. Li, “Developing Modeling and simulation methodology for virtualprototype power supply system,” Ph.D Dissertation, CPES, VPI&SU,March 1999.0-7803-5867-8/00/$10.00 (c) 2000 IEEE