Practical ICT Experience – Flexibility – Worldwide References

Knowledge Evolution
Safety Critical & High Availability Systems Masterclass
Course ID: EPOL-10:026
Duration: 3 days
Number of participants: recommended optimum 15, maximum 25
Course objectives
The primary goal of this Masterclass is to give the participant the skills necessary to design systems
and software for real-time and embedded computers in which faults and failures could pose a danger to
human life. As part of this, participants gain skills in designing systems for high availability. This is very
practical, results-oriented training that provides knowledge and skills that can be applied immediately.
This Masterclass examines the design of embedded systems and software that are to provide services
in applications that could, when they fail, threaten the well-being or safety of people. Many, though not
all, of these systems must not be stopped under any circumstances, and thus must be designed for high
availability. Practical guidance is offered on how to address these concerns when designing systems
in fields such as medical, automotive, avionics, nuclear and chemical process control.
The Masterclass surveys concepts and alternatives for system and software architectures appropriate for
safety-critical and high availability systems. Following an examination of hazard and risk analysis
techniques, the seminar goes on to list a number of approaches to software safety that span fault avoidance,
fault detection, and fault containment tactics including redundancy, recovery, masking
and barriers. A variety of candidate architectural design patterns are examined, including dual/triple
modular redundancy, shutdown monitors, dissimilar independent designs, backup parallel patterns
and active/monitor parallel patterns. Many real-world examples are presented.
Systems which are required to provide high availability must be designed to tolerate faults. Their design
is usually based on off-the-shelf hardware and software combined in ways that will achieve “five-nines”
(99.999%) or greater availability. Basic hardware N-plexing and voting issues are discussed, followed
by an in-depth study of a number of backward error recovery fault tolerance techniques including
Checkpoint-Rollback, Process Pairs, and Recovery Blocks. The class continues with several forward error
recovery techniques. Software design approaches are discussed for run-time Built-In Self Test (BIST) of
processor and peripheral hardware. Technical issues such as failover management, data replication,
and software design defects, are addressed in depth.
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