DIGITAL DESIGN

Section 1.6 Integrated Circuits 13
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pin 1 pin 28 Figure 1-4
pin 1
Dual in-line pin (DIP)
pin 20
packages: (a) 14-pin;
pin 1 pin 14
(b) 20-pin; (c) 28-pin.
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pin 8
pin 11
pin 15
(a) 0.3"
(b) (c)
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In the early days of integrated circuits, ICs were classified by size—small,
medium, or large—according to how many gates they contained. The simplest
type of commercially available ICs are still called small-scale integration (SSI), small-scale integration
and
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contain the equivalent of
NOT
1 to 20 gates. SSI ICs typically contain
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a handful of (SSI)
gates or flip-flops, the basic building blocks of digital design.
The SSI ICs that you’re likely to encounter in an educational lab come in a
14-pin dual in-line-pin (DIP) package. As shown in Figure 1-4(a), the spacing dual in-line-pin (DIP)
between pins in a column is 0.1 inch and the spacing between columns is 0.3 package
inch.
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Larger DIP packages accommodate
NOT
functions with more
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pins, as shown in
(b) and (c). A pin diagram shows the assignment of device signals to package pin diagram
pins, or pinout. Figure 1-5 shows the pin diagrams for a few common SSI ICs. pinout
Such diagrams are used only for mechanical reference, when a designer needs to
determine the pin numbers for a particular IC. In the schematic diagram for a
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Figure 1-5 Pin diagrams for a few 7400-series SSI ICs.
7400
7402
7404
7408
7410
1
2
3
4
5
VCC 14 1
VCC 14 1
VCC 14 1
VCC 14 1
VCC 14
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13 2
13 2
13 2
13 2
13
12 3
12 3
12 3
12 3
12
11 4
11 4
11 4
11 4
11
10 5
10 5
10 5
10 5
10
6
9 6
9 6
9 6
9 6
9
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7 GND
8 7 GND
8 7 GND
8 7 GND
8 7 GND
8
7411
7420
7421
7430
7432
1
VCC 14 1
VCC 14 1
VCC 14 1
VCC 14 1
VCC 14
2
13 2
13 2
13 2
13 2
13
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3
12 3
12 3
12 3
12 3
12
4
11 4
11 4
11 4
11 4
11
5
10 5
10 5
10 5
10 5
10
6
9 6
9 6
9 6
9 6
9
7 GND
8 7 GND
8 7 GND
8 7 GND
8 7 GND
8
0.1"
0.1"
Copyright © 1999 by John F. Wakerly Copying Prohibited
0.3"
0.1"
0.6"