Marcelo Cintra - School of Informatics - University of Edinburgh

Professional Experience
Marcelo Cintra
School of Informatics
University of Edinburgh
1.03 Informatics Forum
10 Crichton Street
Edinburgh, EH8 9AB
United Kingdom
e-mail: mc@inf.ed.ac.uk
tel: +44 131 650-5118 fax: +44 131 667-7209
2012-present - Professor
School of Informatics, University of Edinburgh, Edinburgh, UK.
2011-2013 - Senior Research Scientist (Sabbatical)
Intel Germany Research, Braunschweig, Germany
2009-2012 - Reader (Associate Professor)
School of Informatics, University of Edinburgh, Edinburgh, UK.
2001-2009 - Lecturer (Assistant Professor)
School of Informatics, University of Edinburgh, Edinburgh, UK.
Education
1996-2001 - University of Illinois, Urbana, USA
Ph.D. in Electrical and Computer Engineering.
Thesis: ”Architectural Support for Scalable Speculative Parallelization”.
Advisor: Josep Torrellas (Ph.D. Stanford 1992).
1994-1996 - University of Sao Paulo, Sao Paulo, Brazil
M.Sc. in Computer Engineering.
Thesis: ”Methodology for Multilevel Modeling and Simulation of Computer Systems Using Petri Nets”.
Advisor: Wilson Ruggiero (Ph.D. UCLA 1978).
1988-1992 - University of Sao Paulo, Sao Carlos, Brazil
B.Sc. in Electrical Engineering.
Awards
Association Awards
ACM Senior Membership (since 2010)
IEEE Senior Membership (since 2010)
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Technical Awards
2012 - February - Award of Research Excellence - Intel Germany Microprocessor Laboratory
2012 - November - Award of Research Excellence - Intel Germany Microprocessor Laboratory
Paper Awards
2011 - HiPEAC Paper Award for ”Combining User-Level Coarse-Grain Parallelism with Implicit
Speculative Parallelism”
2011 - Best Paper Award nomination for ”Phase-Based Application-Driven Hierarchical Power
Management on the Single-chip Cloud Computer”
2010 - HiPEAC Paper Award for ”Handling Branches in TLS Systems with Multi-Path Execution”
2009 - HiPEAC Paper Award for ”Stream Chaining: Exploiting Multiple Levels of Correlation in Data
Prefetching”
2008 - HiPEAC Paper Award for ”An OS-Based Alternative to Full Hardware Coherence on Tiled CMPs”.
Grants
2010-present - European Commission, Seventh Framework Programme, EU
Co-Principal investigator (with 8 other EU partners)
Title: ”Embedded Reconfigurable Architectures (ERA)”
Value: e4,000,000
2008-present - EPSRC (Engineering and Physics Science Research Council), UK
Co-Principal investigator (with Gavin Brown - University of Manchester)
Title: ”Machine Learning for Thread-Level Speculation on Multi-core Architectures”
Value: £777,366
2007-present - European Commission, Seventh Framework Programme, EU
European Network of Excellence on High-Performance and Embedded Architecture and Compilation 2
(HiPEAC2)
Member
Value: e4,000,000
2006-2010 - European Commission, Sixth Framework Programme, EU
Co-investigator
Title: ”Scalable Computer Architecture (SARC)”
Value: e8,000,000
2004-2007 - European Commission, Sixth Framework Programme, EU
European Network of Excellence on High-Performance Embedded Architecture and Compilation (HiPEAC)
Member
Value: e4,000,000
2004-2007 - EPSRC (Engineering and Physics Science Research Council), UK
Principal investigator
Title: ”Architecture and Compiler Infrastructure for Flexible Cellular Multiprocessing”
Value: £283,989
2001-2004 - EPSRC (Engineering and Physics Science Research Council), UK
Principal investigator
Title: ”Software and Hardware for Efficient Speculative Multithreading”
Value: £62,607
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2001-2004 - EPSRC (Engineering and Physics Science Research Council), UK
Co-investigator
Title: ”Simulation Studies of the UKqcd Computer Architecture”
Value: £162,763
1996-2000 - CNPq (Brazilian National Science Council), Brazil
Scholarship for Doctoral Studies Abroad.
1994-1996 - CNPq (Brazilian National Science Council), Brazil
Scholarship for Masters Studies in Brazil.
Selected Publications
Book Chapters
”ERA: Embedded Reconfigurable Architectures”
Stephan Wong, Luigi Carro, Mateus Rutzig, Debora Motta Matos, Roberto Giorgi, Nikola Puzovic,
Stefanos Kaxiras, Marcelo Cintra, Giuseppe Desoli, Paolo Gai, Sally A. Mckee, and Ayal Zaks
in ”Reconfigurable Computing: From FPGAs to Hardware/Software Codesign”
João Cardoso and Michael Hübner (Eds.)
Springer Verlag, 2011
Journals
”Autotuning Skeleton-Driven Optimizations for Transactional Worklist Applications”
Luis Fabricio W. Goes, Nikolas Ioannou, Polychronis Xekalakis, Murray Cole, and Marcelo Cintra
IEEE Transactions on Parallel and Distributed Systems (TPDS), vol. 23, no. 12, p 2205-2218, December
2012
”Combined Speculative Multithreaded Execution Models”
Polychronis Xekalakis, Nikolas Ioannou, and Marcelo Cintra
ACM Transactions on Architecture and Code Optimization (TACO), vol. 9, no. 6, September 2012
”An Evaluation of an OS-Based Coherence Scheme for Tiled CMPs”
Christian Fensch and Marcelo Cintra
International Journal of Parallel Programming (IJPP), Special Issue on High Performance and Embedded
Architecture and Compilation, vol. 39, no. 3, p 271-295, June 2011
”Software-Based Cache Coherence with Hardware-Assisted Selective Self Invalidations Using Bloom
Filters”
Thomas J. Ashby, Pedro Diaz, and Marcelo Cintra
IEEE Transactions on Computers (TC), vol. 60, no. 4, p. 472-483, April 2011
”A Compiler Cost Model for Speculative Parallelization”
Jialin Dou and Marcelo Cintra
ACM Transactions on Architecture and Code Optimization (TACO), vol. 4, no. 2, June 2007
”Design Space Exploration of a Software Speculative Parallelization Scheme”
Marcelo Cintra and Diego R. Llanos
IEEE Transactions on Parallel and Distributed Systems (TPDS), vol. 16, no. 6, p. 562-576, June 2005
”Excel-NUMA: Toward Programmability, Simplicity, and High Performance”
Zheng Zhang, Marcelo Cintra, and Josep Torrellas
IEEE Transactions on Computers (TC), Special Issue on Cache Memory, vol. 48, no. 2, p. 256-264,
February 1999
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Conferences
”UCIFF: Unified Cluster Assignment, Instruction Scheduling, and Fast Frequency Selection for
Heterogeneous Clustered VLIW Cores”
Vasileios Porpodas and Marcelo Cintra
International Workshop on Languages and Compilers for Parallel Computing (LCPC), September 2012
”ASCIB: Adaptive Selection of Cache Indexing Bits for Removing Conflict Misses”
Alberto Ros, Polychronis Xekalakis, Marcelo Cintra, Manuel E. Acacio, and Jose M. Garcia
International Symposium on Low Power Electronics and Design (ISLPED), August 2012
”SuperCoP: A General, Correct, and Performance-efficient Supervised Memory System”
Bharghava Rajaram, Vijay Nagarajan, Andrew J. McPherson, and Marcelo Cintra
International Conference on Computing Frontiers (CF), p. 85-94, May 2012
”A Machine Learning-Based Approach for Thread Mapping on Transactional Memory Applications”
Marcio Castro, Luis Fabricio W. Goes, Christiane P. Ribeiro, Murray Cole, Marcelo Cintra, and
Jean-Francois Mehaut
International Conference on High Performance Computing (HiPC), December 2011
”Increasing the Energy Efficiency of TLS Systems Using Intermediate Checkpointing”
Salman Khan, Nikolas Ioannou, Polychronis Xekalakis, and Marcelo Cintra
International Conference on High Performance Computing (HiPC), December 2011
”Combining User-Level Coarse-Grain Parallelism with Implicit Speculative Parallelism”
Nikolas Ioannou and Marcelo Cintra
International Symposium on Microarchitecture (MICRO), p. 284-295, December 2011
Recipient of a HiPEAC Paper Award in 2011
”Phase-Based Application-Driven Hierarchical Power Management on the Single-chip Cloud Computer”
Nikolas Ioannou, Michael Kauschke, Matthias Gries, and Marcelo Cintra
International Conference on Parallel Architectures and Compilation Techniques (PACT), p. 131-142,
October 2011 Best Paper Award nominee
”Toward a More Accurate Understanding of the Limits of the TLS Execution Paradigm”
Nikolas Ioannou, Jeremy Singer, Salman Khan, Polychronis Xekalakis, Paraskevas Yiapanis, Adam Pocock,
Gavin Brown, Mikel Lujan, Ian Watson, and Marcelo Cintra
International Symposium on Workload Characterization (IISWC), p. 117-128, December 2010
”Profitability-Based Power Allocation for Speculative Multithreaded Systems”
Polychronis Xekalakis, Nikolas Ioannou, Salman Khan, and Marcelo Cintra
International Parallel and Distributed Processing Symposium (IPDPS), April 2010
”Generating Code for Holistic Query Evaluation”
Konstantinos Krikellas, Stratis D. Viglas, and Marcelo Cintra
International Conference on Data Engineering (ICDE), p. 613-624, March 2010
”Compiler-Directed Performance Model Construction for Parallel Programs”
Martin Schindewolf, David Kramer, and Marcelo Cintra
International Conference on Architecture of Computing Systems (ARCS), February 2010 (Proceedings
published in Lecture Notes in Computer Science 5974, p. 187-198, Ed. Springer-Verlag, 2010)
”Handling Branches in TLS Systems with Multi-Path Execution”
Polychronis Xekalakis and Marcelo Cintra
International Symposium on High-Performance Computer Architecture (HPCA), p. 367-378, January 2010
Recipient of a HiPEAC Paper Award in 2010
4

”Distance-Aware Round-Robin Mapping for Large NUCA Caches”
Alberto Ros, Marcelo Cintra, Manuel E. Acacio, and Jose M. Garcia
International Conference on High Performance Computing (HiPC), p. 79-88, December 2009
”Stream Chaining: Exploiting Multiple Levels of Correlation in Data Prefetching”
Pedro Diaz and Marcelo Cintra
International Symposium on Computer Architecture (ISCA), p. 81-92, June 2009
Recipient of a HiPEAC Paper Award in 2009
”Combining Thread Level Speculation, Helper Threads, and Runahead Execution”
Polychronis Xekalakis, Nikolas Ioannou, and Marcelo Cintra
International Conference on Supercomputing (ICS), p. 410-420, June 2009
”An OS-Based Alternative to Full Hardware Coherence on Tiled CMPs”
Christian Fensch and Marcelo Cintra
International Symposium on High-Performance Computer Architecture (HPCA), p. 355-366, February 2008
Recipient of a HiPEAC Paper Award in 2008
”Using Predictive Modeling for Cross-Program Design Space Exploration in Multicore Systems”
Salman Khan, Polychronis Xekalakis, John Cavazos, and Marcelo Cintra
International Conference on Parallel Architectures and Compilation Techniques (PACT), p. 327-338,
September 2007
”Quantifying Uncertainty in Points-To Relations”
Constantino G. Ribeiro and Marcelo Cintra
International Workshop on Languages and Compilers for Parallel Computing (LCPC), November 2006
(Proceedings published in Lecture Notes in Computer Science 4382, p. 190-204, Ed. Springer-Verlag, 2007)
”Compiler Estimation of Load Imbalance Overhead in Speculative Parallelization”
Jialin Dou and Marcelo Cintra
International Conference on Parallel Architectures and Compilation Techniques (PACT), p. 203-214,
September 2004
”Toward Efficient and Robust Software Speculative Parallelization in Multiprocessors”
Marcelo Cintra and Diego R. Llanos
Symposium on Principles and Practice of Parallel Programming (PPoPP), p. 13-24, June 2003
”Eliminating Squashes Through Learning Cross-Thread Violations in Speculative Parallelization for
Multiprocessors”
Marcelo Cintra and Josep Torrellas
International Symposium on High-Performance Computer Architecture (HPCA), p. 43-54, February 2002
”Architectural Support for Scalable Speculative Parallelization in Shared-Memory Multiprocessors”
Marcelo Cintra, José F. Martínez, and Josep Torrellas
International Symposium on Computer Architecture (ISCA), p. 13-24, June 2000
Keynote Talks
September 2008 - ”Beyond Auto-Parallelization: Compilers for Many-Core Systems”
The EPSRC/KTN Grand Challenges in Microelectronics Design - Moore for Less, Cambridge, UK.
Panels
January 2009 - ”Can machine learning help to solve the multicore code generation issues?”
Workshop on Statistical and Machine Learning Approaches to Architectures and Compilation (SMART),
Paphos, Cyprus.
5

Invited Talks (last 5 years)
September 2011 - ”Phase-Based Application-Driven Power Management on the Single-chip Cloud
Computer”
Google, London, UK.
May 2011 - ”Stream Chaining: Exploiting Multiple Levels of Correlation in Data Prefetching”
Department of Computer Science, University of Cambridge, Cambridge, UK.
November 2010 - ”Stream Chaining: Exploiting Multiple Levels of Correlation in Data Prefetching”
Department of Informatics Engineering, University of Porto, Porto, Portugal.
September 2010 - ”Fair Prefetching in Multi-Cores with Resizable Prefetch Heaps”
Intel European Research and Innovation Conference (ERIC) (by invitation only)
Intel Germany Research Laboratory, Braunschweig, Germany.
March 2010 - ”Mixed Speculative Multithreaded Execution Models”
Department of Computer Science, University of Manchester, Manchester, UK.
November 2009 - ”Stream Chaining: Exploiting Multiple Levels of Correlation in Data Prefetching”
Department of Informatics, Technical University of Munich, Munich, Germany.
May 2009 - ”Stream Chaining: Exploiting Multiple Levels of Correlation in Data Prefetching”
Department of Computer Science, University of Illinois at Urbana-Champaign, Urbana, USA.
March 2009 - ”An OS-Based Alternative to Full Hardware Coherence on Tiled CMPs”
Department of Electrical and Computer Engineering, University of Rochester, Rochester, USA.
July 2008 - ”An OS-Based Alternative to Full Hardware Coherence on Tiled CMPs”
Intel Germany Research Laboratory, Braunschweig, Germany.
May 2008 - ”An OS-Based Alternative to Full Hardware Coherence on Tiled CMPs”
Department of Computer Engineering, University of Murcia, Murcia, Spain.
July 2007 - ”Alternatives to Eager Hardware Cache Coherence on Large-Scale CMPs”
IBM T. J. Watson Research Center, Yorktown Heights, USA.
June 2007 - ”Alternatives to Eager Hardware Cache Coherence on Large-Scale CMPs”
Department of Informatics, University of Erlangen-Nürnberg, Germany.
March 2007 - ”Alternatives to Eager Hardware Cache Coherence on Large-Scale CMPs”
Oak Ridge National Laboratory, Oak Ridge, USA.
February 2007 - ”Alternatives to Eager Hardware Cache Coherence on Large-Scale CMPs”
ARM Ltd., Cambridge, UK.
January 2006 - ”Toward a Compiler Framework for Thread-Level Speculation”
Department of Informatics, University of Karlsruhe, Karlsruhe, Germany.
Graduate Students
Graduated
Nikolas Ioannou (Ph.D. 2012)
University of Edinburgh, Edinburgh, UK.
Thesis: ”Complementing User-Level Coarse-Grain Parallelism with Implicit Speculative Parallelism”
First Job: Post-doctoral Researcher - IBM Research Zurich, Zurich, Switzerland.
6

Luis Fabrício Góes (Ph.D. 2012 - co-advisor with Murray Cole)
University of Edinburgh, Edinburgh, UK.
Thesis: ”Autotuning Skeleton-Driven Optimizations for Transactional Worklist Applications”
First Job: Assistant Professor - Catholic University of Minas Gerais, Belo Horizonte, Brazil.
Pedro Díaz (Ph.D. 2011)
University of Edinburgh, Edinburgh, UK.
Thesis: ”Mechanisms to Improve the Efficiency of Hardware Data Prefetchers”
First Job: Software Engineer - Google, London, UK.
Salman Khan (Ph.D. 2010)
University of Edinburgh, Edinburgh, UK.
Thesis: ”Putting Checkpoints to Work in Thread Level Speculative Execution”
First Job: Post-doctoral Research Assistant - University of Manchester, Manchester, UK.
Konstantinos Krikellas (Ph.D. 2010 - co-advisor with Stratis Viglas)
University of Edinburgh, Edinburgh, UK.
Thesis: ”The Case for Holistic Query Evaluation”
First Job: Database/Systems Engineer - Greenplum, San Mateo, USA.
Polychronis Xekalakis (Ph.D. 2009)
University of Edinburgh, Edinburgh, UK.
Thesis: ”Mixed Speculative Multithreaded Execution Models”
First Job: Research Staff - Intel Laboratory Barcelona, Barcelona, Spain.
Christian Fensch (Ph.D. 2008)
University of Edinburgh, Edinburgh, UK.
Thesis: ”An OS-Based Alternative to Full Hardware Coherence on Tiled Chip-Multiprocessors”
First Job: Post-doctoral Research Assistant - University of Cambridge, Cambridge, UK.
Jialin Dou (Ph.D. 2006)
University of Edinburgh, Edinburgh, UK.
Thesis: ”A Compiler Cost Model for Speculative Multithreading Chip-Multiprocessor Architectures”
First Job: Graduate Engineer - Compilation Tools, ARM Ltd., Cambridge, UK.
Current Position: Senior Engineer - ARM Ltd., Cambridge, UK.
Constantino Ribeiro (M.Phil. 2008)
University of Edinburgh, Edinburgh, UK.
Martin Schindewolf (Diplom 2008) (co-advisor with Wolfgang Karl)
University of Karlsruhe, Karlsruhe, Germany.
Marius Kuhn (Diplom 2007) (co-advisor with Axel Hunger)
University of Duisburg-Essen, Duisburg, Germany.
Matthew MacLeod (M.Eng. 2007)
University of Edinburgh, Edinburgh, UK.
David Foster (M.Sc. 2005)
University of Edinburgh, Edinburgh, UK.
Salman Khan (M.Sc. 2005)
University of Edinburgh, Edinburgh, UK.
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In Progress
Vasileios Porpodas (Ph.D.) - 2009-present
University of Edinburgh, Edinburgh, UK.
Konstantina Mitropoulou (Ph.D.) - 2010-present
University of Edinburgh, Edinburgh, UK.
Andrew McPherson (Ph.D.) (co-advisor with Vijay Nagarajan) - 2010-present
University of Edinburgh, Edinburgh, UK.
Georgios Stefanakis (Ph.D.) - 2010-present
University of Edinburgh, Edinburgh, UK.
Postdoctoral Associates
Thomas Ashby (2005-2007)
First Job: MPSoC Application Engineer, IMEC, Leuven, Belgium.
Postdoctoral Visitors
Diego R. Llanos - March/April 2002; June/July 2003; May-July 2004; July-August 2010
Universidad de Valladolid, Valladolid, Spain.
Luis Alberto Marqués Cuesta - October-December 2007
Universidad de Valladolid, Valladolid, Spain.
Professional Services
Journal Editorial Board:
2011-present - Journal of Parallel and Distributed Computing (Elsevier)
Associate Editor
2007 - Transactions on High-Performance Embedded Architectures and Compilers (Springer)
Special issue on Future Directions in Embedded Systems Compilation, vol. 1, no. 1, 2007
Guest Editor
To Professional Associations:
2010-present - Member of the Executive Committee of IEEE TCCA (Technical Committee on Computer
Architecture)
Grant Review Panel member:
2010 - Department of Energy (DOE), USA
2010-present - European Research Council (ERC), EU
Advisory Board member:
Euro-Par - 2008-present
8

Program Committee member:
International Symposium on Computer Architecture (ISCA): 2011
International Conference on Supercomputing (ICS): 2011; 2010; 2009
International Conference on Parallel Architectures and Compilation Techniques (PACT): 2012; 2009
International Parallel and Distributed Processing Symposium (IPDPS): 2010; 2007; 2003
International Conference for High Performance Computing Networking, Storage, and Analysis
(Supercomputing, SC): 2011
International Conference on Computer Design (ICCD): 2011; 2010
International Conference on High Performance Computing (HiPC): 2011; 2009
International Conference on Parallel Processing (ICPP): 2004
Euro-Par Conference: 2008
Committee member of Ph.D. final examinations:
University of Manchester, Manchester, UK. (2 students)
University of Cambridge, Cambridge, UK.
Chalmers University of Technology, Göteborg, Sweden.
University of Malaga, Malaga, Spain.
University of Granada, Granada, Spain.
University of Edinburgh, Edinburgh, UK. (8 students)
Other Services:
2005 - 2007 - Assistant Coordinator for European Network of Excellence on High Performance Embedded
Architecture and Compilation (HiPEAC).
Consultancy and External Services
March 2008 - Technical Consultant
CAPS Enterprise, France.
2010 - Translator of book ”Compiler Design - Virtual Machines” from German to English
Springer Verlag, Germany.
Department/University Services
2001-present - Director of Studies
University of Edinburgh, Edinburgh, UK.
2003-2010 - School Library Representative
University of Edinburgh, Edinburgh, UK.
2005-present - School Ph.D. Selection Committee
University of Edinburgh, Edinburgh, UK.
Teaching
Undergraduate Courses:
CS4 Parallel Architectures (4th year B.Sc.) - 2006/07-2010/11
University of Edinburgh, Edinburgh, UK.
9

CS4 Parallel Programming Languages and Systems (4th year B.Sc.) - 2008/09-2010/11
University of Edinburgh, Edinburgh, UK.
CS3 Computer Architecture (3rd year B.Sc.) - 2001/02-2005/06
University of Edinburgh, Edinburgh, UK.
CS3 Computer Design (3rd year B.Sc.) - 2009/10
University of Edinburgh, Edinburgh, UK.
CS2/Inf2 Computer Systems (2nd year B.Sc.) - 2001/02-2004/05 and 2008/09
University of Edinburgh, Edinburgh, UK.
CP1 Computer Programming Skills and Concepts (1st year B.Sc.) - 2005/06-2007/08
University of Edinburgh, Edinburgh, UK.
CS3 Systems Design Project (3rd year B.Sc.) - 2000/01; 2002/03-2003/04
University of Edinburgh, Edinburgh, UK.
CS4 Individual Project (Final year B.Sc.) - 2001/02-2005/06 (supervisor to 9 students)
University of Edinburgh, Edinburgh, UK.
CS&E4 Individual Project (4th year M.Eng.) - 2003/04 (supervisor to 1 student)
University of Edinburgh, Edinburgh, UK.
Other:
Third Year Undergraduate General Course Organizer - 2010/11
University of Edinburgh, Edinburgh, UK.
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