Marcelo Cintra - School of Informatics - University of Edinburgh
Marcelo Cintra - School of Informatics - University of Edinburgh
Marcelo Cintra - School of Informatics - University of Edinburgh
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2001-2004 - EPSRC (Engineering and Physics Science Research Council), UK<br />
Co-investigator<br />
Title: ”Simulation Studies <strong>of</strong> the UKqcd Computer Architecture”<br />
Value: £162,763<br />
1996-2000 - CNPq (Brazilian National Science Council), Brazil<br />
Scholarship for Doctoral Studies Abroad.<br />
1994-1996 - CNPq (Brazilian National Science Council), Brazil<br />
Scholarship for Masters Studies in Brazil.<br />
Selected Publications<br />
Book Chapters<br />
”ERA: Embedded Reconfigurable Architectures”<br />
Stephan Wong, Luigi Carro, Mateus Rutzig, Debora Motta Matos, Roberto Giorgi, Nikola Puzovic,<br />
Stefanos Kaxiras, <strong>Marcelo</strong> <strong>Cintra</strong>, Giuseppe Desoli, Paolo Gai, Sally A. Mckee, and Ayal Zaks<br />
in ”Reconfigurable Computing: From FPGAs to Hardware/S<strong>of</strong>tware Codesign”<br />
João Cardoso and Michael Hübner (Eds.)<br />
Springer Verlag, 2011<br />
Journals<br />
”Autotuning Skeleton-Driven Optimizations for Transactional Worklist Applications”<br />
Luis Fabricio W. Goes, Nikolas Ioannou, Polychronis Xekalakis, Murray Cole, and <strong>Marcelo</strong> <strong>Cintra</strong><br />
IEEE Transactions on Parallel and Distributed Systems (TPDS), vol. 23, no. 12, p 2205-2218, December<br />
2012<br />
”Combined Speculative Multithreaded Execution Models”<br />
Polychronis Xekalakis, Nikolas Ioannou, and <strong>Marcelo</strong> <strong>Cintra</strong><br />
ACM Transactions on Architecture and Code Optimization (TACO), vol. 9, no. 6, September 2012<br />
”An Evaluation <strong>of</strong> an OS-Based Coherence Scheme for Tiled CMPs”<br />
Christian Fensch and <strong>Marcelo</strong> <strong>Cintra</strong><br />
International Journal <strong>of</strong> Parallel Programming (IJPP), Special Issue on High Performance and Embedded<br />
Architecture and Compilation, vol. 39, no. 3, p 271-295, June 2011<br />
”S<strong>of</strong>tware-Based Cache Coherence with Hardware-Assisted Selective Self Invalidations Using Bloom<br />
Filters”<br />
Thomas J. Ashby, Pedro Diaz, and <strong>Marcelo</strong> <strong>Cintra</strong><br />
IEEE Transactions on Computers (TC), vol. 60, no. 4, p. 472-483, April 2011<br />
”A Compiler Cost Model for Speculative Parallelization”<br />
Jialin Dou and <strong>Marcelo</strong> <strong>Cintra</strong><br />
ACM Transactions on Architecture and Code Optimization (TACO), vol. 4, no. 2, June 2007<br />
”Design Space Exploration <strong>of</strong> a S<strong>of</strong>tware Speculative Parallelization Scheme”<br />
<strong>Marcelo</strong> <strong>Cintra</strong> and Diego R. Llanos<br />
IEEE Transactions on Parallel and Distributed Systems (TPDS), vol. 16, no. 6, p. 562-576, June 2005<br />
”Excel-NUMA: Toward Programmability, Simplicity, and High Performance”<br />
Zheng Zhang, <strong>Marcelo</strong> <strong>Cintra</strong>, and Josep Torrellas<br />
IEEE Transactions on Computers (TC), Special Issue on Cache Memory, vol. 48, no. 2, p. 256-264,<br />
February 1999<br />
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