iPhone 5S 820-3292-A

8 7 6 5 4 3 2 1
ÿ
H6P NAND + 12X17 NAND PKG
SUPPORT FOR PPN1.5 (1.8V 10) ONLY
D
D
C
12 11 10 7 6 5 3 2 p P - V C
23 21 19
AP TO NAND ANCO CENO L
AP BI NAND ANCO IQ<0>
2R7 8
1o OK
ÿ
• 5%
- 1/32W
MF
? 01005
ROOM=H6P
NC
G32
B32
6 AP BI NAND ANCO I0<1> C32
6 AP BI NAND ANCO IO<2> C33
6 AP BI NAND ANCO IO<3> C34
6 AP BI NAND ANCO IO<4> F32
6 AP BI NAND ANCO IO<5> F33
6 AP BI NAND ANCO IO<6> F34
6 AP BT NAND ANCO IO<7> G34
PPNO.
PPNO
PPNO.
PPNO.
PPNO.
PPNO.
PPNO.
PPNO.
PPNO.
PPNO
CENO I
CEN1
.100
.101
102
.103
.104
.105
.106
107
U1
H6PPOP-1GB-DDR
SC58960X01-AO30
FCMSP
SYM 4 OF 13
OMIT TABLE
VDDIOl 8 GRP 3
PPN1 CENO
PPN1 CEN1
PPN1
PPN1
PPN1
PPN1
PPN .
PPN .
PPN1
PPN1
R32
M34
NC
2R82
10 OK
ÿ
5%
- 1/32W
MF
o 01005
ROOM=H6P
AP TO NAND ANC1 CENO
1
CI3 6
- 0 . 01UF
- 10%
0 6.3V 2 X5R
01005
R00M=H6P
1
CI4 4
- 0 . 01UF
— 10%
0 6 .3V 2 X5R
01005
R00M=H6P
ÿ
XR137
5 OK
• i%
• 1/32W
MF
9 01005 z R00M=H6P
AP TO NAND ANC DOVREF
2R143
5 OK
- i%
• 1/32W
MF
9 01005
* R00M=H6P
AP BI NAND ANC1 IQ<0>
M33 .ANCl I0<1>
L32 AP BI NAND ANC1 V C\] A
6 AP BI NAND ANCO IQ<0>
6 AP BI NAND ANCO I0<1>
6
6
AP BI NAND ANCO IQ<2>
AP_B I_NAND_ANC0_IO<3>
AP BI NAND ANCO IO<4>
AP BI NAND ANCO IO<5>
AP BI NAND ANCO IO<6>
AP BI mw ANCO J. O < 7>
f
C50
2 .2UF
20%
4 V
X5R-CERM
0201
ROOMÿNAND
M32 AP BI NAND ANC1 IO<3> N3
K32 AP BI NAND ANC 1 IO<4> N5
J32 AP„„BI NAND ANCl IO<5> L7
H33 AP BI NAND ANC1 oV <£) A
o
G3
H2
J3
K2
L5
K6
J5
H6
G1
LI
H &7
H34 AP BI NAND ANCl IO<7> G7
VDDI
IOO-O
IOl-O
IO2-0
IO3-0
IO4-0
IO5-0
IO6-0
107— 0
IOO-l
101-1
102-1
103-1
104-1
105-1
106-1
107-1
1000MA
VCC
CI8 0
0 .47UF
20%
4 V
X7S
0204
ROOM=NAND
VCCQ
U4
LGA-12X17
Hi
Q
OI
A
H
z
Oa
cu
L
O
h
21
X)
5 0 0MA
20%
4V
X6S
0204
ROOM=NAND
r
C185
1UF
i20%
4 V
X6S
0204
ROOM=NAND
i C376
2 .2UF
20%
4 V
X5R-CERM
0201
ROOM=NAND
OMIT_TABLE
ROOM=NAND
CEO*
CLEO
ALEO
WEO *
REO
REO*
DQSO
DQSO*
R/BO*
CE1*
CLE1
ALEl
WEI*
T
I
T
15UF
20%
4V
X5R
0402
CI82
10UF
T
20%
6.3V
CERM
0402
C377
ROOM=NAND
ROOM=NAND
T
i C378
15UF
T20%
4 V
X5R
0402
ROOM=NAND
A5
c—-
A3 AP TO NAND ANCO CLE
CI AP TO NAND ANCO ALE
oE3
AP TO NAND ANCO WE L
-ÿ4<
nC7 NC 45 AP TO NAND ANCO RE L
J
H4 45 AP BI NAND ANCO DOS
3—4<
E5
NC
NAND
RDYBSYO
C5
C3~ AP TO NAND ANCl CLE
D2 AP TO NAND ANCl ALE
ÿE1
J
AP TO NAND ANCl WE L
TC307
T
10UF
20%
6.3V
CERM
0402
ROOM=NAND
t
i C99<
- 10UF
— 20%
10V
9
2 X5R-CEFH
0402-1
ROOM=NAND
TC209
T
10UF
20%
6.3V
CERM
0402
ROOM=NAND
NOSTUFF
2R160
10 OK
5%
• 1/32W
MF
9 01005 2 ROOM=NAND
T
CI8 7
10UF
20%
6. 3V
CERM
0402
ROOM=NAND
NOSTUFF
2R161
10 OK
5%
1/32W
MF
9 01005 2 ROOM=NAND
_PP_3\
SBW «-.
c
B
i
I
R153
240 ,
1%
1/32W
MF
01005
ROOM=H6P
6AP TO NAND ANCO ALE A3 1
«AP TO NAND ANCO CLE B31
6ap TO NAND ANCO WE L A32
6 45 AP TO NAND ANCO RE L D33
e4 5 AP BI NAND ANCO DOS D34
45 AP PPNQ ZO
E33
«AP TO NAND ANC DOVREF
D31
PPNO_ALE
PPNO_CLE
PPNO_WEN
PPNO_REN
PPNO_DQS
PPNO_ZQ
PPNO VREF
PPNl ALE
PPN1_CLE
PPN1_WEN
PPN1_REN
PPN1_DQS
PPN1_ZQ
PPNl VREF
N34 AP TO_NAND ANC 1_ALE
P31 AP TO NAND ANC1 CLE
N32 AP TO NAND ANC1 WE L
L31 45 AP TO NAND ANC1 RE L
L34 45 AP BI NAND ANCl DOS
K33 45 AP PPNl y.Q
N31 AP TO NAND ANC DOVREF
R55
240 o
-Wv-
mavn
1/
MFl
01005
ROOM=H6P
ROOM=NAND
PP17
P2MM
SM
>P]
PP19
P2MM
ROOM=NAND SM
NAND TO PP TCKC OAO
NAND TO PP TMSC OBO
TCKC
TMSC
Csj
CO
VSS
X
mu
X
I
2
Z
XX
VSSQ
KD 07 r- CS] o o CO O CO
Lu J < 2 U Q U U, O
o O O o\
RE1
NC
REl* 4 5 AP TO NAND ANCl RE L
cD6
DQS1
DOS1*
R/BI*
VREF
ZQ
M4 45 AP BI NAND ANCl DOS
AA<nc
12_ NAND RDYBSY1
G3 KP TO NAND ANC DOVREF
Al 45 NAND PPN ZO
R8
243
-—WV
1%
1/32W
MF
01005
ROOM=NAND
1
B
NOTE: NAND PADS SHOULD BE SHIELDED FROM TRACES WITH A GROUND PLANE
PP2
P2MM
ROOM=H6P SM
1
ROOM=H6P
ROOM=H6P
NOTE: IO<6> PREFERRED BY MATT BYOM
(IS A STATUS READY BIT)
AP BI NAND ANCQ TQ<6>6
SM
45 AP TO NAND ANCO RE L
SM
ra 1 45 AP BI NAND ANCO DOS 6
PP 3
P2MM
PP 1
PP10
P2MM
A
8 7 6 5 4 3