fsmd

Finite State Machine
w/ Data Path
Last updated 9/24/20

FSMD
These slides review FSM’s with Datapath
Upon completion: You should be able to design and
simulate FSM’s with Datapath
EE 3921
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FSMD
• FSMD
• FSM with Data Path
• FSM
• Control the Data Path
• Data Path
• Sequential circuitry to accomplish a task
• Typically register transfer operations
Reg A
Task
(combinational)
Reg B
Task
(combinational)
Reg C
clk
EE 3921
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FSMD
• FSMD
• FSM with Data Path
• Data Path
• Sequential circuitry to accomplish a task
• Typically register transfer operations
Task
(Combinational)
Reg A
clk
EE 3921
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FSMD
• FSMD
Data Path
inputs
Task
(Combinational)
Reg A
outputs
clk
inputs
Next State
Logic
Register
(D-FFs)
Output
Logic
outputs
clk
Control Path
EE 3921
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FSMD
• Fibonacci – FSMD
0 i = 0
fib(i) = 1 i = 1
fib(i-1) + fib(i-2) i > 1
for i= 6
0-1-1-2-3-5-8
EE 3921
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FSMD
• Fibonacci – FSMD
• Input Signals
• clk, rstb
• num_cycles – how many numbers to generate - vector
• startb – start generating (bar)
• Output Signals
• complete – generation complete
• result_latched – Final Fibonacci value
• States
• Idle
• Run
• Complete
EE 3921
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FSMD
• Fibonacci – FSMD
Data Path
fib(0) = 0
fib(1) = 1
fib(i) = fib(i-1) + fib(i-2)
result(i)
Output
Register
result_latched
num_cycles
startb
State Machine
(idle, run, complete)
complete
EE 3921
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FSMD
• Fibonacci – FSMD
Data Path
fib(0) = 0
fib(1) = 1
fib(i) = fib(i-1) + fib(i-2)
result(i)
Output
Register
result_latched
calc
num_cycles
startb
State Machine
(idle, run, complete)
complete
EE 3921
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FSMD
• Fibonacci – FSMD
• Control Path
idle
run
calc 0
complete 1
startb = 0
T
F
cnt
num_cycles
calc 1
complete 0
T
cnt = 1
F
cnt cnt - 1
complete
calc 0
complete 1
EE 3921
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FSMD
• Fibonacci – FSMD
• Data Path
T
calc = 0
F
fib(i-2) 0
fib(i-1) 1
fib(i-1) fib(i-1)
+ fib(i-2)
fib(i-2) fib(i-1)
EE 3921
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FSMD
• Fibonacci – FSMD
calc
EE 3921
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FSMD
• Fibonacci – FSMD - FSM
EE 3921
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FSMD
• Fibonacci – FSMD - FSM
EE 3921
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FSMD
• Fibonacci – FSMD - data path
EE 3921
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FSMD
• Fibonacci – FSMD - data path
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FSMD
• Fibonacci – FSMD
EE 3921
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FSMD
• Fibonacci – FSMD
EE 3921
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FSMD
• Fibonacci – FSMD
EE 3921
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FSMD
• Fibonacci
FSMD
FSM
Data Path
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FSMD
• Fibonacci
Results and intermediate values
N = 6
EE 3921
Indicates the correct vector
size was calculated
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FSMD
• Multiplication
• Shift and add
1110
x 0011
11111110
x 00000011
11111110
x 00000011
11111110
11111110
00000000
00000000
00000000
00000000
00000000
00000000
11111010
EE 3921
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FSMD
• Multiplication
• Want a process that is repetitive
• Repetitive addition multiplication
5 x 4 = 5 + 5 + 5 + 5 i.e. the multiplicand added the multiplier times
• Requires integers – or non-fractional binary numbers for the
multiplier
EE 3921
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FSMD
• Multiplier
Data Path
inputs
Task
(Combinational)
Reg A
outputs
clk
inputs
Next State
Logic
Register
(D-FFs)
Output
Logic
outputs
clk
Control Path
EE 3921
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FSMD
• Multiplier – FSMD
• Control Path
idle
calc 0
complete 1
startb = 0
T
F
run
calc 1
complete 0
finish
done = 1
T
calc 0
complete 1
F
EE 3921
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FSMD
• Multiplier – FSMD
• Data Path
T
calc = 0
F
Load multiplicand
Load multiplier
Result <- 0
T
multiplier
= 0
F
done 1
Result = result +
multiplicand
Multiplier - -
EE 3921
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FSMD
• Multiplier – FSMD
idle
calc 0
complete 1
startb = 0
F
T
calc = 0
F
done
calc
run
T
Load multiplicand
Load multiplier
Result <- 0
T
multiplier
= 0
F
calc 1
complete 0
done = 1
F
done 1
result = result +
multiplicand
T
Multiplier - -
finish
calc 0
complete 1
EE 3921
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FSMD
• Multiplier – FSMD - FSM
EE 3921
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FSMD
• Multiplier – FSMD - FSM
EE 3921
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FSMD
• Multiplier – FSMD – Data path
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FSMD
• Multiplier – FSMD – Data path
EE 3921
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FSMD
• Multiplier – FSMD
EE 3921
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FSMD
• Multiplier – FSMD
EE 3921
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FSMD
• Multiplier
FSMD
FSM
Data Path
EE 3921
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FSMD
• Multiplier - FSMD
Results and intermediate values
Note: Takes “multiplier” number of clock cycles
Takes a variable number of clock cycles
EE 3921
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