List_of_VLSI_Design_Topics_for_Interview_Preparation_1680076989

Comprehensive List of
VLSI Topics For
Interview Preparation
https://www.linkedin.com/in/vivek-arya-532558143

Digital
Electronics
1.
Binary number system
20
Logic gates
3.
Logic
levels
Go combination circuits
circuits
5. Sequential
6. Finite State machines
to sequence detector
8.
Frequency divider/multiplyer
circuit
9. Clock gating concepts
10.
PAL/PLAconcept
* 11.
Designing
of combinational circuit and
sequentialcircuits MUK
using
12. Semiconductor memories
13.
Logic family
Semiconductor Physics
10 PN junction
2. BJT
3.
Doping/impurities
ya bands
Energy
5. Fermilad
6.
Diffusion 8 Drift current
7.
Mobility
https://www.linkedin.com/in/vivek-arya-532558143

-
80 Depletion region
9. sever dioce
10
e-type A p-type
1. Ammobile ions
materials
Basic Network
theory
/8 Basic of R,4,
2. Basic of AVL, KCL
3. Networktheorems
4. RC fircuits
5. Filters -> LPF
HDF
BPF
BSF
APF
6. 1st order RC/RL circuits
70 Nodal analysis, mesh analysis
8. Power
analysis - instanious power
Average powe
9. Two-portNetwork
power
factor
https://www.linkedin.com/in/vivek-arya-532558143

Analog
Circuit Design
/o Basic of BIT, diode
2a
OPAMP - Non
inverting amplifier
Inverting amplifier
adder/substractor
-> Differentiator / Integrator
-> log/Antilog
->
->
3. Feedback amplifier
4. oscillators
50 comparator circuit
60 Schmit trigger
7. filter deligh
80 Differential amplifier
4. Current mirror firc't
100 Basic of MOSFET
operation of mosfet
> I character stics
Region
of operation
↓t
1/0 Common source, common
gate
follower amplifiers
12. Phase Locked loop (PLL)
cutoff, triode saturation
and
source
https://www.linkedin.com/in/vivek-arya-532558143

CMOS
VLSI Design
10 Basicof NMOS and PMOS
2 concepts of it
ina Mos
3. Input output characterstics
7. Region of operation
50
Body effect
Ga channel length modulation
7.
WIL ratio concept
8. Cmos Enverter
9. Noee Margin
100
Designing combinational logicgates
and
sequential
circuit in CMOS
11. CMOS Pass Transistor
190 Transmission gate concept
130 Dynamic mos
design
14. Rationed Logic
150 power dissipation
in CMOS
Dynamicpower
short circ't power
static power
160 CMOS
fabrication process (Step by step)
17. Latch up concepts
18.
Driving strength
19. PVT corners
90. short channel effect
https://www.linkedin.com/in/vivek-arya-532558143

Linux/Unic
/o Features of Linon Os
20 Linux commands you
managing
and
directories.
30 vi editor concept
4. shell
scripting
-> bash, awk, sed
5. Linus commands
disk files
programming and scripting languagi
10 TCL spell smipting
90 procedure in TCL I
grep commands.
3.
regular
expression
4. file handling, Rw operation
50 How contral (far, foreach, whiletc)
6. List and
array
7. Basic of C /ct
8. OOPS concept
90
Array, string, pointers, functions.
10. Data
types
https://www.linkedin.com/in/vivek-arya-532558143

Verilog HDL
1. Verilog data types
po Verilog operators
30 Gak fuel
modelling
4. Data flow modelling
So
Structural
modelling
6a Task and function
70 Write a
verilog testbench
80
Delays,
qu user
defined
event contral.
primitives (WDP]
10. Generated blocks
system Verilog
1. Data types
2. Structures, Array
3. Task sfunctions
4. IPC (Inter procss communication)
5. Semaphall
6. Mailbox
7.
Randomization
8function coverage
9. System verilog Assertions
10.
Program clocking Block
11.
Verification Environment
https://www.linkedin.com/in/vivek-arya-532558143

Universal
verification Methodology (UVM
1 UVM Basic
20
rum
reporting
3. urm
factory
4. wum
sequences
5. UVM transaction level
modelling (TLM)
6. Uum transaction
7. Uum
configuration
8. Num testbench
UVM Test
rum Scrowboard
urm environment
wum agent
4 urm monitor
4 uum Sequencer
uum driver
Whm bass
Uhm scoreboard
9. UVm callback
DFT (Design of
testability)
1. What is DFT?
2. Basic of DFT.
3. Testing of VLSI circuits
https://www.linkedin.com/in/vivek-arya-532558143

4. Fault
modelling
50 Fault Simulation
6a
Boundary scan chain
7. Builtin
Self Test(BIST), LBIST, MBIST
8: scan chain concepts
9. ATPG ·Automatic Test battern
Generation)
100 scan flip-flops
Layout Design
/o knowledge of fabrication steps
40 Metal stackconcepts
30 DRC Rules
4.
fingering concepts
5. Antenna effects
60
Electromigration concepts
7.
Latup concepts
8: stick diagram
9. conceptof tracks, grid,
site rows.
100 well
proximity effect (WPE)
11. Standard cell
layout design
19. Guard ring concepts
13. LVS Us
Kayout
schematic)
https://www.linkedin.com/in/vivek-arya-532558143

Static
timing
Analysis(STA)
1. Basic of timinganalysis
20 Input outputfiles far STA
3.
Timing
arcs
4. Delay concept-> Net delay
5.
cell
delay
timing models - gate
day models
-> not clay models
60 setup /Hold concepts
7.
Fixing Setup/old Violation
I.
Timing
paths
9. timing checks
10
timing exceptions
I
timing constraints
10
timing reports
L
13. PUT corners
140 OCU, AOCU, and POCV
15. Global Setup S Hold time
16. Skews
latency
17. multi-mode multi corner
analysis
180
signal integrity concept
19. Crosstalk analysis
200 CRPR (Clock Reconvergente Pessimism
removal)
210 Time
Borrowing concept
https://www.linkedin.com/in/vivek-arya-532558143

22. SPEF, SDC,,:lib, SDF.
23. Uncertainty, fitter, minimum pulse width.
Physical Design
1.
Physical Design flow
20 Floor
planning, power planning
3. Placement
40 clocktree synthesis (CTS)
5j: Routing
signolf
Fo
Physical only cells Tap cells
The cells
filler cells
Decap cells
endcapcells
8. Low power concept-UPF, special far
power planning
1 isolation cells
2. Level Shifter
3.
Retention registers
4. on
Always
cells
https://www.linkedin.com/in/vivek-arya-532558143

9. LEF, DEFfiles, tent files, its, lib,V
10.
Timing library
11 v LVS, DRC, ERC checks
120 Hard macross soft
macros
130 IR Drop
140 Temperation version
15.
Congestion Analysis
16. power analysis
170 NUT, LVT, SUT Cells
18. NDR Rules
-> Hard
19. Blockages
-> soft
-> partial
20. Macro placementguidling
21 Latup-up - whatisLatch-up ?
-> Reason for it
-> How to fix it.
22. Electro migration - WhatiseM?
-> Reason far it
-> How to fix it.
23. Antenna effect -> What is antenna
effect?
->
-
reason
far it.
How to fix it.
https://www.linkedin.com/in/vivek-arya-532558143

24.
synthers
-> Translation
->
logicoptimization
-> Mapping
25. synthesisHow
26. Goal of synthesis
27. Types of Floorplan
Extra to biss
10 Basic FIFO concept
2. Protocols-UART, I2C, SPI, AMBA
3.
Metastability
concept
4. Clock domain
crossing (CDC)
5. LINT concept
6.
Aptitude
70
Memory - SRAM
-> DRAM
-> RIW operation
8. EDA tools
PNR tools-synopsys /C2
timing-prime time
I layout-cadence virtuoso
4 Simulation
-
Vilinuvivado,
US
Synthesis-synopsys design complier
https://www.linkedin.com/in/vivek-arya-532558143