GEORGE THEODORIDIS - VLSI Design Laboratory

GEORGE THEODORIDIS
Last Name: Theodoridis
First Name: George
Position: Assistant Professor
Address: VLSI Design Laboratory
Section of Electronics and Computers
Department of Electrical & Computer Engineering
Patras University
26500, Rio- Patras, Greece
Phone Number: +30 2610 996822
Fax Number: +302610 994798
e-mail:theodor@ece.upatras.gr
EDUCATION
Diploma in Electrical Engineering, Electrical and Computer Department, University
of Patras (July 1994)
Ph.D., Electrical and Computer Department, University of Patras (July 2001), title of
thesis: “Methods for estimating and techniques for reducing the power consumption
of digital integrated circuits.”
RESEARCH INTERESTS
• Design of digital VLSI circuits and Systems with emphasis in high performance,
low-power consumption, and application specific integrated circuits
• Design of Embedded Systems
• Development of Reconfigurable Hardware Architectures
• Development of power-aware design techniques and power consumption
estimation methodologies at gate and register transfer level
Dr. Theodoridis has published fifty-one (51) articles in international technical, books,
journals, and conference proceedings. He has 150 citations on his published work (not
included self-citations).
PROFESSIONAL EXPERIENCE
06/01-03/02: ALMA TECHNOLOGIES S.A. (Co-founder of the company).
03/02-05/03 Research at the VLSI Design Laboratory, Electrical and Computer
Department, University of Patras, Greece.
ACADEMIC POSITIONS
05/2003 – 06/2009: Lecturer at the Physics Department (Section of Electronics &
Computers) of Aristotle University of Thessaloniki, Greece
07/2009 – today: Assistant professor at the Department of Electrical & Computer
Engineering, Patras University

TEACHING
Undergraduate courses
• Aristotle University of Thessaloniki (2003-2009): Computer Architecture, VLSI
Design, Electronics Laboratory course.
• Patras University (2009 - ): VLSI Design I, VLSI Design II, Integrated Systems
Design - VLSI, Digital Design Logic.
• Postgraduate courses
• Aristotle University of Thessaloniki (2003-2009): Systems Synthesis, Electronic
Circuits Laboratory
• Patras University (2009 - ): Systems on integrated circuits.
PARTICIPATION IN RESEARCH AND DEVELOPMENT
PROJECTS
• Researcher in “QUICKCHIPS: A system supporting ASIC design and providing
rapid turnaround prototyping”, (Esprit Project-6043).
• Researcher in “HEAR: Design of hearing-aid processors”", (Esprit Project-8560).
• Researcher in “MEDCHIP”, (Esprit Project-8010).
• Researcher in “LPGD: A Low Power Methodology/Flow and its Application to the
Implementation of a DCS 1800-GSM/DECT Modulator-Demodulator” (ESPRIT-
25256).
• Researcher in “EASY: Energy-Aware SYstem-on-Chip of the HIPERLAN/2
standard”, (IST-2000-30093),
• Researcher in “AMDREL: Architecture and Methodologies for Dynamic
REconfigurable Logic”, (IST-2001-34379).
He also has participated in a large number of national projects.
MEMBER
• IEEE Computer Society
• IEEE Circuits and Systems Society
• Greek Technical Champers
SERVICES
Member of Program and Technical Committees:
• International Conference on Computer Design (CDES-05).
• International Conference on embedded Computer Systems: Architectures
MΟdeling and Simulation (SAMOS) (2007 - 2010)
• International Conference in Very Large Scale Integration – System on Chip (VLSI-
SOC 08)
• International Conference on Electronics, Circuits and Systems (ICECS 2010).
Reviewer:
• IEEE – Transaction on Very Large Scale Integrated Systems,
• ΙΕΕ – Proceedings on Computers & Digital techniques
• ΙΕΕΕ – International Conference on Electronics, Circuits and Systems (ICECS).
• ΙΕΕΕ – International Symposium on Circuits And Systems (ISCAS).
• ΙΕΕΕ – Design Automation & Test in Europe (DATE).

• ΙΕΕΕ - International Conference Great Lakes VLSI Design (GLVLSI).
• International Workshop on Power and Timing Modelling, Optimization and
Simulation (PATMOS).
PUBLICATIONS
A. Ph. D., thesis:
[A1] “Methods for estimating and techniques for reducing the power consumption of
digital integrated circuits”, University of Patras, Greece, 2001.
Β. Book chapters
[Β1] G. Theodoridis and C. Goutis, “Logic Level Power Estimation”, in “Designing
CMOS Circuits for Low Power”, Kluwer Academic Publishers, 2002.
[Β2] G. Theodoridis and D. Soudris, “Logic Level Power Optimization”, in
“Designing CMOS Circuits for Low Power”, Kluwer Academic Publishers,
2002.
[Β3] G. Theodoridis, D. Soudris, and S. Vassiliadis, “A survey of coarse-grain
reconfigurable architectures and CAD tools”, in Fine- and Coarse-Grain
Reconfigurable Computing, Springer; 1 edition (December 6, 2007).
C. Articles in journals
[C1] Theodoridis G., Theoharis S., Soudris D., Goutis C., “A New Method for Low-
Power Design of Two-Level Logic Circuits”, in VLSI Design, Journal of
Custom-Chip Design, Simulation and Testing, Taylor & Francis, Vol. 9, No. 2.,
pp. 147-157, 1999.
[C2] Theodoridis G., Theoharis S., Soudris D., Goutis C., “Method for Minimizing
the Switching Activity of Two-Level Logic Circuits”, in IEE Proc. Computers
& Digital Techniques, Vol. 145, No. 5, pp. 357-363, Sept. 1998.
[C3] Theodoridis G., Theoharis S., Soudris D., Goutis C., “Switching Activity
Estimation under Real-Gate Delay Using Timed Boolean Functions”, in IEE
Proc. Computers & Digital Techniques, Vol. 147, No. 6, pp. 444-450,
November 2000.
[C4] Theoharis S, Theodoridis G., P. Merakos and Goutis C., “Accurate Data Path
Models for Fast RT-Level Power Estimation”, in IEE Proc. Computers &
Digital Techniques, Vol. 147, No. 4, pp. 209-214, July 2000.
[C5] Theodoridis G., Theoharis S., Soudris D., Goutis C., “A Probabilistic Power
Estimation Method for Combinational Circuits Under Real Gate Delay Model”,
in VLSI Design, Journal of Custom-Chip Design, Simulation and Testing,
Taylor & Francis, Vol. 12, No. 1., pp. 69-79, 2001.
[C6] Theodoridis G., Theoharis S., Soudris D., Goutis C., “A Fast and Accurate
Method of Power Estimation for Logic Level Networks”, in VLSI Design,
Journal of Custom-Chip Design, Simulation and Testing, Taylor & Francis,
Vol. 12, No. 2., pp. 205-219 (special issue on Low-Power Design), 2001.
[C7] Theoharis S., Theodoridis G., Soudris D. and Goutis C., “A Fast and Accurate
Delay-Dependent Method for Switching Estimation of Large Combinational
Circuits”, in Journal of Systems Architecture (JSA), Volume 48, Issue 4-5, pp.
113-124, 2002.
[C8] Kitsos P, Theodoridis G., and Koufopavlou O, “An efficient reconfigurable
multiplier for Galois field –GF(2 m )”, in Journal of Microelectronics, Elsevier
Science Publisher, vol. 43, pp. 975-980, 2003.

[C9] N. Zervas, G. Theodoridis, and D. Soudris, “Behavioral-Level Event-Driven
Power Management for DECT Digital Receivers” in Journal of
Microelectronics, Elsevier Science Publisher, vol 36, pp. 163-172, 2005.
[C10] A. Milidonis, G. Dimitroulakos, M. D. Galanis, G. Theodoridis, C. Goutis, and
F.Catthoor, “A Framework for Data Partitioning for C++ Data-Intensive
Applications” in Design Automation of Embedded Systems (DAES), Springer
Link, vol. 9., pp. 101-121, 2004.
[C11] M. D. Galanis, G. Theodoridis, S. Tragoudas, and C.E. Goutis, “A
Reconfigurable Coarse-Grain Data-Path for Accelerating Computational
Intensive Kernels”, in Journal of Circuits, Systems, and Computers, World
Scientific, Vol. 14, pp. 877-893, 2005.
[C12] A.P. Kakarountas, H.E. Michail, A. Milidonis, G. Theodoridis, and C.E.
Goutis, “A Performance Efficient Hardware Implementation for the Encrypted
Shared Storage Media Standard”, in WSEAS Transactions on Computers ,
WSEAS, Issue 10, Vol. 4, pp. 1417-1425, October 2005.
[C13] M. D. Galanis, G. Theodoridis, S. Tragoudas, and C.E. Goutis, “A High-
Performance Data-Path for Synthesizing DSP Kernels” in IEEE Transaction on
Computer Aided Design, vol. 25. No 6, pp. 1154-1163, June 2006.
[C14] A. P. Kakarountas, H. Michail, G. Theodoridis, A. Milidonis, and C. E.Goutis,
“High-Speed FPGA Implementation of Secure Hash Algorithm for IPSec and
VPN Applications”, in Journal of Supercomputing, Springer Link, vol. 37, pp.
179-195, 2006.
[C15] N. Vassiliadis, N. Kavvadias, G. Theodoridis, and S. Nikolaidis, “A RISC
Architecture Extended by an Efficient Tightly Coupled Reconfigurable Unit”, in
International Journal of Electronics, Taylor & Francis, vol.93, No. 6., pp.421-
438, 2006 (Invalided, Special Issue Paper of ARC05 conference).
[C16] A .P. Kakarountas, N. D. Zervas, G. Theodoridis, H. E. Michail, and D.
Soudris, “Power Management Through Dynamic Frequency Scaling for Low
and Medium Bit-Rate Digital Receivers”, in Journal of Low Power Electronics,
Vol.2, No. 3, pp. 356-364(9), December 2006.
[C17] N. Vassiliadis, G. Theodoridis, and S. Nikolaidis, “Exploring Opportunities to
Improve the Performance of a Reconfigurable Instruction Set Processor”, in
International Journal of Electronics, Vol. 94, Issue 5, pp. 481-500, May 2007,
(Invalided, Special Issue Paper of ARC06 conference).
[C18] M.D. Galanis, A. Milidonis, G. Theodoridis, D. Soudris, and C.E. Goutis,
“Automated framework for partitioning DSP applications in hybrid
reconfigurable platforms”, in Microprocessors and Microsystems Journal,
Elsevier Science Publisher, Vol. 31, Issue 1, pp.1-14, 2007.
[C19] N. Vassiliadis, G. Theodoridis, and S. Nikolaidis, “The ARISE Approach for
Extending Embedded Processors With Arbitrary Hardware Accelerators” in
IEEE Trans. on Very Large Scale Integration (VLSI), pp. 221-223, Feb. 2009.
[C20] G. Theodoridis, N. Vassiliadis, and S. Nikolaidis, “An integer linear
programming model for mapping applications on hybrid systems, in IET (IEE)
Computers & Digital Techniques, Vol. 3, No.1, pp. 33-42, Jan. 2009.
[C21] N. Vassiliadis, G. Theodoridis, and S. Nikolaidis, “An Application
Development Framework for ARISE Reconfigurable Processors”, in ACM
Transactions on Reconfigurable Technology and Systems, Vol. 2, No. 4, 2009.

D. Articles in conferences proceedings
[D1] Theodoridis G., Theoharis S., Soudris D., Koufopavlou O. and Goutis C., “Α
Novel Approach for Reducing the Switching Activity in Two Level Circuits”, in
Proc. of IEEE International Conference on Electronics, Circuits and Systems
(ICECS'96), vol. 2, pp. 840-843, October 1996.
[D2] Soudris D., Theodoridis G., Theoharis S., and Thanailakis A., “Low Power
Design of Array Architectures”, in Proc. of IEEE International Conference on
Electronics, Circuits and Systems (ICECS'96), vol. 1, pp. 120-123, October.
1996.
[D3] Theoharis S., Theodoridis G., Soudris D. and Goutis C., “A New Method for
Switching Activity Estimation of Logic Networks”, in Proc. of International
Workshop on Power And Timing Modeling, Optimization and Simulation
(PATMOS), pp. 131-140, 1997.
[D4] Theoharis S., Theodoridis G., Soudris D. and Goutis C., “Accurate Data Path
Models for RT-Level Power Estimation”, in Proc. of International Workshop on
Power And Timing Modeling, Optimization and Simulation (PATMOS), pp.
213-222, 1998.
[D5] Theodoridis G., Theoharis S., Soudris D., Goutis C., “An Efficient Probabilistic
Method For Logic Circuits Using Real Delay Model” in Proc. of IEEE
International Symposium on Circuits & Systems (ISCAS), pp. 286-289 1999.
[D6] Theoharis S., Theodoridis G., Zervas N. and Goutis C., “Accurate and Fast
Power Estimation Of Large Combinational Circuits” in Proc. of International
Workshop on Power And Timing Modeling, Optimization and Simulation
(PATMOS), pp. 199-208, 1999.
[D7] D. Soudris, N.D. Zervas, M. Perakis, S. Theoharis, G. Theodoridis, G. Kalivas,
C. Dre, C.E. Goutis, and A. Thanailakis, “On the Low Power Design of Digital
Receivers for Wireless Applications”, in Proc of IEEE Conference on Design
Automation and Test in Europe (DATE-User Forum), pp. 255-259, 2000.
[D8] G. Theodoridis, D. Soudris, and C. Goutis “Accurate Power Estimation of
Logic Structures Based on Timed Boolean Functions”, in Proc. of International
Workshop on Power And Timing Modeling, Optimization and Simulation
(PATMOS), pp. 76-87, 2000.
[D9] N. D. Zervas, S. Theoharis, A. Kakaroudas, D. Soudris. G. Theodoridis, and C.
Goutis “Reducing Power Consumption through Dynamic Frequency Scaling for
a Class of Digital Receivers”, in Proc. of International Workshop on Power And
Timing Modeling, Optimization and Simulation (PATMOS), pp. 47-55, 2000.
[D10] D.Soudris, M.Perakis, X.Mizas, V.Madridis, C.Dre, A.Tzimas, E.Metaxakis,
G.Kalivas, N.Zervas, S.Theoharis, G.Theodoridis, A.Thanailakis, and C.Goutis
“Low-Power Design of a Multi-Mode Transceiver”, in Proc. of IEEE
International Symposium on Circuits & Systems (ISCAS), pp. 721-724, 2000.
[D11] Kitsos P, Theodoridis G., and Koufopavlou O, “An Efficient Reconfigurable
Multiplier in GF(2 m ) for Elliptic Curve Cryptosystem”, in Proc. of IEEE
International Conference on Electronics, Circuits and Systems (ICECS'03).
[D12] Kakaroudas A. Theodoridis G., and Goutis C, “A Novel High-Speed Counter
with Counting Rate Independent of the Counter’s Length”, in Proc. of IEEE
International Conference on Electronics, Circuits and Systems (ICECS'03), pp.
1164-1167.
[D13] Dimitroulakos G. Milidonis A., Galanis M, Theodoridis G., Goutis C. and
Catthoor F, “Power Aware Data Type Refinement on the HIPELAN 2”, in Proc.

of IEEE International Conference on Electronics, Circuits and Systems
(ICECS'03).
[D14] M. D. Galanis, G. Theodoridis, S. Tragoudas, and C. E. Goutis, "Synthesizing
DSP Kernels with a High-Performance Data-Path Architecture", in Proc. of 12th
IEEE Mediterranean Electrotechnical Conference (MELECON 2004), pp. 221-
225, 2004.
[D15] M.D. Galanis, G. Theodoridis, S. Tragoudas, D. Soudris, and C.E. Goutis,
“Accelerating DSP Applications on a Mixed Granularity Platform with a new
Reconfigurable Coarse-Grain Data-Path”, in Symposium on Field-
Programmable Custom Computing Machines (FCCM), 2004.
[D16] M. D. Galanis, G. Theodoridis, S. Tragoudas, D. Soudris, and C. E. Goutis,
“A Novel Data-Path for Accelerating DSP Kernels”, in proc. of Embedded
Computer Systems: Architectures, MOdeling, and Simulation workshop
(SAMOS) 2004, LNCS 3133, pp. 363–372, 2004, Springer-Verlag Berlin
Heidelberg 2004.
[D17] M. D. Galanis, G. Theodoridis, S. Tragoudas, D. Soudris, and C. E. Goutis,
“Mapping DSP Applications to a High-Performance Reconfigurable Coarse-
Grain Data-Path”, in Proc of of International Conference on Field
Programming Logic and its applications (FPL 2004), LNCS 3203, pp. 868–873,
2004, Springer-Verlag Berlin Heidelberg 2004.
[D18] A. Milidonis, G. Dimitroulakos, M. D. Galanis, G. Theodoridis, C. Goutis,
and F.Catthoor, “An Automated C++ Code and Data Partitioning Framework
for Data Management of Data-Intensive Applications” in Proc. of International
Symposium on Software and Compilers for Embedded Systems (SCOPES 04),
pp. 122-136, 2004.
[D19] D. Karatasos, A. Kakaroudas, G. Theodoridis, and C.E. Goutis, “A Novel
Constant-Time Fault-Secure Binary Counter”, in Proc. of f International
Workshop on Power and Timing Modeling, Optimization and Simulation
(PATMOS), pp. 742-749, 2204.
[D20] M. D. Galanis, A. Milidonis, G. Theodoridis, D. Soudris, and C. E. Goutis, “A
Partitioning Methodology for Accelerating Applications in Hybrid
Reconfigurable Platforms”, in proc. of Design Automation and Testing in
Europe (DATE 05), pp. 247-252, Designers Forum, 2005.
[D21] N. Vassiliadis, N. Kavvadias, G. Theodoridis, and S. Nikolaidis "A RISC
Architecture Extended by an Efficient Tightly Coupled Reconfigurable Unit"
accepted for publication in International Workshop on Applied Reconfigurable
Computing (ARC 2005).
[D22] M. D. Galanis, A. Milidonis, G. Theodoridis, D. Soudirs, and C.E. Goutis, “A
Framework for Partitioning Computational Intensive Applications in Hybrid
Reconfigurable Platforms”, in Proc. of IEEE Parallel and Distributed
Processing Symposium (Reconfigurable Architectures Workshop - RAW), pp.
157-168, 2005.
[D23] A. Chromoviti, N. Vassiliadis, G. Theodoridis, and S. Nikolaidis, “Enhancing
Embedded Processors with Specific Instruction Set Extensions for Network
Applications”, in Proc. of IEEE Workshop on Intelligent Data Acquisition and
Advanced Computing Systems (IDAACS), pp. 199-203, 2005.
[D24] A. P. Kakakrountas, G. Theodoridis, T. Laopoulos and C. E. Goutis, “High-
Speed Implementation of the SHA-1 Hash Function”, in Proc. of IEEE
Workshop on Intelligent Data Acquisition and Advanced Computing Systems
(IDAACS), pp. 211-215, 2005.

[D25] N. Vassiliadis, G. Theodoridis, and S. Nikolaidis, “An Automated
Development Framework for a RISC Processor with Reconfigurable Instruction
Set Extensions”, in Proc. of IEEE Parallel and Distributed Processing
Symposium (Reconfigurable Architectures Workshop - RAW), pp. 25-29, 2006,
[D26] N. Vassiliadis, G. Theodoridis, and S. Nikolaidis, “Enhancing a
Reconfigurable Instruction Set Processor with Partial Predication and Virtual
Opcode Support”, to appear in IEEE International Workshop on Applied
Reconfigurable Computing (ARC), 2006.
[D27] N. Vassiliadis, G. Theodoridis and S. Nikolaidis, “The ARISE Reconfigurable
Instruction Set Extensions Framework”, in Intern. Conf. on Embedded
Computer Systems: Architectures, Modeling, and Simulation (IC-SAMOS),
2007.
[D28] N. Vassiliadis, G. Theodoridis and S. Nikolaidis, “ARISE Machines:
Extending Processors with Hybrid Accelerators”, to appear in IEEE
International Workshop on Applied Reconfigurable Computing (ARC), 2008.
[D29] A. P. Kakarountas, H.E. Michail, G. Theodoridis, and C. E. Goutis, “A
Segmented High-Speed Counter Based on the Use of Redundant Bits”, in
Proc. of IEEE Int. Conf. on VLSI Systems on Chip (VLSI-SOC), pp. 42-46,
2008.
[D30] N. Vassiliadis, G. Theodoridis and S. Nikolaidis, “A Flexible Simulation
Framework for Reconfigurable Processors”, in Proc. of IEEE Int. Conf. on
VLSI Systems on Chip (VLSI-SOC), pp. 140-143, 2008.
Ε. Translation of scientific books (in Greek)
[Ε1] “Circuit Design with VHDL”, A. Pedroni, MIT Press, (Editions Klidarithmos,
2010, Greece).
[E2] “Digital Integrated Circuits”, J. Rabaey, A. Chandrakasan, and B. Nikolic,
Prentice Hall, (Editions Klidarithmos, 2006, Greece).