Ching-Hsuan Ma

FPGA
Ching-Hsuan Ma

• Basic concepts
Outline
• Combinational circuit
• Sequential circuit
• Finite state machine

• Basic concepts
Outline
• Combinational circuit
• Sequential circuit
• Finite state machine

• Modules
Basic concepts
module ();
…
…
endmodule
The half adder could be defined as a module as follows:
module HA(…);
…
…
endmodule
HA

• Ports
module HA(a,b,sum,c_out);
input a, b;
output sum,c_out;
…
…
endmodule
Basic concepts
a
b
HA
sum
c_out

Basic concepts
• Structured procedures
module HA(a,b,sum,c_out);
input a, b;
output sum,c_out;
reg sum, c_out;
always@(a or b)
begin
sum = a ^ b;
c_out = a & b;
end
endmodule

Basic concepts
• Number specification
4’b1111; // a 4-bit binary number
12’habc; // a 12-bit hexadecimal number
10’d1023; // a 10-bit decimal number

• Data types
Basic concepts
Nets represent connections between hardware elements.
wire GND = 1’b0; //1-bit net
wire [3:0] data; //4-bit net
Registers represent data storage elements.
reg data1;
reg [7:0] data2;

Basic concepts
• Conditional statements
if () true_statement;
else false_statement;
Ex: a = ~b
If (a==1’b0) begin
b = 1’b1;
end
else begin
b = 1’b0;
end

• Case statement
Basic concepts
case (expression)
alternative1: statement1;
alternative2: statement2;
alternative3: statement3;
default: default_statement;
endcase
Ex: ALU
case (opcode)
2’b00: out=a+b;
2’b01: out=a-b;
2’b10: out=a&b;
default: out=a|b;
endcase

• Basic concepts
Outline
• Combinational circuit
• Sequential circuit
• Finite state machine

Combinational circuit
• A combinational circuit consists of logic gates whose
outputs at any time are determined directly from the
present combination of inputs without regard to previous
inputs.

• Always block
Combinational circuit
– always@(sensitive list) begin
….
end module adder(a, b, c_in, sum, c_out);
input a, b, c_in;
output sum, c_out;
reg sum, c_out;
always@(a or b or c_in)
begin
{c_out, sum} = a + b + c_in;
end
endmodule

Combinational circuit
• Continuous assignment
– assign wire_variable = expression;
module adder(a, b, c_in, sum, c_out);
input a, b, c_in;
output sum, c_out;
wire sum, c_out;
assign {c_out, sum} = a + b + c_in;
endmodule

Combinational circuit
• The same result
a
b
c_in
1' h0 --
1' h0 --
Add0
A[1..0]
B[1..0]
ADDER
OUT[1..0]
1' h0 --
Add1
A[1..0]
B[1..0]
ADDER
OUT[1..0]
sum
c_out

• Basic concepts
Outline
• Combinational circuit
• Sequential circuit
• Finite state machine

Sequential circuit
• A sequential circuit is a system whose
outputs at any time are determined from
the present combination of inputs and the
previous inputs or outputs.

Sequential circuit
• always@(posedge clk) begin
…..
end
• always@(negedge clk) begin
…..
end

Sequential circuit
• EX: a 10-bit counter
module counter(clk, reset, D, Q);
input clk, reset;
output [9:0] count;
reg [9:0] count;
always@(posedge clk)
begin
if (reset) count=0;
else count=count + 1’b1;
end
endmodule

• Basic concepts
Outline
• Combinational circuit
• Sequential circuit
• Finite state machine

Finite state machine
• Finite state machine (FSM)
– 2C1S
C: combinational circuit, S: sequential circuit

• Top module
Moore machine
module Moore_FSM(Clock, Reset, In, Out);
input Clock, Reset, In;
output [1:0] Out;
reg [1:0] Out;
reg [1:0] State, NextState;
parameter S0=2'b00, S1=2'b01, S2=2'b10, S3=2'b11;
….
endmodule

• 1S, state logic
Moore machine
always @(posedge Clock or posedge Reset)
begin
if(Reset)
State = S0;
else
State = NextState;
end

Moore machine
• 2C, next state logic and output logic
always @(In or State)
begin
case(State)
S0: begin
if(In == 1)
NextState = S2;
else
NextState = S0;
end
….
endcase
end
always @(State)
begin
case(State)
S0:Out = 0;
S1:Out = 1;
S2:Out = 1;
S3:Out = 0;
endcase
end

• Top module
Mealy machine
module Mealy_FSM(Clock, Reset, In, Out);
input Clock, Reset, In;
output [1:0] Out;
reg [1:0] Out;
reg [1:0] State, NextState;
parameter S0=2'b00, S1=2'b01, S2=2'b10, S3=2'b11;
….
endmodule

Mealy machine
• 1S, state logic(the same with Moore
machine)
always @(posedge Clock or posedge Reset)
begin
if(Reset)
State = S0;
else
State = NextState;
end

Mealy machine
• 2C, next state logic and output logic
always @(In or State)
begin
case(State)
S0: begin
if(In == 1)
begin
NextState = S1;
end
else
begin
NextState = S0;
end
end
…
endcase
end
always @(In or State)
begin
case(State)
S0: begin
if(In == 1)
begin
Out = 1;
end
else
begin
Out = 0;
end
end
…
endcase
end

Reference
• 數位IC設計入門-Verilog
作者:陳培殷等編著
年份:2008年1版
ISBN:9789866889905
書號:EE0343
規格:16開/平裝/單色
頁數:328
出版商:滄海書局