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5-3-20 EHT Compensation<br />
The vertical waveform can be scaled according to the average beam current. This is used to compensate the effects of<br />
electric high-tension changes due to beam current variations. EHT compensation for East/West deflection is done with<br />
an offset corresponding to the average beam current.<br />
5-3-21 Reset Function<br />
Reset of all VDP functions is performed by the RESQ pin. When this pin becomes active, all internal registers and<br />
counters are lost.<br />
5-3-22 Standby and Power-On<br />
The VDP does not have a standby mode. To disable all the analogue and digital video functions, it is necessary to<br />
switch off the supplies for analogue front-end (VSUP AF ), analogue back-end (VSUP AB ) and digital circuitry<br />
(VSUP D ).<br />
5-4- Microcontroller<br />
5-4-1 Introduction<br />
The TV controller basically consists of the CPU, RAM, ROM, and a number of peripheral modules.<br />
For instance:<br />
– a memory banking module is included to allow access to more than 64 kB memory.<br />
– a bootloader software is included to allow in-system-downloading of external code to Flash memory via the I 2 C<br />
interface.<br />
The TV controller runs the complete software necessary to control a TV set. The software includes control of the audio,<br />
video, OSD, and text processors on chip, as well, as control of external devices like tuner or stereo decoder.<br />
Communication between the TV controller and external devices is done either via I 2 C bus interface or via programmable<br />
port pins. The TV Controller is clocked with f OSC = f XTAL /2.<br />
5-4-2 CPU<br />
The CPU is fully compatible to WDC’s W65C02 micro-processor. The processor has 8-bit registers/accumulator, an 8bit<br />
data bus, and a 16-bit address bus.<br />
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