designfeature DSP assembly language - EDN

designfeature DSP assembly language
cle-accurate, instructionlevel
simulator lets you simulate
your application in real
time. Also, the VisualDSP
tool features a well-defined
application programming
interface (API). Third-party
products, runtime operating
systems, emulators, HLL
compilers, and multiprocessor
hardware can interface
seamlessly with VisualDSP
and thereby simplify tool integration.VisualDSP
follows
the COM API format. Two
API tools, Target Wizard and
API Tester, are also available.
You can find links to third
parties that support Analog’s
DSP product lines at www.
analog.com/support/3rd_
party/third_party.html.
Texas Instruments TMS-
320C6x DSP features two
datapaths—each with 16 32-bit registers—shared
by eight functional units.
The C6x is a very-long-instructionword
(VLIW) processor; a composite
instruction (line), formed by concatenating
n short instructions, controls its
functional units. In the C6x, the short
instructions are 32 bits wide, and the
line consists of a maximum of eight
32-bit instructions. Therefore,
the C6x packs instructions to avoid inefficient
use of program memory.
FOR MORE INFORMATION...
Instruction packing may result in
alignment restrictions between lines and
the physical-memory organization. In
the C6x, the program is organized as
eight instruction lines, or fetch packets.
You may divide each fetch packet into
groups of instructions or “execute packets,”which
are issued in parallel. The C6x
is restricted because the execute packet
must be within an eight-word boundary.
Every fetch packet must start with an execute
packet. This stipulation implies that
For information on products such as those discussed in this article, circle the appropriate numbers
on the Information Retrieval Service card or use EDN’s InfoAccess service. When you contact
any of the following manufacturers directly, please let them know you read about their products
in EDN.
Analog Devices
Norwood, MA
1-781-329-4700
fax 1-781-326-8703
www.analog.com/dsp/
Circle No. 301
DSPecialists GmbH
Berlin, Germany
+49 30 467 805 60
fax +49 30 467 805 99
www.DSPecialists.de
Circle No. 302
Texas Instruments
Dallas, TX
1-972-644-5580
fax 1-972-480-7800
www.ti.com
Circle No. 303
ZSP Corp
Santa Clara, CA
1-408-450-6207
fax 1-408-986-1687
www.zsp.com
Circle No. 304
The Code Composer IDE features the Assembly Optimizer tool. Using the
Assembly Optimizer, you can write conventional-looking C6000 assembly
code without bothering with parallel instructions, instruction latencies, or
register usage. The Assembly Optimizer then schedules the instructions,
taking into account the C6000’s parallel architecture.
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For more information on the
products available from all of
the vendors listed in this box,
circle one number on the reader
service card. Circle No. 305
you must pad fetch packets
that do not end with an execute
packet with no-op-
Figure 3
eration instructions. Furthermore,
the need to track
various functional units in a
VLIW architecture can rapidly
overwhelm a DSP programmer.
To help application developers,
TI has introduced the
concept of “linear” assembly
language. Linear assembly language
allows you to write assembly
language without regard
to registers and pipeline
behavior, significantly easing
the task of writing low-level
code. An Assembly Optimizer,
which performs many compilerlike
optimizations, processes
linear assembly by assigning
registers and scheduling
the instructions, effectively
handling all the “hard” problems
associated with writing code for a
pipelined processor (Figure 3).
TI claims that the C6000 compiler offers
an average improvement in execution
speed; it is three times faster than
state-of-the-art fixed-point DSP C compilers.
The C compiler accepts ANSI C
source code and produces efficient C6000
assembly-language source code, performing
a variety of optimizations to improve
the efficiency of the compiled code.
The compiler incorporates four levels of
state-of-the-art generic and target-specific
optimizations. The level of optimizations
is selectable.
Optimizations include those features
specific to the TMS320C6201 processor,
such as software pipelining, if conversion/predicated
execution, memory-address
cloning, memory-address-dependence
elimination, branch optimizations/control-flow
simplification, alias
disambiguation, copy propagation, common
subexpression elimination, redundant
assignment elimination, loop-induction-variable
optimizations/strength
reduction, loop rotation, loop invariant
code motion, inline expansion of function
calls, register tracking/targeting, and
cost-based register allocation. For more
information, visit TI’s DSP third-party
Web site (www.ti.com/sc/docs/dsps/
develop/3party.htm).
Even with all these development tools,
108 edn | January 21, 1999 www.ednmag.com