Design Team Emulation - SystemVerilog
Design Team Emulation - SystemVerilog
Design Team Emulation - SystemVerilog
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Axis Systems, Inc.<br />
<strong>SystemVerilog</strong> Methodology for<br />
Acceleration and <strong>Emulation</strong><br />
© 2003 Axis Systems, Inc. <strong>Design</strong> <strong>Team</strong> <strong>Emulation</strong>
Outline<br />
�� Axis Overview<br />
�� Acceleration & <strong>Emulation</strong> with <strong>SystemVerilog</strong><br />
�� Summary<br />
© 2003 Axis Systems, Inc.<br />
2<br />
<strong>Design</strong> <strong>Team</strong> <strong>Emulation</strong>
Axis Business Focus<br />
Solve verification productivity crisis<br />
© 2003 Axis Systems, Inc.<br />
Deliver software and hardware<br />
verification solutions<br />
Target system and<br />
system-on<br />
system on-a-chip chip designers<br />
Leverage breakthrough innovation of<br />
ReConfigurable Computing technology<br />
3<br />
<strong>Design</strong> <strong>Team</strong> <strong>Emulation</strong>
Axis Breakthrough Technology<br />
ReConfigurable Computing (RCC) for<br />
High Performance Verification Platform<br />
© 2003 Axis Systems, Inc.<br />
programs<br />
data<br />
4<br />
PCI<br />
Patented RCC<br />
<strong>Design</strong> <strong>Team</strong> <strong>Emulation</strong>
<strong>Design</strong> <strong>Team</strong> <strong>Emulation</strong> (DTE)<br />
Methodology<br />
Methodology<br />
�� Multiple Levels of<br />
Abstraction<br />
� Adv Behavioral Debugging<br />
© 2003 Axis Systems, Inc.<br />
5<br />
Benefits<br />
�� IP Model Reuse and<br />
Flexibility<br />
� Single Kernel Database � Fastest Bring Up - Time to<br />
Value<br />
� Easy to Use<br />
� Small Form Factor � Multi-team Access<br />
� HW/SW Co-Verification<br />
� Fast and Efficient<br />
Debugging<br />
<strong>Design</strong> <strong>Team</strong> <strong>Emulation</strong>
Axis Product Overview<br />
Software Solutions<br />
Hardware Platforms<br />
Productivity<br />
Verilog<br />
Xcite 1000<br />
1998 1999 2000 2001 2002<br />
© 2003 Axis Systems, Inc.<br />
3 rd<br />
3rd Party SW<br />
rd Party SW<br />
IP Builder<br />
Xcite 2000<br />
Xchange<br />
6<br />
Xtreme<br />
Xpert<br />
Mixed HDL<br />
Xtreme-II<br />
<strong>Design</strong> <strong>Team</strong> <strong>Emulation</strong><br />
RCC<br />
Model Compiler<br />
XoC<br />
2003
ReConfigurable Computing (RCC)<br />
<strong>Design</strong><br />
RTL<br />
•Always @(posedge clk)<br />
•begin<br />
•rw_bus = istate;<br />
•if (bus_active)<br />
Gate<br />
•Inv inv1 (b, a);<br />
•and and2(c, b, a);<br />
•dffp mydff(q, d, clk);<br />
Behavioral<br />
•Initial<br />
•begin<br />
•$monitor(….);<br />
•$my_pli(…);<br />
Assertion<br />
•assert assert<br />
•(•irq ( == 1’b0)<br />
© 2003 Axis Systems, Inc.<br />
•Sun Host<br />
•Workstation<br />
•RCC<br />
•Cluster<br />
•Interface<br />
7<br />
•RCC<br />
•Cluster<br />
•Millions of<br />
•Reconfigurable<br />
•Computing<br />
•Elements<br />
•Dynamic<br />
•Event<br />
•Signaling<br />
•RCC<br />
•Cluster<br />
•RCC<br />
•Cluster<br />
•RCC<br />
•Cluster<br />
•<strong>Emulation</strong><br />
•Memory<br />
Interface<br />
Core<br />
•SIMD Controller<br />
<strong>Design</strong> <strong>Team</strong> <strong>Emulation</strong><br />
•RCC<br />
•Cluster<br />
•RCC<br />
•Cluster<br />
•RCC<br />
•Cluster
Outline<br />
�� Axis Overview<br />
�� Acceleration & <strong>Emulation</strong> with <strong>SystemVerilog</strong><br />
�� Summary<br />
© 2003 Axis Systems, Inc.<br />
8<br />
<strong>Design</strong> <strong>Team</strong> <strong>Emulation</strong>
Next Generation Verification Flow<br />
Hardware<br />
© 2003 Axis Systems, Inc.<br />
System<br />
RTL reuse Expertise<br />
HW/SW partitioning +<br />
architecture definition<br />
Block level <strong>Design</strong> and<br />
Verification<br />
Subsystem integration<br />
Verification<br />
Physical design/tapeout<br />
Prototype<br />
In-system Full chip<br />
Verification<br />
9<br />
Software<br />
1) <strong>Design</strong> for Verification<br />
–assertion Dev C-based technology<br />
Platform<br />
Software development<br />
(driver, embedded)<br />
2) Testbench technology<br />
Application<br />
SW<br />
Development<br />
3) Assertions accelerated<br />
with Volume Axis tapeout<br />
<strong>Design</strong> <strong>Team</strong> <strong>Emulation</strong>
SVA Acceleration<br />
Testbench<br />
Monitor<br />
SV simulator<br />
Monitor<br />
RTL<br />
© 2003 Axis Systems, Inc.<br />
monitor<br />
Assertions<br />
• Simulation at hardware<br />
speed with Axis RCC<br />
• Assertions run at HW<br />
speed<br />
• Reporting handled by<br />
SW simulator<br />
10<br />
RTL<br />
RTL<br />
RTL<br />
RCC Compiler<br />
Testbench<br />
RTL<br />
RCC<br />
SV simulator<br />
<strong>Design</strong> <strong>Team</strong> <strong>Emulation</strong><br />
Acceleration/<br />
<strong>Emulation</strong><br />
System
Test Bench: HDL (Verilog & VHDL)<br />
�� Transparent kernel integration<br />
�� Direct behavioral mapping + RPC host I/O<br />
�� Target-less <strong>Emulation</strong><br />
© 2003 Axis Systems, Inc.<br />
RCC<br />
DUT<br />
11<br />
Host<br />
<strong>Design</strong> <strong>Team</strong> <strong>Emulation</strong>
Test Bench: Co-Sim (C, Vera, e, SV)<br />
�� Native support for PLI, VPI, VHPI and FLI.<br />
�� Multi-kernel sync overhead limits speed.<br />
RCC<br />
DUT<br />
© 2003 Axis Systems, Inc.<br />
CLK<br />
Host<br />
12<br />
TB<br />
<strong>Design</strong> <strong>Team</strong> <strong>Emulation</strong>
Test Bench: Transaction-based<br />
Co-Simulation<br />
�� Transactors in RCC<br />
�� Better performance by fewer synchronization<br />
�� Limited by Co-Sim synchronization and data object conversion<br />
RCC<br />
© 2003 Axis Systems, Inc.<br />
DUT<br />
CLK<br />
Host<br />
13<br />
TB<br />
<strong>Design</strong> <strong>Team</strong> <strong>Emulation</strong>
<strong>SystemVerilog</strong> Opens<br />
Acceleration Market<br />
�� What has Changed:<br />
© 2003 Axis Systems, Inc.<br />
— Testbench and assertions are embedded within the<br />
design<br />
— Sets natural boundary for testbench parallelism<br />
— Clear interface definition between testbench and<br />
design<br />
14<br />
<strong>Design</strong> <strong>Team</strong> <strong>Emulation</strong>
Embedded Testbench Activates<br />
Inherent Parallelism<br />
TB<br />
© 2003 Axis Systems, Inc.<br />
Now<br />
DUT<br />
(Verilog/<br />
VHDL)<br />
15<br />
<strong>SystemVerilog</strong><br />
<strong>Design</strong> <strong>Team</strong> <strong>Emulation</strong>
Direct Behavioral Modeling<br />
Logic-FPGA<br />
© 2003 Axis Systems, Inc.<br />
Event<br />
Processor<br />
Busy<br />
16<br />
Ctrl<br />
Event<br />
Eval<br />
Busy<br />
<strong>Design</strong> <strong>Team</strong> <strong>Emulation</strong>
<strong>SystemVerilog</strong> Accelerated on RCC<br />
Classes with methods<br />
and inheritance<br />
Interface protocol specification<br />
access control and interface methods<br />
Architecture<br />
configuration<br />
Dynamic<br />
generation of<br />
hardware<br />
Signed numbers<br />
Event handling<br />
4 state logic<br />
Assertions<br />
Protocol checkers<br />
temporal assertions<br />
Simple assertions<br />
VHDL multi-D Like<br />
arrays<br />
Constructs<br />
Automatic variables<br />
Basic datatypes<br />
(bit, int…)<br />
Hardware concurrency<br />
design entity modularization<br />
Advanced data structures<br />
Records, enums<br />
Basic programming<br />
(for, if, while,..)<br />
Verilog<br />
Gate level modelling and timing<br />
Switch level modeling and timing<br />
© 2003 Axis Systems, Inc.<br />
Associative arrays<br />
Sparse arrays<br />
Process<br />
spawning<br />
ASIC timing<br />
Testbench<br />
Coverage<br />
monitoring<br />
Constructs<br />
Assertion<br />
Processor<br />
RTL<br />
Processor<br />
RTL<br />
Processor<br />
17<br />
Polymorphic directed<br />
random generators<br />
Further programming<br />
(do while, break,<br />
continue<br />
Strings<br />
Packed structures<br />
Behavioral<br />
Processor<br />
Axis RCC<br />
Coverage & Assertion<br />
API<br />
Dynamic<br />
memory<br />
allocation<br />
C interface<br />
Behavioral<br />
Processor<br />
C Programming<br />
Void type<br />
Unions<br />
pointers<br />
Semaphores<br />
<strong>Design</strong> <strong>Team</strong> <strong>Emulation</strong>
Full <strong>SystemVerilog</strong> Acceleration<br />
and <strong>Emulation</strong><br />
RCC<br />
© 2003 Axis Systems, Inc.<br />
DUT<br />
18<br />
TB<br />
Simulator VCS<br />
<strong>Design</strong> <strong>Team</strong> <strong>Emulation</strong>
Summary<br />
�� Integrated <strong>SystemVerilog</strong> solution for<br />
acceleration and emulation<br />
�� <strong>SystemVerilog</strong> changes simulation<br />
acceleration paradigm<br />
�� Axis’ RCC behavioral processors can<br />
directly accelerate and emulation<br />
<strong>SystemVerilog</strong> constructs<br />
© 2003 Axis Systems, Inc.<br />
19<br />
<strong>Design</strong> <strong>Team</strong> <strong>Emulation</strong>
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