Design Team Emulation - SystemVerilog
Design Team Emulation - SystemVerilog
Design Team Emulation - SystemVerilog
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Test Bench: Co-Sim (C, Vera, e, SV)<br />
�� Native support for PLI, VPI, VHPI and FLI.<br />
�� Multi-kernel sync overhead limits speed.<br />
RCC<br />
DUT<br />
© 2003 Axis Systems, Inc.<br />
CLK<br />
Host<br />
12<br />
TB<br />
<strong>Design</strong> <strong>Team</strong> <strong>Emulation</strong>
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