Design Team Emulation - SystemVerilog
Design Team Emulation - SystemVerilog
Design Team Emulation - SystemVerilog
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Test Bench: Transaction-based<br />
Co-Simulation<br />
�� Transactors in RCC<br />
�� Better performance by fewer synchronization<br />
�� Limited by Co-Sim synchronization and data object conversion<br />
RCC<br />
© 2003 Axis Systems, Inc.<br />
DUT<br />
CLK<br />
Host<br />
13<br />
TB<br />
<strong>Design</strong> <strong>Team</strong> <strong>Emulation</strong>
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