Voice Control Function - Holtek Semiconductor Inc.

HT98R068-1 Two-way Radio OTP MCU 


D/N: HA0305E 

Introduction 

The Holtek HT98R068-1 is an ASSP OTP (One-Time Programmable) MCU specifically 

designed for two-way radio communication applications. The internal in-band tone/sub-tone 

processor supports functions, such as emphasis/de-emphasis, CTCSS/DCS encoder/ 

decoder, DTMF encoder/decoder, scramble/descramble, VOX…etc., transmitted to the 

other port by a radio frequency carrier. Using the code to mark the product extended series, 

but it’s still avalible in this text such as the HT98R068-1. 

Operating Principles 

� Sub-tone 

� CTCSS encode/decode 

� DCS encode/decode 

� In-band tone processor 

� DTMF encode/decode 

� Selective call tone (EEA standard) 

� In band tone(user define) 

� Other signals 

� DCS turn-off tone 

� Advanced audio processor 

� Scrambling 

� Companding 

� Emphasis/De-emphasis 

� Digital filter: 12.5k / 25k / HPF(300) filter 

� In-band signal level adjustment function 

� Voice Control(VOX) 

� MIC AGC 

1

Block Diagram 


Hardware Block Function Decription 

� Audio processor unit: A signal process unit, responsible for the audio and signal 

processing. 

� Input unit: The input source selection including MIC OPA, multiplexer and PGA. 

Multiplexer provides selectable audio and modulation signal input such as MICO, AUX, 

BEEP1 and DEMI. 

� Output unit – MOD/SMOD: The signal output port includes MODO for the in-band 

signal output and SMODO for the sub-tone signal output (can use this port if you want 

to decode sub-tone). 

� Output unit – Audio: The audio output port with selective DAC1 and BEEP0 multiplexer 

outputs. 

� MCU unit: The MCU control unit is applied to control the user program code for I/O 

control, flow control etc. 

2

Application Circuit 

The application circuit is divided into three main parts. 


� Clock/PLL circuit: Y1, R7, C16 and C17 are from the PLL external clock source where 

Y1 is a 32,768 KHz crystal to lock the PLL so as to the set frequency. R6, C14 and C15 

are the PLL filter circuits. Refer to the component values for correct circuit designing. 

� MIC/AUX/DEMOD – The microphone/secondary audio/in-band input port: The MIC 

section includes an internal OPA with a gain value = R2 

� . The R2 value can be altered 

R1 

according to actual application requirments. If the internal AGC function is to be used, 

please refer to the AGC section to select this resistance. DEMOD is the in-band signal 

input port after RF demodulation. AUX: This external audio input supports external 

audio applications. In principle, the input signal must be limited in: {signal * PGA 

amplification ratio ≦ VDD*0.7(AD maximum)}. 

� MOD/SMOD/AUDO – In-band/sub-tone/audio output port: The MOD output can 

generate in-band signals connected to the RF input port. The SMOD generates 

sub-tone signals to be applied in applications requiring sub-tones. AUDO: The audio 

signals after demodulation can generate tones through a LPF circuit connected to the 

speaker drive circuit (ex: HT82V739). The output signals showing likes a ladder which 

is applied in describing the precise relation of the adjacent channel power and tone 

quality, but it must be followed with a LPF circuit. 

� Power circuit: The power consumption is so much (25mA@3.3V) at the moment 

turning on the audio processor. Hence, note that the VCC changement effection. Where, 

C11 is the tantalum capacitor for compensation. Considering the mutual interference of 

anolog and digtal signals, it’s recommended that seperate VCC and GND into two 

parts. The power supply and ground portion then are connected respectively by BEAD. 

3

System Clock Switches 


In the system setup preliminary stage, the operating frequency controlled by two groups of 

registers, CTRL2 [7-5, 3-0] and CTRL0 [0] is firstly selected. The description is as follows: 

System Control Register 2 (CTRL2) 

Bit 7 6 5 4 3 2 1 0 

CTRL2 M1 M0 PLLD2 AUPRST PLLEN PLLD1 PLLD0 LXTEN 

POR 0 0 1 0 0 1 1 0 

CTRL2 [3]: ON/OFF PLL mode 1. This bit controls the PLL on/off. The CTRL2 [7-6] bits 

select the PLL ascending frequency which has four system frequencies to meet different 

application requirmennts. The CTRL2 [5] bit selects the PLL divider ratio of the audio 

processor with one and two times provided. The CTRL2 [2-1] bits is the MCU PLL 

divider/multiplier select bits with 1, 2, 4 ratio selections. The CTRL2 [0] bit is LXT low 

speed selection bit, which can request the system to enter the IDLE mode when used 

together with HALT instruction. 

System Control Register 0 (CTRL0) 

Bit 7 6 5 4 3 2 1 0 

CTRL0 PCFG PFDCS - - - PFDC LXTLP CLKMOD 

POR 0 0 - - - 0 0 1 

The CTRL0 [0] bit selects the MCU high speed mode. If CTRL0 [0] =1, the MCU operates 

in the low speed mode (32,768kHz). If CTRL0 [0] = 0, the MCU operates in the PLL mode. 

When using the PLL mode, it is important to note that when the PLL is enabled the PLL 

ascending frequency ratio, MCU and audio processor divider ratio must be first selected 

after which a delay of 10ms (PLL stabilising time) mus be implemented before allowing it 

to be a device clock source. When the MCU is on by using the CTRL0 [0] bit and the 

audio processor is turned on by using the CTRL2 [4] bit, the MCU operates in the PLL 

mode, it is not recommended that change the PLL divider setting. 

PLLEN M1,M0 

PLL 

Speed 

MCU 

PLLD1 , PLLD0 

0,1 (÷1) 1,0 (÷2) 1,1 (0,0) 

Audio Processor 

PLLD2 

0 (÷1) 1 (÷2) 

0 X 32.768K 32.768K 32.768K 

1 00 8.192M 8.192M 4.096M 2.048M 8.192M 4.096M 

1 01 10.24M 10.24M 5.12M 2.56M 10.24M 5.12M 

1 10 12.288M 12.288M 6.144M 3.072M 12.288M 6.144M 

1 11 16.384M 16.384M 8.192M 4.096M 16.384M 8.192M 

X: Don’t care 

MCU & Audio Procrssor PLL Divider Table 

4

PLL Control Flow - for MCU 


Flow description: 

: Setup the PLL divider and PLL enable. 

: Delay 10ms which is to wait the PLL to stabilise. 

: Set the MCU to be in the PLL mode. 

Controlling Audio Processor 

Audio Processor Reset 

After the PLL is setup, the next step is to enable the audio processor by setting the 

CTRL2 [4] bit, which is the audio processor reset signal control bit. Use a 1 � 0 � 1 

sequence, which drives POR=0. Also do not set CTRL[4]= 1 when configuring the PLL. 

After a reset, it is necessary to wait for 200ms~300ms (fSYS_Audo=16MHz (Note) ) before 

sending the control command. This waiting perios is for the audio processor internal 

initialisation, including RAM initialisation, ADC, DAC ...etc. Any SPI commands during 

this period will be invalid as shown below: 

5

Audio Processor Reset Flow 



: This is the audio processor reset bit. The correct reset sequence is 1 � 0 

� 1, with two nope instructions in between. 

: This is the audio processor initial time. Any SPI data transmitted during this 

period may be overwritten by the audio processor and become invalid , which may waste 

250ms~300ms. 

Audio Processor Turn on Timing 

Note: fSYS_Audo is audio processor fSYS. 

Audio processor Turn on Timing 

6

SPI Command 


The audio processor uses the SPI interface as the communication interface with two methods 

of communicating through the internal (SPICR [7] =1) SPI circuit or the external (SPICR [7] =0) 

pin-shared I/Os (the following unit will describe). The internal communication can control the 

practical circuit by using the control bit as the following table shows: 

SPI Control Register(SPICR) 

Bit 7 6 5 4 3 2 1 0 

SPICR IEMC - ERAM SPISS SPICK MOSI MISO SPIRQ 

POR 1 - 0 1 0 0 x x 

SPICK MOSI MISO SPISS SPIRQ 

SPICR[7]=1 SPICR[3] SPICR[2] SPICR[1] SPICR[4] SPICR[0] 

SPICR[7]=0 PC6 PC4 PA5 PC7 PC5 

SPI Control Signal Table 

One complete data transmission is 20 bits long, starting from MSB to the 20 th bit LSB. The 

data includes a 4-bit group command and a 16-bit data. The group is divided into two 

categories, I/O and CLI. Their maximum SPI pulse frequencies are 16MHz and 150kHz. 

When designing, it’s recommended that the frequency should be less than 150kHz that 

the SPI receive and transmit program can be shared. The I/O command is applied in 

some application areas, such as for circuit control, sharing data etc, marked as I/O 

CMD-NNh in this document. The CLI (Control layer interface) command can access the 

audio processor related parameters, such as the threshold parameters, modulation, 

advanced application control and so on. Its usage is different from the I/O group and 

requires three commands to write a command completely. Reading data requires two 

commands. These are marked as CLI CMD–NNNNh in this document. See the following 

for details: 

SPISS 

SPICK 

MOSI 

MISO 

SPIRQ 

C3 C2 C1 C0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 

C3 C2 C1 C0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 

HT98R068-1 SPI Communication Format 

7

SPI Application Example Program 


The source codes are attached in the HT98R068-1_AppInc.inc file where the SPI 

application section contains: 

� SPI command Macro = SPITX (macro) 

� SPI Write = Procedure_SPI_Tx (procedure) 

� SPI Read = Procedure_SPI_Rx (procedure) 

� I/O Command (C[3-0]:Write/Read=8xxxx/9xxxx) 

The [19-16] bits are setting differs for reading and writing. Set to “8(Dec)” for a write 

command and “9(Dec)” for a read command. The audio processor will not reply with any 

information during data writing. D7-D0 will be in a “Don’t Care” condition during a read 

command execution. A7~A0 are the register addresses. D7~D0 are the access datas. 

Write I/O CMD: 

Master write: 

SPI[19:16] SPI[15:8] SPI[7:0] 

4’b1000 Address(A7~A0) Data(D7~D0) 

Audio processor reply: 

SPI[19:16] SPI[15:8] SPI[7:0] 

x (No signal) x (No signal) x (No signal) 

Read I/O CMD: 

Master Write: 

SPI[19:16] SPI[15:8] SPI[7:0] 

4’b1001 Address(A7~A0) x (Don’t care) 

Audio processor reply: 

SPI[19:16] SPI[15:8] SPI[7:0] 

4’b1001 Address(A7~A0) Data(D7~D0) 

Ex: Write C3h to the I/O register “1Eh” and then read this register to confirm if it is 

correctly written. 

� Write 1Eh Flow 


: Enable the DAC2, DAC1, AMP2, AMP1, Buffer, MIC and PGA circuits. 

There will be no data response after the command is transmitted. 

8

� Read 1Eh Flow 



: Read the 1Eh register. A data response will be sent to 1Eh after this 

command is transmitted. 

CLI Command 

This interface protocol is different from the I/O command. For the write mode it must 

contain three bytes of 20-bit SPI data and two for the read mode. To excute the CLI 

command, the first byte is ID code, then the 16-bit address and finally the 16-bit data. 

Reading data will have no data byte. The ID code of the read/write mode is different. 

IDcode >> Read/Write: 14181/14082, must be correct so that the audio processor will 

continue to receive successive data. When the data is written, the audio processor will 

reply with 14000 which means that the data is correctly written, otherwise it means no 

data written. 

� Write CLI CMD 

� Master Write 

CLI_CMD Major Minor Multi Length 

4’b0001 4’b0100 4’b0000 4’b1000 4’b0010 

4’b0001 Address[15:0] 

4’b0001 Data[15:0] 

� Audio processor reply 


4’b0001 4’b0100 4’b0000 4’b0000 4’b0000 

� Read CLI CMD 

� Master Write 


4’b0001 4’b0100 4’b0001 4’b1000 4’b0001 

4’b0001 Address[15:0] 

� Audio processor reply 


4’b0001 4’b0100 4’b0001 4’b1000 4’b0001 

4’b0001 Data[15:0] 

9


Ex: Write FFFFh (with MOD and SMOD outputs at the maximum modulation) to the CLI 

register "04CBh" and then read this register. 

� Write 04CBh Flow 


: The CLI writeS ID code. To execute a write operation with the CLI Command, 

it is necessary to execute this command first. No data response will be provided. 

: Select the 04CB register. Set as a write register. No data response will be 

provided. 

: Set the data: FFFFh. Write data to the register. A data response of 14000 

means that it is correctly written, otherwise it means that no data has been correctly 

written. 

� Read 04CBh Flow: 


: The CLI read ID code. To execute a read operation with the CLI command, 


: Select the 04CB register. Set the read register. After the command, it will 

reply with 14181 firstly, then responses the read data 1FFFFh (the 04CBh data is 

FFFFh). There are two bytes of data in all. 

10

External Control 


For different audio processing control requirements, in addition to the internal MCU 

connections, external SPI control is also supported. However, before using the external 

control, some relevant initialisation must be executed which includes the PLL, reset and 

SPI path. After the PLL is setup and the audio processor is reset (the flow is the same 

with the previous unit), set SPICR [7] (IEMC) =0 to switch the SPI path to be an external 

pin-shared port so that the external SPI command can be excuted. The five occupied I/O 

ports cannot be applied for other functions at this time. 

SPICK MOSI MISO SPISS SPIRQ 

SPICR[7]=1 SPICR[3] SPICR[2] SPICR[1] SPICR[4] SPICR[0] 

SPICR[7]=0 PC6 PC4 PA5 PC7 PC5 

SPI Control Signal Table 

Points to note when using external control 

� when required to reduce the PLL frequency or entering the sleep mode 

� when the SPI is returned to the internal MCU control 

� Usable pins decrease 

When 1 or 2 problems of those described above occurs, it’s recommended that use 

master slave control signal in the SPI external control unit and internal MCU or establish 

a control protocol, for the objective of internal register control for frequency adjustment or 

audio processor control.This will reduce the loading on the master MCU (external MCU) 

for calculations and flow control. See the following for description: 

External MCU Connection Diagram 

11

� Use External Control Flow 



: Enable and set the PLL. 

: Reset the audio processor. 

: Check the control signal status and select the SPI path to be 

external or internal. 

: Excute the MCU SPI external/internal control bit configuration. 

: Excute the external/internal MCU system flow. 

IDLE/SLOW/TX/RX Mode Select Setting 

When applied in a radio walkie talkie application, the ON/OFF circuit and function for 

different modes are different, as well as the ON/OFF timing. Switch to the correct input or 

output source and disable any unnecessary circuits so as to save power and eliminate 

interference among signals (Note that turning on the circuit needs a stable time 

(according to the circuit, it is usually about 250ms) except that the system enters the 

sleep mode to wait). This control is designed in the I/O command group.This part is in the 

I/O command making signal control easier and empty the unnecessary processing 

resources.The following describes the three mode setups (see SLOW Mode in VOX): 

12

IDLE M ode 


When the audio processor is not processing data, entering this mode can save power, 

however the quantity depends on the actual practical situation. The device provides many 

ways to enter the idle mode (see to the datasheet). Here we use the simplest method. 

The I/O CMD-51h can control the audio processor operation-stop/operate: FAh/F8h. Note 

that it must be separated into two parts of commands. Stop the audio processor by using 

an F8h � FAh � DAh sequence while operating by using DAh � FAh � F8h. Disable 

the audio processor clock when no event is happening, then use the MCU to detect the 

external signals, and enable the audio processor after the signal is identified as shown 

below. 

� IDLE Mode Setup Flow 


When there is no output or input signal are waiting to be processed, the audio 

processor can be disabled. After it’s enabled, operating can be restarted without 

needing re-initialise. 

: Enable the audio circuit power supply or select to enable the needed circuit 

only. 

: Enable the audio processor pulse frequency first stage switch. 

: Enable the audio processor pulse frequency second stage switch. 

// 

: Disable the audio circuit power supply to lower or turn down unnecessary 

power consumption. 

: Set the input/output line input/output path as common-mode bias voltage to 

reduce misunderstanding and reset the receive status. 

: Disable the audio processor pulse frequency first stage switch. 

: Disable the audio processor pulse frequency second stage switch. 

13

TX Mode 


Entering the TX mode depens on the input data trigger, such as pressing PTT, audio 

signal (VOX)…etc.The mode switches, input source selection, circuit disabling etc will be 

generally executed in this mode. As for the audio buffer input source, it is recommended 

to switch to bias voltage to reduce noise, or disable the buffer (I/O CMD-1Eh [3]), or even 

choose both. During TX/RX switching, it is recommended to execute circuit ON/OFF � 

path select � mode switch so as to decrease the generation of error signals. The 

following illustrates the PTT processing: 

Ex: Setup the TX mode, Input = MIC, Output = MOD, No Sub-tone. 

� Tx Mode Setup Flow 


: Enable the DDAC1, AMP1, MIC and PGA circuits. Setup the circuit switch 

first. DAC1, AMP1 on-enable the MOD output. MIC on-enable the microphone circuit, 

PGA on- enable the PGA input source. 

: Select the input PGA and audio input source paths. Select the PGA input 

source to be MIC and the audio output to be DAC common-mode bias voltage to 

reduce noise. 

: Enter the TX mode. Select the TX mode as the final step to enter the TX 

processing flow. 

14

RX Mode 


This mode is mainly applied for in-band signal demodulation. Although it is acceptable to 

wait for the RF signal in this mode, it is recommended that the MCU should verify the 

RSSI (Receive signal strength indicator) signal before switching the input source to the 

DEMOD path and then enable the audio processor for management. In this way, power 

can be saved and in the meantime avoid erroneous signal judgments. The modes 

switching, paths selection, circuit ON/OFF and the SPI command settings are as follows: 

Ex: RX mode, Input = DEMOD, Output = AUDO (source = DAC1), No Sub-tone. 

� RX Mode Setup Flow 


: Confirm if the RF signal is OK. 

: Enable the DAC1, buffer and PGA circuits. Setup the circuit switches first. 

DAC1 on-enable DAC1 output, AUDO output buffer on- enable the audio output circuit, 

PGA on- enable the PGA input source. 

: Select the PGA and audio input source paths. Select the PGA input source 

to be DEMOD, the audio output to be DAC1 and then switch the DAC1 pin source path 

to the internal common-mode bias voltage in order to prevent the audio leaking from 

MOD. 

: Enter the RX mode. Select the RX mode as the final step to enter the RX 

processing flow. 

15

Audio Processor IRQ 


When an audio process event occurs, the audio processor will use this signal as an 

interrupt request, during which time the master should send a SPI signal to read the 

20-bit data, transmitting 100h as the first 12 bits data with the last data corresponding to 

the I/O CMD-23h, the last byte data bit will generate an interrupt if there is a status 

changing event (0 � 1 or 1 � 0). Hence, read the I/O CMD-23h command again to 

acknowledge the event is OK or end. The I/O CMD-22h is the interrupt mask selection, 

and is used as an interrupt request. The main interrupt source must be enabled (I/O 

CMD-22h [6] =1). This application does not need to use a polling method. Managing after 

the interrupt generation makes the MCU more efficient. The format description is as 

follows: 

Event Interrupt Mask - 22h Address 

Bit 7 6 5 4 3 2 1 0 

Name — IRQ 

DTMF 

INT 

Selective 

call INT 

CTCSS 

INT 

DCS 

INT 

Audio Processor IRQ Event Masking Control Register 

Off_Tone 

INT 

Event VOX DCS CTCSS SelCal_Tone DTMF Off_Tone 

IRQ SPI Data 10001h 10004h 10008h 10010h 10020h 10002h 

Polling I/O 

Command 23h 

01h 04h 08h 10h 20h 02h 

Polling I/O 

Command 30h 

— — 01h — — — 

IRQ & Polling Comparision Table (when generating an active signal) 

Ex: Detect the CTCSS tone. 

� CTCSS Interrupt Flow 

Step 1: Enable CTCSS INT. 

16 

VOX 

INT

Step 2: Rx AUP ISR. 

Step 3: Rx 23h detection flow. 

Flow description (1): 


: Set the interrupt enabled selection. Select the CTCSS interrupt, enable the 

interrupt source. 


: Confirm this interrupt signal is CTCSS event. 

: Poll event status. 


: Confirm this interrupt signal is approved by CTCSS (92308) or 

don’t decode CTCSS (92300) correctly. 

17

Audio Processor Status Reset 


When decoding normally, the audio processor processes depending on the signal data 

code, frequency and amplitude. Its status (I/O CMD-23h, 30h) will change if the 

communication flow meets with that RF ok � signal ok � signal fail � RF fail. When the 

audio status changes by a sequence 0 � 1 � 0, it can decode again in the next 

communication setup. However, sometimes due to using of various combinations, there 

is no way to get the audio processor decoding again and it remains the false status. 

Hence, we need a mechanism to make it back to the decoding stage to decode again. 

There are two ways: 

� Reset using command (I/O CMD: 10000), but note that this command will make the 

original data wrote to the CLI automatically overwritten. 

� Reset basing on signal. Set the PGA source to be VAG and increase the de-response 

delay time to make the audio processor return to none decoding automatically, the 

status register will be changed to 0, then switched to the Rx mode to detect the signal 

again. But the disadvantage is that it must consum time to delay. 

The other situation is sub-audio tail-tone detection status, CTCSS anti-tone (I/O 

CMD-30h [0] =1) or DCS off-tone (I/O CMD-23h [1] =1). When decoding a CTCSS 

off-tone, the I/O CMD-30h[0]=1, this status will be remained(because it is belong to 

respective decode), so we must load I/O CMD: 12000 and make it reset sub-audio 

tail-tone decoding detection, set I/O CMD-30h[0]=0 or I/O CMD-23h[1]=0. Hence, take it 

to consider that at the moment decoding the tail-tone it excutes the command 

immediately when designing. 

Internal Audio Function 

In the open public radio system (such as aviation communication), when someone wants 

to select to call some users or resist to receive irrelevant information, the selective call 

function is always applicated in specifying the person to communicate with. When calling 

someone, the tranimitter will firstly transmit the specification information of 2 or 5 tones 

audio (selective call), then send the sound signal. Each receiver of the same frequency 

will receive this radio signal then decodes the data of 2 or 5 tones at the same time and 

compare them. If the decoded selective call code is the same with the receiver’s, the 

process end will open the speaker to make it heared to complete the communication 

information transmission of the ends. Besides, the signals such as DTMF are applied in 

keys triggle, can be used in transmitting the data input by the user to the other end to 

decode or application of the same selective call use. This product provides two audio 

selection, selective call and DTMF, which include transmit encoder and receive decoder 

as the following shows. 

18

Selective Call Setting 

19 


It’s a sine wave frequency anolog signal, has 16 groups of signals. It meets with the 

standard international specification (EIA, EEA, CCIR, ZVEI 1, ZVEI 2…etc), also, the 

user can define the frequency channel to applicate flexibly. It can be achieved from 

300Hz to 3000Hz. Set this function by using I/O CMD-11h [4-2] = b’010. Select the TX 

encode channel by using I/O CMD-2Ah [3-0]. Each channel data is separately stored in 

the two proximate CLI CMD registers. For example, the channel 0 data is located in CLI 

CMD-04E0 and 04E1. It can generate required frequency by application program. In the 

Rx mode, the process unit will detect the incoming signal frequency and compare the 

datas in the channel list (CLI CMD-04E0~04FF). If the comparision is successful, locate 

the decoding frequency channel number in I/O CMD-2Eh [3-0] and set the status bit I/O 

CMD-23h [4]. In addition, note that the threshold setting when decoding, the generally 

accepted threshold is CLI CMD-0324 and the published threshold is CLI CMD-0325. 

They respectively control the decoding low value and the non-decoding high value which 

are described as the following. 

Ex: TX mode, Output = MOD, Selective call tone = 00h. 

� Set the Selective Call TX Mode Flow 


: Select selective call channel. Select zeroth group frenquency channel (default 

EEA: 1981Hz). 

: Enable DAC1 and AMP1 circuit. DAC1, AMP1 on- enable MOD output. 

: Select input PGA and audio input source paths. Select PGA input source as 

VAG, the audio output as DAC common-mode bias voltage to reduce noise. The DAO1 

input source is DAC1. 

: Enter the TX mode. Select the TX mode and turn on the in-band audio = 

selective call function.

Ex: RX mode, Input = DEMOD, Output =null, Non sub-tone. 

� Set Selective Call RX Mode Flow 



: Acknowledge the RF signal is OK. 

: Enable the PGA circuit, PGA on – enable the input source PGA. 

: Select input PGA and audio input source paths. Select the PGA input source 

as DEMOD, the audio output as DAC common-mode bias voltage to reduce noise. DAO1 

and DAO2 are DAC common-mode bias voltage. 

: Enter Rx mode. Select RX mode and enable in-band audio = selective call 

function. 

: Acknowledge that the signal a steady frenquency in the selective 

call frequency channel list. 

: Read the selective call detection data. Read the frenquency channel of this 

selective call detection data. 

: Store the number after detection. Store this number data 

temporarily. After finishing the complete byte data receiving, use it to the application. 

: Enter the IDLE mode. Before the RSSI signal is ok, enter the waiting 

mode firstly. 

20

DTMF Setting 


DTMF is a dual tone multiple frequency anolog signal, which includes high frequency 

tone and low frequency tone. There are 16 groups signals (0~D), common in telephone 

system dialing or keypad tone. Set I/O CMD-11h [4-2] = b’100. Select the TX encode 

channel by using the I/O CMD-2Dh [3-0] bits and select the frequencies in the list. In the 

Rx mode, the process unit will detect the incoming signal and compare the 16 groups of 

frequencies. If the comparision is successful, locate the decoding frequency channel 

number in the I/O CMD-2Fh [3-0] and set the status bit I/O CMD-23h [5]. In addition, there 

is a power threshold (CLI CMD-01C4). It selects the minimum amplitude one of the two 

frequencies as the measurement standard, which is described in the following note. 

Ex: RX mode, Input = MOD, DTMF tone= 00h. 

� Set DTMF TX Mode Flow 


: Select DTMF channel. Select DTMF zeroth group frenquency channel. 

: Enable DAC1 and AMP1 circuit. DAC1, AMP1 on- enable MOD output. 

: Select input PGA and audio input source paths. Select PGA input source to be 

VAG, the audio output to be DAC common-mode bias voltage to reduce noise. The DAO1 

input source is DAC1. 

: Enter the Tx mode. Select the TX mode and enable the in-band audio = DTMF 

function. 

21

Ex: RX mode, Input = DEMOD, Output = null, Non sub-tone. 

� Set the DTMF RX Mode Flow 



: Acknowledge the RF signal is OK. 

: Enable the PGA circuit, PGA on – enable the input source PGA. 

: Select input PGA and audio input source path. Select the PGA input source to 

be DEMOD, the audio output to be DAC common-mode bias voltage to reduce noise. 

DAO1 and DAO2 are DAC common-mode bias voltage. 

: Enter the TX mode. Select the TX mode and enable the in-band audio = DTMF 

function 

: Acknowledge that the signal a steady frenquency in the DTM 

frequency channel list. 

: Read the DTMF detection data. Read the frenquency channel of this DTMF 

detection data. 

: Store the number after detection. Store this number data 

temporarily. After finishing the complete byte data receiving, use it to the application. 

Mode>: Enter the IDLE mode. Before the RSSI signal is ok, enter the 

waiting mode firstly. 

22

Sub-tone Function 


For the open systems such as walkie-talkies, under conditions of limited frequency 

channels, a sub-tone method can be applied to increase the same frequency channel 

numbers and to receive the required signals. Users at the receiving port should select the 

correct sub-tone type and channel so as to decode the data properly and reduce 

unnecessary signals. This will help to reduce the problems of mutual interference and 

frequency bands. The device provides two main sub-tone options described as follows. 

CTCSS Setting 

This produces analog signals of sinusoidal frequency from 62.5Hz~254.1Hz and contains 

51 groups of standard channel selections which meet the relevant specifications. An 

additional user-defined channel is provided to increase the flexibility of data protection. 

The channel is selected by using I/O CMD-2Bh sharing with DCS. For the audio 

processor, there are still two registers in which data changes should be noted when being 

used. In the Rx mode, it is acceptable to use polling (I/O CMD-23h [3]) or interrupt (10008 

I/O CMD-23h [3]) methods to detect whether it is the same as the setup channel. The 

table below provides relevant table and design descriptions. 

Tone CTCSS Tone CTCSS Tone CTCSS 

number freq.(Hz) number freq.(Hz) number freq.(Hz) 

01h 67 12h 123 23h 225.7 

02h 71.9 13h 127.3 24h 233.6 

03h 74.4 14h 131.8 25h 241.8 

04h 77 15h 136.5 26h 250.3 

05h 79.7 16h 141.3 27h 69.3 

06h 82.5 17h 146.2 28h 62.5 

07h 85.4 18h 151.4 29h 159.8 

08h 88.5 19h 156.7 2Ah 165.5 

09h 91.5 1Ah 162.2 2Bh 171.3 

0Ah 94.8 1Bh 167.9 2Ch 177.3 

0Bh 97.4 1Ch 173.8 2Dh 183.5 

0Ch 100 1Dh 179.9 2Eh 189.9 

0Dh 103.5 1Eh 186.2 2Fh 196.6 

0Eh 107.2 1Fh 192.8 30h 199.5 

0Fh 110.9 20h 203.5 31h 206.5 

10h 114.8 21h 210.7 32h 229.1 

11h 118.8 22h 218.1 33h 254.1 

CTCSS Frequency and Tone Numbers Table 

The device supports coded mark inversion designing of 180° and 120°. The Tx mode is 

controlled by the I/O CMD-31h [0] bit. It will generate a reversion signal by 1 � 0 or 0 � 1. 

The Rx mode detection is selected by the I/O CMD-31h [1] bit. If detecting a phase 

chaing, the I/O CMD-30h [0] bit will change to 1{note: this bit must clear to 0 automatically 

(see the Audio Processor Status Reset section)}. And the interrupt SPI data is sharing 

with (it is 10008h too). Hence, when using the CTCSS anti-tone detection function, you 

must check the I/O CMD-23h [3] and I/O CMD-30h [0] bits. The table below provides 

relevant table and design descriptions. 

23

Event 2 Control - 31h Address 


Bit 7 6 5 4 3 2 1 0 

Name — — — — — — 

Event 2 Status - 30h Address 

Event 2 Control Register 

En_CTC 

Rx_Anti-tone 

Bit 7 6 5 4 3 2 1 0 

Name — — — — — — — 

Event 2 Status Register 

En_CTC 

Tx_Anti-tone 

CTC Anti- 

Tone Event 

Ex: TX mode, Input = MIC, Output = MOD & SMOD, Sub-tone = CTCSS, CTCSS tone 

=01h. 

� CTCSS Tx Mode Setup Flow 


: Setup the sub-tone channel by selecting the first group of the CTCSS channel. 

: Enable the DAC1, DAC2, AMP1, AMP2, MIC and PGA circuits. DAC1, AMP1 

on- enable the MOD output. DAC2, AMP2 on- enable the SMOD output, MIC on–enable 

the microphone circuit. PGA on–enable the PGA input source. 

: Select the PGA and audio input source locations. Select the PGA input source 

to be MIC and audio out to be DAC common-mode bias to reduce noise. 

: Enter the TX mode. Select the TX mode and enable the Sub-tone = CTCSS 

function. 

24


Ex: RX mode, Input = DEMOD, Output = AUDO (sources = DAC1), Sub-tone = CTCSS, 

CTCSS tone = 01h 

� CTCSS RX Mode Setup Flow 


: Confirm the RF signal is OK. 

: Enable the PGA circuit. PGA on and enable the PGA input source. 

: Select the PGA and audio input source path. Select the PGA input source to be 

DEMOD with audio out to be DAC common-mode bias to reduce noise. 

: Enter the RX mode. Select the RX mode and enable the Sub-tone = CTCSS 

function. 

: To be confirmed that the signal has the CTCSS sub-tone of the same 

channel. 

: Enable the DAC1, buffer and PGA circuits. DAC1 on and enable the DAC1 

output. AUDO output buffer on and enable the audio output circuit. PGA on and enable 

the PGA input source. 

: Select the PGA and audio input source paths. Select the PGA input source to 

be DEMOD, audio out sources to be DAC1 and switch the DAC1 pin source paths to the 

internal common-mode bias voltage in order to prevent the audio leaking from MOD. 

25

DCS Setting 


DCS is a data waveform formed by a digital carrier signals using “0” and “1” data. The 

23-bit data signal includes the checksum and data codes. It provides a choice of 83x2 

(reverse codes included) standard channels and one user-defined channel. Set this 

function by using I/O CMD-11h[1-0] = b’01. The TX encode channel is selected by I/O 

CMD-2B h [6-0] (sharing with CTCSS). The encoding data is located in CLI CMD-04DC 

(DCS code bit0~bit15) and CLI CMD-04DD (DCS code bit16~bit22). When the 

communication is to be end, it will transmit an end signal (usually about 200ms~300ms), 

which is set by the channel selecting I/O CMD-82B [3-0] = h’7F. User can set CLI 

CMD-04DC, CLI CMD-04DD and set I/O CMD-2Bh [6-0] = h’00 to encode. But two points 

must be noted that the data can be recovered and it is transmitted starting from MSB. For 

example, set the DCS code to be 1BF1C8h, but it’s observed for 763813h by the 

waveform (right to left). 

� 1BF1C8h = 001, 1011, 1111, 0001, 1100, 1000 

� After resevering= 110, 0100, 0000, 1110, 0011, 0111 

� Oscilloscope observation(left to right,read from LSB) = (first) 1110, 1100, 0111, 0000, 

0010, 011 

7 6 3 8 1 3 

In the RX mode, detecting the incoming DCS code depends on the I/O CMD-2Bh 

pre-defined value. When detecting a correct code, the DCS event will sense that by 

polling (I/O CMD-23h [2]) or the interrupt (10004 � I/O CMD-23h [2]) with the DCS 

turn-off tone (I/O CMD-23h [1]) event checking it up which can indicate the end of DCS 

information (some systems provide this function to disable the audio output). The related 

configuration is shown in the table below: 

Tone DCS Tone DCS Tone DCS Tone DCS Code Tone DCS Code Tone DCS Code 

Number Code Number Code Number Code Number Inverted Number Inverted Number Inverted 

01h 023 1Dh 174 39h 445 81h 023 9Dh 174 B9h 445 

02h 025 1Eh 205 3Ah 464 82h 025 9Eh 205 BAh 464 

03h 026 1Fh 223 3Bh 465 83h 026 9Fh 223 BBh 465 

04h 031 20h 226 3Ch 466 84h 031 A0h 226 BCh 466 

05h 032 21h 243 3Dh 503 85h 032 A1h 243 BDh 503 

06h 043 22h 244 3Eh 506 86h 043 A2h 244 BEh 506 

07h 047 23h 245 3Fh 516 87h 047 A3h 245 BFh 516 

08h 051 24h 251 40h 532 88h 051 A4h 251 C0h 532 

09h 054 25h 261 41h 546 89h 054 A5h 261 C1h 546 

0Ah 065 26h 263 42h 565 8Ah 065 A6h 263 C2h 565 

0Bh 071 27h 265 43h 606 8Bh 071 A7h 265 C3h 606 

0Ch 072 28h 271 44h 612 8Ch 072 A8h 271 C4h 612 

0Dh 073 29h 306 45h 624 8Dh 073 A9h 306 C5h 624 

0Eh 074 2Ah 311 46h 627 8Eh 074 AAh 311 C6h 627 

0Fh 114 2Bh 315 47h 631 8Fh 114 ABh 315 C7h 631 

10h 115 2Ch 331 48h 632 90h 115 ACh 331 C8h 632 

11h 116 2Dh 343 49h 654 91h 116 ADh 343 C9h 654 

12h 125 2Eh 346 4Ah 662 92h 125 AEh 346 CAh 662 

13h 131 2Fh 351 4Bh 664 93h 131 AFh 351 CBh 664 

14h 132 30h 364 4Ch 703 94h 132 B0h 364 CCh 703 

15h 134 31h 365 4Dh 712 95h 134 B1h 365 CDh 712 

16h 143 32h 371 4Eh 723 96h 143 B2h 371 CEh 723 

17h 152 33h 411 4Fh 731 97h 152 B3h 411 CFh 731 

18h 155 34h 412 50h 732 98h 155 B4h 412 D0h 732 

19h 156 35h 413 51h 734 99h 156 B5h 413 D1h 734 

1Ah 162 36h 423 52h 743 9Ah 162 B6h 423 D2h 743 

1Bh 165 37h 431 53h 754 9Bh 165 B7h 431 D3h 754 

1Ch 172 38h 432 9Ch 172 B8h 432 

DCS Code and Tone Numbers Table 

26


Ex: TX mode, Input = AUX, Output = MOD & SMOD, Sub-tone = DCS, DCS tone = 01h 

� DCS TX Mode Setup Flow 

(1)Tx DCS Signal 

(2) Transmit an off_tone signal at the end of the signal 


: Setup the sub-tone channel by selecting the first DCS channel group. 

: Enable the DAC1, DAC2, AMP1, AMP2 and PGA circuits. DAC1、AMP1 

on-enable the MOD output. DAC2、AMP2 on- enable the SMOD output. PGA on–enable 

the PGA input source. 


be AUX with the audio out to be DAC common-mode bias voltage to reduce noise. 

: Enter the TX mode. Select the TX mode and enable the sub-tone = DCS 

function. 

27


* * * After the DCS signal is transmitted * * * 


: Select the OFF-tone to produce 134Hz signals. 

: Return to the idle mode. Complete the DCS and return to the standby status. 

Ex: RX mode, No audio tone signal, DCS sub-tone, AUDO sources = DAC1, DAC2 off, 

MIC off, DCS tone = 01h. All are implemented using interrupts (IRQs) in this example. 

When a DCS event interrupt is received, add an additional command to read the I/O 

CMD-23h for event status judgment: 

� DCS RX Mode Setup Flow 

(1) RF Signal Detection 

(2) Audio Processor IRQ Management 

28

(3) Enable and output the Audio_out signal 



: Confirm the RF signal is OK. 

: Enable the PGA circuit, PGA on - enable the PGA input source. 

: Select the PGA and Audio input source paths. Select the PGA input source to 

be DEMOD and audio out to be DAC common-mode bias voltage to reduce noise. 

: Enter the RX mode. Select the RX mode and enable the Sub-tone = DCS 

function. 


: Confirm the interrupt is the DCS sub-tone signal of the same channel. 

: Check again the event status. Confirm the DCS status is 1 or 0. 


: To be confirmed that the signal contains a DCS sub-tone of same 

channel. 

: Enable the DAC1, Buffer, PGA circuits. DAC1 on - enable the DAC1 output, 

AUDO output buffer on–enable the audio output circuit. PGA on–enable the PGA input 

source. 


be DEMOD, audio out sources to be DAC1 and switch the DAC1 pin source path to the 

internal common-mode bias voltage in order to prevent the audio leaking from MOD. 

29

Audio Advanced Function 


The device provides multiple audio processors, including scrambler, compandor, 

emphasis, HPF, LPF…etc. for a wide range of applications. The function switches are 

located in I/O CMD-2Ch [7-2]. As the audio processor operating frequencies are different, 

there are some restrictions in enabling the function groups and for using the TX/RX. See 

the appendix for reference: 

Audio Control - 2Ch Address 

Bit 7 6 5 4 3 2 1 0 

Name EN_Scram EN_Comp EN_Emp EN_NBW EN_WBW EN_HPF300 EN_VOX EN_AGC 

Advanced Audio Process Control Register 

Audio – Low Pass Filter/High Pass Filter Function Set 

In a communication system, signal interference and noise from adjacent channels will 

destroy the data to be transmitted or received. Suitable filtering can improve this problem. 

The device provides a 3.0kHz broad band and a 2.55kHz narrow band for a low pass filter 

as well as a 300Hz high pass filter to filte the sub-tones and signals outside the channel. 

The control bit I/O CMD-2Ch [4-2] is setup as follows. 

� 12.5k LPF & 300 HPF Enable Flow 


: Setup data: 14h. 2Ch [4] = 1 enables 12.5k LPF. 2Ch [2] = 1 enables 300Hz 

HPF. 

30


Audio – Pre-emphasis/de-emphasis Funtction Set 

The Emphasis function is used to modulate the high/low frequencies of the power 

spectrum so as to obtain a more average power spectrum density and a better S/N ratio. 

The high frequency power spectrum of a typical signal tends to reduce while noise will 

increase rapidly as the frequency rises. This is quite opposite to the signals and will 

cause a bad S/N ratio, so emphasis will be used to improve this unbalanced situation. 

The control bit I/O CMD-2Ch [5] is setup as follows: 

� Emphasis Enabe Flow 


: Setup data: 220h. 2Ch [5] = 1 enables the Emphasis. 

31


Audio – Scrambler/De-scrambler Function Setting 

Scrambling implements reversion signal processing which is an encryption method for 

the transmitted signals. In the TX mode, signals transmitted through a scrambler will 

become meaningless and impossible to use. Likewise, when in the RX mode, after the 

descrambler is used, the scrambled signals will be returned back to their original signals. 

The device provides eight reversion frequencies selection (CLI CMD-013A, 013B). 

Disable the scrambler before changing the frequency setting, and set the reversion 

frequency to be changed, enable the scrambler function to complete the frequency 

change. This function is controlled by the I/O CMD-2Ch [7] bit by using the following 

setup. 

� Scrambler Enable Flow 


: Setup data: 80h. 2Ch [7] = 1 enables the scrambler. 

32


� Change Scrambling Code Inversion Frequency (3200Hz) Flow 


: Setup data: 00h. 2Ch [7] = 0 disable the scrambler. 

: The CLI wrote ID code. To execute a write operation with the CLI Command, 


: Select the 013A register. Setup it as a write register. No data response will 

be provided. 

: Setup data: 9873h. Write data to the register. A data response of 14000 

means that it is correctly written; otherwise it means that no data has been correctly 

written. 

: The CLI wrote ID code. To execute a write operation with the CLI Command, 


: Select the 013B register. Setup it as a write register. No data response will 

be provided. 

: Setup data: 4B3Eh. Write data to the register. A data response of 14000 

means that it is correctly written; otherwise it means that no data has been correctly 

written. 

: Setup data: 80h. 2Ch [7] = 1 enable the srambler. 

33

Audio – Compandor Function Setting 


Companding is applied to lower the dynamic range by compressing or expanding the 

signals. Dynamic range: 60dB, output 30dB, value = 0.5 (subject: MIC in). In a radio 

transmission process, the RF signals will include noise after reception. Therefore, before 

the signals are transmitted, the data is compressed by a certain setup ratio. When the 

original signals are retrieved by the descrambler expanded with the same ratio, most of 

RF noise that does not belong to the original signals will be eliminated after the expansion 

and will thus greatly reduce the noise in the output. Set the companding amplitude turning 

point by CLI CMD-012A in the TX mode and CLI CMD-012B in the RX mode. It’s 

important to note that the TX/RX setting value is different in the same turning point. For 

example, in the turning point of 100mV, the 1V signal in the TX mode will be measured to 

be 550mV by MOD but in the Rx mode it is 1900mV. Note that if the signal exceeds the 

limiter by companding. Control for this is setup using the I/O CMD-2Ch [6] bit as follows: 

� Compandor Function Enable Flow 


: Setup data: 40h. 2Ch [6] = 1 enables the compandor. 

34

In-band Signal Level Adjustment Function 


The output modulation differs between different system applications. The device provides 

multi-level modulating settings for different paths and also provides a mixer. The 

modulation diagram and description are as follows: 

Modulation Path Block Diagram 

� VR1: The internal audio generator modulation level select (I/O CMD-11h [4-2: b’010]), 

256 levels. Default: 00h. 

� VR2: Sub-tone modulation level select, 256 levels. Defaul: 00h. 

� VR3: Mixer modulation option/setting. When VR3=0, it means no MIX function, 256 

levels. Default: 00h. 

� VR4: The MOD (pin) in-band output modulation select, 1024 levels. Default: 3FFh. 

� VR5: The SMOD (pin) sub-tone output modulation select, 1024 levels. Default: 3FFh. 

The MOD output depends on the VR1 setting (if a tone generator is used), VR4 and the 

system operating voltages. The SMOD output depends on VR2, VR5 and the system 

operating voltages. However, there may be some distortion in the actual output (RC 

filter etc.). For example, in a 3V system, MOD Output (max) ~= 2780mv, SMOD Output 

(max) ~= 1920mv due to the default value of the audio processor. Users must enable or 

change the path modulation level for their application. 

In the high frequency modulation mechanism TX mode, CTCSS and DCS always 

seperate the signals to access so that the digital signal of the DCS high and low fast 

changing can be processed efficiently. The device ouput by using the same SMOD pin, so 

the mixer mechanism is designed specially for output the DCS to be modulated by the 

MOD signal. The generic method is that the CTCSS sub-audio is output by SMOD and 

VR3 is disabled (CLI CMD-04D2h=0000h). The CTCSS signal is determined by VR2 and 

VR5. However, the DCS signal is output by MOD mixed with the audio signal. VR3 is 

enabled and has a numerical value to scale while VR5 is diabled (CLI CMD-04D5=0000h) 

or it’s OK to disable the DAC2 output. At this time, the DCS is determined by VR2 and 

VR3. All are aiming at taking advantages of the TX DCS function. Note that: Whether the 

system can applicate in this way or not is depending on the actual condition. 

Ex: Operating voltage = 3V, setup and enable the maximum modulation of the sub-audio 

path, VR5 = default (3FFh): 

35

� Sub-audio Path Modulating Flow 



: The CLI wrote ID code. 

: Select the register: 04CB 

: Setup data: 00FFh. VR2 = FFh enables the maximum VR2 level. 

: The audio processor writes an acknowledge reply. 

36

Voice Control Function -- VOX 


The VOX function is often applied in some special applications. From the VOX high level 

threshold (CLI CMD-04CD) and low level threshold (CLI CMD-04CE) which are related to 

the MIC voice volume, the input source can be determined whether it is above the 

threshold (I/O CMD-29[1-0]=02h) or below the threshold (I/O CMD-29[1-0]=01h). The 

control bit is I/O CMD-2Ch [1]. 


Bit 7 6 5 4 3 2 1 0 

Name EN_Scram EN_Comp EN_Emp EN_NBW EN_WBW EN_HPF300 EN_VOX EN_AGC 

VOX Selection Register 

VOX Detection Status Chart 

In this mode, setup the slow mode, then lower the audio processor operating frequency 

(16MHz 4MHz) and disable any unused circuits (output related components) to meet the 

minimum power consumption (16mA - 10mA @3.3V). When the signal is acknowledged, 

enter the TX mode to continue with signal transmission. The control flow is shown below: 

� VOX Enable Flow 

(1) VOX and Slow Mode Setting 

37

(2) VOX Signal Status Detection 



: Enable the MIC and PGA circuits. MIC on–enable the microphone circuit, PGA 

on–enable the PGA input source. 

: Select the PGA and Audio input source paths. Select the PGA input source to 

be MIC and the audio out to be DAC common-mode bias voltage to reduce the noise. 

: Setup to slow mode. 

& : Set the audio processor to the lowest 

frequency - 4MHz. 

: Setup data: 02h. 2Ch [1] = 1 enable the VOX function. 


: To be confirmed it is a VOX event. 

: The VOX high/low threshold status. Read the VOX threshold status. 29h [1-0] = 

b’10, above the high threshold = a VOX event. 29h [1-0] = b’01, below the low threshold = 

end a VOX event. 

: Go back to the slow mode and wait. 

& : Set the audio processor to the maximum 

frequency - 16MHz (assumed to be the original setup value.) 

: Enter the Tx control flow. 

38

Auto Gain Control -- AGC 


The audio input magnitude to microphones usually varies influencing the quality of the 

audio output. This problem is usually resolved by the addition of an AGC circuit which 

requires less circuit space but incurs a cost increase. This device includes an internal 

AGC function which can fully implement an automatic gain control mechanism when 

accompanied with its internal microphone amplifier (with a fixed gain of 5) and digital 

control. The range is selected by using the control bit I/O CMD-2Ch [0]. 


Bit 7 6 5 4 3 2 1 0 

Name EN_Scra 

m 

� AGC Enable Flow 

EN_Comp EN_Emp EN_NBW EN_WBW EN_HPF300 EN_VOX EN_AG 

C 

AGC Selection Register 


: Setup data: 01h. 2Ch [0] = 1 enable the AGC function. 

Ex: With 3.3V voltage, try to select OPA ratio (standard MIC=16rms) 

Sol: 

� Step 1: The maximum AD range: 3.3 * 0.7 = 2310mV 

� Step2: Input source: 16rms * (2/√2) = 45.3mV 

� Step3: Specification→ 2310 ≧ 45.3 * 8 * C (8 = PGA max ratio, C = Amplification ratio) 

→ C = 6.37 

� Step4: Carry out the OPA resistance: R2 / R1 = 6.37 

→ if R1 = 10K → R2 = 62K. 

AGC Application Circuit @3.3V : 

39

Parameter Setting 


The audio processor frequency generation, threshold detection, variation values, drop 

time and limiting values can be modified according to actual requirements and generate 

the required setting parameters using the application program in the appendix: 

� Use the program HT98R068-1_AppProg_Vxx.exe to generate the required 

parameters. 

� For details, see the HT98R068-1_AppProgNote_Vxx.pdf. 

Tool Development Considerations 

� Use the development tool specifically for the HT98R068-1. Real ICE: MEV (Lot 

No.:M1001C) DEV (Lot No.: D1044A) or the update version). 

� To meet with the stabilish requirement, it’s recommended that be used by connecting 

with power externally to provide correct detection voltage (See e-ICE manual). 

� Some modifications should be made to the ICE circuit by adding a PLL Clock Sources 

(32.768 rystal) and a filter (PLLC Circuit). Check the figure below (Please note the pin 

name and the circuit. The pin name is the ICE defined pin.): 

ICE Gain Circuit: 

40

Real 

Chip 

Pin 

Real Chip 

Pin Name 

ICE pin assignment of the 64LQFP real chip: 

J5 J5 

Real Chip 

Pin Name 

Real 

Chip Pin 

Real 

Chip 

Pin 


Real Chip 

Pin Name 

J6 J6 

Real Chip 

Pin Name 

VSS 46 45 VSS VSS 46 45 VSS 

Real Chip 

Pin 

37 PA2 44 43 PA3 38 39 PC0 44 43 PC1 40 

35 PA0 42 41 PA1 36 41 PC2 42 41 PC3 42 

33 PB6 40 39 PB7 34 43 PD4 40 39 PD5 44 

NC 38 37 NC 45 PD6 38 37 PD7 46 

NC 36 35 NC NC 36 35 NC 

NC 34 33 NC NC 34 33 PA7/RESB 50 

NC 32 31 NC 51 PA6 32 31 PA5 52 

NC 30 29 NC 53 PA4 30 29 PC4 54 

NC 28 27 NC 55 PC5 28 27 PC6 56 

NC 26 25 VDD 27/28/29 57 PC7 26 25 PD0 58 

24 XOUT 24 23 VSS 25/26 59 PD1 24 23 NC 

22 PLLC 22 21 XIN 23 NC 22 21 VSS 60/61 

20 PB4 20 19 PB5 21 NC 20 19 NC 

18 PD2 18 17 PD3 19 NC 18 17 NC 

16 PB2 16 15 PB3 17 63 MIC_O 16 15 MIC_I 64 

14 PB0 14 13 PB1 15 1 DEMOD 14 13 VAG 2 

NC 12 11 NC 3 VAGREF 12 11 VCCA1 4 

NC 10 9 NC 5 AUX 10 9 PE1 6 

NC 8 7 NC 7 PE0 8 7 SMOD 8 

NC 6 5 NC 9 MOD 6 5 AUDO 10 

NC 4 3 NC 11 VCCA2 4 3 VSS 12 

VDD 2 1 VDD VEXT 2 1 VEXT 

41

Real 

Chip 

Pin 

Real Chip 

Pin Name 

ICE pin assignment of the 48LQFP real chip: 

J5 J5 

Real Chip 

Pin Name 

Real 

Chip 

Pin 


Real 

Chip 

Pin 

Real 

Chip 

Pin Name 

J6 J6 

Real Chip 

Pin Name 

VSS 46 45 VSS VSS 46 45 VSS 

30 PA2 44 43 PA3 31 32 PC0 44 43 PC1 33 

28 PA0 42 41 PA1 29 34 PC2 42 41 PC3 35 

26 PB6 40 39 PB7 27 PD4 40 39 PD5 

NC 38 37 NC PD6 38 37 PD7 

NC 36 35 NC NC 36 35 NC 

NC 34 33 NC NC 34 33 PA7/RESB 36 

NC 32 31 NC 37 PA6 32 31 PA5 38 

NC 30 29 NC 39 PA4 30 29 PC4 40 

NC 28 27 NC 41 PC5 28 27 PC6 42 

NC 26 25 VDD 25 43 PC7 26 25 PD0 44 

23 XOUT 24 23 VSS 24 45 PD1 24 23 NC 

21 PLLC 22 21 XIN 22 NC 22 21 VSS 46 

19 PB4 20 19 PB5 20 NC 20 19 NC 

17 PD2 18 17 PD3 18 NC 18 17 NC 

15 PB2 16 15 PB3 16 47 MIC_O 16 15 MIC_I 48 

13 PB0 14 13 PB1 14 1 DEMOD 14 13 VAG 2 

NC 12 11 NC 3 VAGREF 12 11 VCCA1 4 

NC 10 9 NC 5 AUX 10 9 PE1 6 

NC 8 7 NC 7 PE0 8 7 SMOD 8 

NC 6 5 NC 9 MOD 6 5 AUDO 10 

NC 4 3 NC 11 VCCA2 4 3 VSS 12 

VDD 2 1 VDD VEXT 2 1 VEXT 

42 

Real 

Chip 

Pin

Appendix 


In the different functional groups, the audio processor system clock speed table. 

Sub-audio Audio Scrambler Compandor Emphasis LPF HPF fSYS_Audo 

None 

CTCSS 

DCS 

None 

DTMF 

Audio 

Band 

None 

DTMF 

None 

DTMF 

ˇ ˇ 8M 

ˇ ˇ ˇ 8M 

ˇ ˇ ˇ 12M 

ˇ ˇ ˇ ˇ 16M 

ˇ ˇ ˇ 12M 



ˇ ˇ ˇ ˇ ˇ 16M 

ˇ ˇ 12M 

ˇ ˇ ˇ 12M 

ˇ ˇ ˇ 12M 

ˇ ˇ 16M 

ˇ ˇ 12M 

ˇ ˇ ˇ 12M 

ˇ ˇ ˇ 12M 


ˇ ˇ ˇ 12M 




ˇ ˇ 16M 

ˇ ˇ ˇ 16M 

ˇ ˇ ˇ 16M 

ˇ ˇ 12M 

ˇ ˇ ˇ 12M 

ˇ ˇ ˇ 12M 


ˇ ˇ ˇ 12M 




ˇ ˇ 16M 

ˇ ˇ ˇ 16M 

ˇ ˇ ˇ 16M 

VOX 4M 

Rx Functional Combination Capability Table 

“fSYS_Audo”: Audio processor fSYS. 

43

44 


Sub-audio Audio Scrambler Compandor Emphasis LPF HPF Fsys_Audo 

None 

CTCSS 

DCS 

None 

DTMF / Audio 

Band tone 

None 

DTMF / Audio 

Band tone 

None 

DTMF / Audio 

Band tone 

ˇ ˇ 8M 

ˇ ˇ ˇ 8M 

ˇ ˇ ˇ 12M 


ˇ ˇ ˇ 12M 




ˇ ˇ 12M 

ˇ ˇ ˇ 12M 

ˇ ˇ ˇ 12M 


ˇ ˇ 12M 

ˇ ˇ ˇ 12M 

ˇ ˇ ˇ 16M 


ˇ ˇ ˇ 12M 




ˇ ˇ 16M 

ˇ ˇ ˇ 16M 

ˇ ˇ ˇ 16M 

ˇ ˇ 12M 

ˇ ˇ ˇ 12M 

ˇ ˇ ˇ 16M 


ˇ ˇ ˇ 12M 




Tx Functional Combination Capability Table 

ˇ ˇ 16M 

ˇ ˇ ˇ 16M 

ˇ ˇ ˇ 16M

Voice Control Function - Holtek Semiconductor Inc.

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