SOHA HASSOUN - Department of Computer Science - Tufts University

Department of Computer Science
Tufts University
Medford, MA 02155
SOHA HASSOUN
Curriculum Vitae
Tel. (617) 818-0591
Soha.Hassoun@tufts.edu OR soha@cs.tufts.edu
URL: http://www.cs.tufts.edu/~soha
Research Interests
Systems Biology: Modeling, analysis, and synthesis of Metabolic Pathways
Electronic Design Automation for novel technologies including: 3D integration, double-gate
devices, and carbon nanotubes
Education
University of Washington, Seattle, WA
Ph.D., Computer Science and Engineering, 1997
MIT, Cambridge, MA
M.S., Electrical Engineering, 1988
South Dakota State University, Brookings, SD
B.S., Electrical Engineering, 1986
Professional Experience
Associate Professor, Tufts University, May 2004 –
Assistant Professor, Tufts University, January 1998 –May 2004
Department of Computer Science & Department of Electrical and Computer Engineering
Patents
Consultant, Carbon Design Systems, Acton, MA January 2007-October 2008
Visiting Researcher, IBM Austin Research Labs, Austin, TX, January 2002-July 2002
Consultant, IKOS Systems (Now Mentor Graphics), Sept 1999-June 2001
Research Assistant, University of Washington, September, December 1997
Department of Computer Science and Engineering
Senior Design Engineer, Digital Equipment Corporation, August 1988-August 1991
Microprocessor Design Group
Research and Teaching Assistant, Massachusetts Institute of Technology, Cambridge, MA
Department of Electrical Engineering and Computer Science, September 1986 - May 1988
1. S. Hassoun and B. Swahn, "Circuit Having Hardware Threading", provisional filed in 2003.
2. C. Selvidge, K. Crouch, M. Kudlugi, and S. Hassoun, "Non-Synchronized Multiplex Data Transport
across Synchronous Systems", U.S. patent 6,961,691, November 1, 2005.
3. Alpert, C. and S. Hassoun, "Optimal Buffered Routing Path Constructions for Single and Multiple
Clock Domain Systems", U.S. Patent 6,915,361, July 5, 2005.
4. S. Hassoun and D. Sanders, "Method and Apparatus for Parity Generation", U.S. Patent 5557622,
September 17, 1996.

Journals
1. N. Khan, S. Hassoun, and D. Brooks, “A System-Level Study of Carbon Nanotubes for Power
Delivery in Single-Die and 3D Architectures”, under review, IEEE Transactions on Very Large
Scale Integration (VLSI) Systems.
2. Khan, S. Alam, and S. Hassoun, “Power Delivery Design for 3D ICs Using Different TSV
Technologies”, Accepted for publication, IEEE Transactions on Very Large Scale Integration
(VLSI) Systems, September 2009.
3. B. Swahn and S. Hassoun, “Thermal Analysis of Multi-Fin Devices”, IEEE Transactions on Very
Large Scale Integration (VLSI) Systems, 816-829, July 2008.
4. S. Hassoun, M. Kudlugi, C. Selvidge, and D. Pryor, "A Transaction-Based Unified Architecture for
Simulation and Emulation", IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
pp. 278-287, February, 2005.
5. S. Hassoun, C., Cromer, and E. Calvillo-Gámez, "Static Timing Analysis for Level-Clocked
Circuits in the Presence of Cross Talk", IEEE Transactions on Computer-Aided Design, September,
2003.
6. D. Dobberpuhl, R. Witek, R. Allmon, R. Anglin, D. Bertucci, S. Britton, L. Chao, R. Conrad, D.
Dever, B. Gieseke, S. Hassoun, G. Hoeppner, K. Kuchler, M. Ladd, B. Leary, L. Madden, E.
McLellan, D. Meyer, J. Montanaro, D. Priore, V. Rajagopalan, S. Samudrala, S. Santhanam. "A
200 MHz 64-b Dual-Issue CMOS Microprocessor", IEEE Journal of Solid-State Circuits,
November, 1992, Vol. 27, No. 11. Also appears in Digital Technical Journal. Vol. 4, No. 4, 1992.
Highly-Refereed Conferences (acceptance rates less than 25%)
7. E . Ullah, K. Lee, and S. Hassoun, “A Weighted Graph Algorithm for Identifying Dominant-Edge
Metabolic Pathways”, International Conference on Computer-Aided Design (ICCAD), November,
2009.
8. B. Swahn and S. Hassoun, "Gate Sizing: FinFETs vs. 32nm Bulk MOSFETs", Design Automation
Conference (DAC), July, 2006.
9. S. Hassoun and C. Alpert, "Optimal Path Routing in Single and Multiple Clock Domain Systems",
IEEE Transaction on Computer-Aided Design (ICCAD), November, 2003.
10. B. Swahn and S. Hassoun, "Hardware Scheduling for Dynamic Adaptability Using External
Profiling and Hardware Threading", International Conference on Computer-Aided Design
(ICCAD), November, 2003.
11. S. Hassoun, C. Alpert, and M. Thiagarajan, "Optimal Buffered Routing Path Constructions for
Single and Multiple Clock Domain Systems", International Conference on Computer-Aided Design
(ICCAD), pp. 247—252, November, 2002.
12. S. Hassoun, C. Cromer, and E. Calvillo-Gámez, "Verifying Clock Schedules in the Presence of
Cross Talk", Design Automation and Test in Europe (DATE) Conference, pp. 346—350, March,
2002.
13. M. Kudlugi, S. Hassoun, C. Selvidge, and D. Pryor, "A Transaction-Based Unified
Simulation/Emulation Architecture for Functional Verification", Design Automation Conference
(DAC), pp. 623—8, June, 2001.
14. S. Hassoun, "Critical Path Analysis Using a Dynamically Bounded Delay Model", Design
Automation Conference (DAC), 260—265, June, 2000.
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15. S. Hassoun, and C. McCreary, "Regularity Extraction Via Clan-Based Structural Circuit
Decomposition", International Conference on Computer-Aided Design (ICCAD), pp. 414—419,
November, 1999.
16. S. Hassoun, and C. Ebeling, "Using Precomputation in Architecture and Logic Synthesis",
International Conference on Computer-Aided Design (ICCAD), pp. 316—423, November, 1998.
17. S. Hassoun and C. Ebeling, "Architectural Retiming: Pipelining Latency-Constrained Circuits",
Design Automation Conference (DAC), June, 1996.
18. R. Allmon, B. Benschneider, M. Callander, L. Chao, D. Dever, J. Farrell, N. Fitzgerald, J.
Grodstein, S. Hassoun, L. Hudepohl, D. Kravitz, J. Lundberg, R. Marcello, S. Marino, J. Pickholtz,
R. Preston, M. Richesson, S. Samudrala, and D. Sanders. "System, Process, and Design
Implications of a Reduced Supply Voltage Microprocessor", IEEE International Solid-State
Circuits Conference (ISSCC), February, 1990.
19. W. Dally, L. Chao, A. Chien, S. Hassoun, W. Horwat, J. Kaplan, P. Song, B. Totty, and S. Wills,
"Architecture of a Message-Driven Processor", International Symposium on Computer Architecture
(ISCA), June, 1987. (A re-write of this article appears in the Best of ISCA 2000.)
Refereed Conferences
20. N. Khan, S. M. Alam, and S. Hassoun “TSV-induced Noise Characterization and Noise Mitigation
using Coaxial TSVs”, IEEE International 3D System Integration Conference, 2009.
21. N. Khan, S. M. Alam, and S. Hassoun “System-Level Comparison of Power Delivery Design for
2D and 3D ICs”, IEEE International 3D System Integration Conference, 2009.
22. B. Swahn and S. Hassoun, " METS: Metric for Electro- Thermal Sensitivity, and Its Application
To FinFETs", International Symposium on Quality Electronic Design, March, 2006.
23. S. Hassoun, "Optimal Use Of 2-Phase Transparent Latches In Buffered Maze Routing", IEEE
International Symposium on Circuits and Systems (ISCAS), May, 2003.
24. F. Aloul, S. Hassoun, K. Sakallah, and D. Blaauw, "Robust SAT-Based Search Algorithm for
Leakage Power Reduction", International Workshop on Power and Timing Modeling, Optimization
and Simulation (PATMOS), 2002.
25. S. Hassoun, "Fine Grain Incremental Rescheduling via Architectural Retiming", International
Symposium on System Synthesis (ISSS), pp. 158-163, December, 1998.
Books and Book Chapters
26. S. Hassoun and T. Sasao, Editors, Logic Synthesis and Verification, Kluwer Academic Publishers,
2002. Book has 15 chapters with contributions from 27 experts in the field.
27. S. Hassoun and T. Villa, "Optimization of Synchronous Circuits", a chapter in "Logic Synthesis
and Verification", editors: Hassoun and Sasao, Kluwer Academic Publishers, pp. 225—253, 2002.
Other Publications
28. E. Ullah, Kyongbum Lee, and Soha Hassoun, “DOMINANT-EDGE PATHWAY: A Weighted
Graph Algorithm for Identifying Dominant Metabolic Pathways”, International Workshop on Bio
Design Automation, July, 2009. Also appears as “An Algorithm for Identifying Dominant-Edge
Metabolic Pathways”, at the International Workshop on Logic and Synthesis, July 2009.
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29. J. Rieffel et al., “Evolving Soft Robotic Locomotion in PhysX”, Workshop on Computational
Intelligence on Consumer Games and Graphics Hardware, 2009.
30. B. Swahn and S. Hassoun, "Thermal and Sensitivity Analysis of Multi-fin devices", International
Workshop on Thermal Investigation of ICs and Systems, Sept, 2006.
31. B. Swahn, S. Hassoun, S. Alam, D. Botha, and A. Vidyarthi, “Thermal Analysis of FinFETs and its
Application to Gate Sizing”, ACM/IEEE International Workshop on Timing Issues in
the Specification and Synthesis of Digital Systems (TAU), February, 2005.
32. A. Vidyarthi and S. Hassoun, “Wave Pipelining for Interconnect”, ACM/IEEE workshop on Logic
and Synthesis, June, 2004.
33. S. Hassoun and D. Marculescu, “Towards GALS Design Methodologies”, workshop on Formal
Methods For Globally Asynchronous Locally Synchronous (GALS) Architecture, September, 2003.
34. J. Xie and S. Hassoun, "A Case Study in IP Functional Customization: The UART 16550",
International Workshop on Logic Synthesis (IWLS), June, 2001.
35. S. Hassoun and C. McCreary, "Clan-Based Structural Circuit Decomposition", International
Workshop on Logic Synthesis (IWLS), June, 1999.
36. S. Hassoun and C. Ebeling, "An Overview of Prediction-Based Architectural Retiming",
International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems
(TAU), December, 1997.
37. S. Hassoun and C. Ebeling, "Experiments in the Iterative Application of Resynthesis and
Retiming", International Workshop on Timing Issues in the Specification and Synthesis of Digital
Systems (TAU), December, 1997.
38. S. Hassoun and C. Ebeling, "Sequential Circuit Optimization Using Precomputation", International
Workshop on Logic Synthesis, May, 1997.
39. S. Hassoun and C. Ebeling, "Architectural Retiming: An Overview", International Workshop on
Timing Issues in the Specification and Synthesis of Digital Systems (TAU), Seattle, WA,
November, 1995.
40. K. Bolding, S.-C. Cheung, S.-E. Choi, C. Ebeling, S. Hassoun, T. Ngo, and R. Wille, "The Chaos
Router Chip: Design and Implementation of an Adaptive Router", International Conference on
Very Large Scale Integration, Grenoble, France, September, 1993.
41. S. Hassoun and G. Borriello, "Improving Finite State Assignment for Two-Level Programmable
Logic Devices", International Workshop on Logic Synthesis (IWLS), May, 1993.
42. S. Hassoun, "A Memory Design for the Message-Driven Processor", MIT VLSI Memo No. 88-564,
August, 1988.
Education Related Publications
43. S. Hassoun and S. Bana, “Practices for Recruiting and Retaining Graduate Women Students in
Computer Science and Engineering, International Conference on Microelectronic Systems
Education, June, 2001.
44. S. Hassoun and G. Janssen, “First CADathlon Programming Contest Held at 2002 ICCAD“, IEEE
Design and Test Magazine, pp. 104—107, May-June, 2003.
Research Grants & Gifts
1. “Multi-Resolution Partitioning and Kinetic Function Estimation for Dynamic Biochemical Network
Model Development”, NSF, Co-PI Kyongbum Lee, Sept 2008-August 2011, with an REU supplement.
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2. “Modeling Neuro-Mechnical Control in Soft-Tissue Organism”, Co-PI: Barry Trimmer, CRA-W, Sept
08-Aug 09
3. Gift, from the Altera Corp., March 2005
4. “Tools for Double-Gate FETs”, NSF, August 2004-August 2006
5. “Tufts CSEMS-Scholars Program", NSF, Co-PI Diane Souvaine, Laurie Baise, Caroline Cao, and
Misha Kilmer, January 2002- January 2006
6. “Tools for Designing and Integrating Configurable Components”, NSF CAREER Award,
February 2001, February 2006
7. “Verification for Deep Submicron Designs”, DAC Design Automation Scholarship, June 2000
8. "Functional and Physical Co-Analysis in Timing Verification", NSF', August 1999-February 2001
9. "Microarchitectural Optimizations and Synthesis", DAC Design Automation Scholarship, June 1998
Select Presentations & Invited Talks
� Computing Research Association Distinguished Lecturer, University of Virginia, VA, Oct, 2007
� Distinguished Lecturer, Northeastern University, Boston, MA, Oct, 2007
� Invited speaker on the topic of FinFETs, University of Toronto, Jan 2006, Altera Corp, Jan. 2006,
University of Michigan Ann Arbor, February 2006, IBM Research Labs Austin, Oct 2006
� Invited speaker, 2006, 2007, 2008, and 2009. Computing Research Association Graduate Cohort
workshops
� Invited speaker, “Optimal Route Construction”, Cadence Berkeley Labs, August, 2003; Intel,
August, 2003; Harvard University, November, 2003; University of Mass, Amherst, Fall, 2003;
Tufts CS seminar, Fall 2003
� Invited speaker, “Let’s Re-sort the Phone Book and Other Topics in Computer Science”, first year
student orientation at Tufts, September, 2003
� Panelist, “Future Leaders and Ideal Hires”, a panel at the International Conference on
Microelectronic Systems Education, June 2001
� Invited speaker, "Department and Grassroots: Improving Graduate School Environment for Female
Students". A presentation at the CRA Snowbird Conference, July 1998. [CRA is the annual meeting
for heads of Computer Science Departments in the US]
� Invited speaker, “Architectural Retiming”, Intel, February, 1998; Synopsys, March, 1998
Professional Service
� Member, Defense Science Study Group, Institute for Defense Analysis, 2010-2011
� Associate Editor for IEEE Transactions on Computer-Aided Design (TCAD), January 2002-
January 2006
� Associate Editor for IEEE Design and Test Magazine (D&T), January 2002- current
� Design Community Chair and member of the Executive Committee for the Design Automation
Conference, June 2008-current
� Technical Program Co-Chair, Design Automation Conference, 2011
� Co-Founder, Executive and Technical Committee member for the International Workshop on
Biology Design Automation, July 2009, and Publicity chair for 2010
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� PhD Forum Co-Chair (2010) and Panelists (2009) for the Grace Hopper Celebration for Women in
Computing
� Member of the IEEE CEDA (Council on Design Automation), and member of the technical
activities group, June 2005-current. Vice President of Technical Activities committee, July 2007-
August 2008
� Member of the CACM (Communication of the ACM) Task Force, A group of dynamic individual
charged by David Patterson, President of ACM, to remap the key flag publication
� Advisory Board member for ACM's Special Interest on Design Automation (SIGDA), 1999-2004
� Director of Educational Activities, ACM/SIGDA. Initiated, organized, and currently direct the
following programs: Ph. D. Forum at DAC, CADathlon at ICCAD, Design Automation Summer
School. Also oversee SIGDA's International Lectureship Program
� Executive Committee member for the International Conference on Computer-Aided Design
(ICCAD), June 2001-2007
� General Chair, the International Conference on Computer-Aided Design (ICCAD), 2006
� Technical Program Chair, the International Conference on Computer-Aided Design (ICCAD), 2005
� Technical Program Vice Chair, the International Conference on Computer-Aided Design (ICCAD),
2004
� Chairperson for the technical sub-committee on Synthesis for the Design Automation Conference
(DAC), 2003, 2004, and 2005
� Technical Program Committee member for the Design Automation Conference (DAC), 2002-2005
� General Chairperson for The International Workshop on Logic and Synthesis, 2002
� Technical Program Chairperson for The International Workshop on Logic and Synthesis, 2001
� Technical Program Committee Member for The International Workshop on Logic and Synthesis,
2000-2005
� Technical Program Committee Member for The International Workshop on Timing Issues in the
Specification and Synthesis of Digital Systems, 2002-2006
� Guest Editor, with Leon Stok (IBM Watson) and Steve Nowick (Columbia), for IEEE Transactions
on Computer-Aided Design special issue on Logic Synthesis, May 2003
� Guest Editor, with Sani Nassif (IBM Austin Research Labs) for IEEE Design and Test Magazine
special issue on Power Grid Design and Analysis, May-June 2003
� Guest Editor, with Yong-Bin Kim (Northeastern) and Fabrizio Lombardi (Northeastern), for IEEE
Design and Test Magazine special issue on Clockless Design, November-December 2003
� Reviewer: IEEE Transactions on Computer-Aided Design, ACM Transaction on Design
Automation of Electronic Systems, IEEE Transaction on VLSI, IEEE Transaction on Electron
Devices, and other conferences and workshops
� Reviewer: Best paper selection committee, ICCAD 2003
� Reviewer: NSF Panel, 2002, 2003, 2004, 2007, 2008, 2009; MICRO program, 2003, 2004
Service and Activities at Tufts
� Undergraduate Committee Chair, 2008-2009
� Member, Campus Planning and Development Committee (CPDC), September 2001- May 2005.
Fall 2008-current
� Member, Equal Educational Opportunity Committee (EEOC), September 2001- May 2004
� Graduate Program Director, 2005-2006, and member of the graduate committee 2001-2006
� Faculty search committee, 2003-2004, 2004-2005, 2008-2009, 2009-2010
Teaching
VLSI & Architecture
� Introduction to VLSI, EE/COMP 103
� Advanced VLSI Design, EE 104
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� Computer Architecture, COMP 40
� Computer Organization, EE 126
� Advanced Computer Architecture, COMP 150-ACA
� Analog Electronics, EE 11
� Computer-Aided Design (Novel technologies) COMP 150-CAD
� Computer-Aided Design (Algorithms) COMP 150-CAD
Other
� Algorithms, COMP 160
� Data Structures, COMP 15
� Stochastic Search and Genetic Algorithms, COMP 150-GA
� Exploring Computer Science, an introductory course, COMP 10
Research Student Advising
� 4 current Ph.D. students; 1 master; 4 undergrads
� Supervised 1 PhD, 8 master projects, and 14 senior design projects
Awards & Distinction
� NSF CAREER award
� IEEE Senior member
� ACM/SIGDA Distinguished Service Award, June 2007
� Tufts University Mellon Fellowship, Spring 2003
� ACM/SIGDA Technical Leadership Award, June 2002
� ACM/SIGDA Service Award, June 2000
� 1995-1996, Women and Minorities Fellowship, CSE Dept., University of Washington
� 1991-1992, Digital Equipment Corporation Fellowship
� 1986-1987, Tau Beta Pi Fellow
CV - Soha Hassoun, 6/7 Updated March, 2010