PCB + ASSEMBLY Research done to determine void reducing optimized profile Reduce voiding for low-standoff components during reflow Bottom terminated components (BTCs) are one of the most ubiquitous of all electronic components. By the end of 2017, approximately 50 billion QFNs (quad-flat pack no-leads), the most common BTC, will be used. In fact, there are enough BTCs in electronics that every man, woman, and child in the world could each have seven. With this great dependency on BTCs, it is important that they perform well. A QFN is the most common BTC. Note the thermal pad on it. One area of great concern that can impact performance is the fact that BTCs generate a considerable amount of heat during their normal operation. The thermal pad, which is soldered to the receiving pad on the printed wiring board (PWB), is designed to remove this heat. Unfortunately, voids that form during reflow soldering can inhibit this process, causing the BTC to overheat and potentially impact reliability. An informal survey of engineers suggests that this voiding issue is the greatest concern in electronics assembly today. Source: Indium Corporation Why do voids form? Voids form due to the evaporation of flux materials in the solder paste. Solder paste is about 50 % of volume flux so the amount of these evolved volatile materials during reflow can be considerable. There is no standard as to how much voiding is acceptable, but there appears to be an agreement that a total void area of less than 50 %, with no “lake” void greater than 40 % of the area, is an absolute requirement; however, 25 % is preferred. In some critical applications such as automotive, 10 % or less is required. Reducing voiding: past work To minimize voiding in the past, process engineers had to perform designed experiments to optimize many of the assembly variables, such as reflow profiles and stencil design. Considerable work was done to investigate the effect of stencil designs to create paths for the evolved flux vapors to escape. 1) Other work showed the benefit of using solder preforms to maximize the amount of solder between the BTC and the PWB pads. 2) Reducing voiding: current work with reflow ovens Considerable developments have occurred in reflow oven technology to minimize voiding – most noteworthy has been the use of vacuum reflow to aid in removing voids. 3) Reports suggest that these ovens have been successful in reducing voiding to less than a few percent. While this achievement is significant, it requires the as- Source: Indium Corporation These X-ray images show voiding. These “lake” voids occupy about 40 % of the area and may cause reliability issues. The “windowpane” stencil design used in the experiments. Source: Indium Corporation 54 EPP EUROPE November 2017
sembler to purchase a new oven or at least an upgrade. There have also been anecdotal reports of solder paste spattering, but we expect that process optimization procedures can minimize this problem. Reflow ovens employing ultrasonic energy have been reported to achieve similar success. 4) As Heller Industries stated in a 2016 presentation, “Ultrasonics are applied when solder is in liquid state.” Ultrasonics create cavitation, which stretches voids/bubbles so they combine with other voids, and move to the outer surface of solder to escape. As with vacuum reflow ovens, the process engineer must purchase a new oven or an upgrade. Reducing voiding: current work with solder paste and process Recently, Indium Corporation conducted research to determine critical variables in minimizing voids, especially in light of modern solder pastes that have been designed to reduce voiding. 5) After considering the many possible variables, they settled upon an experimental plan using the following: • Entek Plus CU-106A-HT OSP PWB pad finish • Laser cut, non-nano-coated steel stencils of 100 μm and 125 μm thicknesses • A windowpane stencil design in the PWB thermal pad area to allow volatiles to escape. The windowpane squares were 0.088 “ on each side • Squeegee printing speed of 100 mm/s with a pressure of 6 kg • Printer separation speed of 5 mm/s at a distance of 2 mm • A stencil wipe (W/D/V) was performed before each board The QFN they assembled had a square ground plane of 7.75 mm (0.30 “) on a side. They performed reflow in air with Profile #1—a straight ramp profile (0.9 ˚C/second ± 0.1 ˚C/second) and a peak temperature of 241 ˚C ± 4 ˚C for most investigations. However, a second optimized profile (Profile #2) was also investigated to determine the effect of the reflow profile on voiding. A variety of solder pastes was used that had halogen-free and halogen-containing fluxes and different solder particles sizes (e.g., Type 3, Type 4, Type References 1) N.C. Lee et al. http://www.indium.com/technical-documents/white paper/voiding-control-for-qfn-assembly 2) Homer, S., Lasky. R, Minimizing Voiding In QFN Packages Using Solder Preforms, SMTAI 2011, Fort Worth, TX. 3) http://www.circuitnet.com/news/uploads/2/SMT_Vac uum_void_reduction_Sept2012.pdf 4) http://www.hellerindustries.com/Inline-Vacuum-Reflow-System.pdf 5) The work is discussed in detail in our paper Minimizing Voiding In SMT Assembly Of BTCs, SMTAI 2016, Chicago, IL. EPP EUROPE November 2017 55
