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TECHNICAL ARTICLE<br />
CLCxIN[0]<br />
CLCxIN[1]<br />
CLCxIN[2]<br />
CLCxIN[3]<br />
CLCxIN[4]<br />
CLCxIN[5]<br />
CLCxIN[6]<br />
CLCxIN[7]<br />
Figure 2<br />
Input Data Selection Gates<br />
See Figure 19-2<br />
lcxg1<br />
lcxg2<br />
lcxg3<br />
lcxg4<br />
See Figure 19-3<br />
Logic<br />
Function<br />
LCxMODE<br />
LCxEN<br />
lcxg<br />
LCxPOL<br />
lcx_out<br />
Interrupt<br />
det<br />
LCxINTP<br />
LCxINTN<br />
Interrupt<br />
det<br />
Q1 LE<br />
LCxOE<br />
LCxOUT<br />
inputs that can come from I/O pins, internal clocks,<br />
Peripherals, or even from register bits. These inputs can<br />
then be passed through one of a number of pre-configured<br />
logic blocks that perform functions like AND-OR, S-R,<br />
J-K and D type flip-flops. What’s then quite nice is that an<br />
external pin can be driven directly from this output, read<br />
internally, or it can even generate an interrupt. It may not<br />
have the flexibility and programmability of, say, a FPGA<br />
LAB, but I can see these becoming very useful glue logic<br />
tools for embedded engineers.<br />
CLCxIN[0]<br />
CLCxIN[1]<br />
CLCxIN[2]<br />
CLCxIN[3]<br />
CLCxIN[4]<br />
CLCxIN[5]<br />
CLCxIN[6]<br />
CLCxIN[7]<br />
CLCxIN[0]<br />
CLCxIN[1]<br />
CLCxIN[2]<br />
CLCxIN[3]<br />
CLCxIN[4]<br />
CLCxIN[5]<br />
CLCxIN[6]<br />
CLCxIN[7]<br />
CLCxIN[0]<br />
CLCxIN[1]<br />
CLCxIN[2]<br />
CLCxIN[3]<br />
CLCxIN[4]<br />
CLCxIN[5]<br />
CLCxIN[6]<br />
CLCxIN[7]<br />
CLCxIN[0]<br />
CLCxIN[1]<br />
CLCxIN[2]<br />
CLCxIN[3]<br />
CLCxIN[4]<br />
CLCxIN[5]<br />
CLCxIN[6]<br />
CLCxIN[7]<br />
Figure 3<br />
000<br />
111<br />
000<br />
111<br />
000<br />
111<br />
000<br />
111<br />
Data Selection<br />
LCxD1S<br />
LCxD2S<br />
LCxD3S<br />
LCxD4S<br />
lcxd1T<br />
lcxd1N<br />
lcxd2T<br />
lcxd2N<br />
lcxd3T<br />
lcxd3N<br />
lcxd4T<br />
lcxd4N<br />
LCxD1G1T<br />
LCxD1G1N<br />
LCxD2G1T<br />
LCxD2G1N<br />
LCxD3G1T<br />
LCxD3G1N<br />
LCxD4G1T<br />
LCxD4G1N<br />
D Q<br />
LCxG1POL<br />
(Same as Data GATE 1)<br />
(Same as Data GATE 1)<br />
(Same as Data GATE 1)<br />
TRIS Control<br />
CLCx<br />
Data GATE 1<br />
Data GATE 2<br />
Data GATE 3<br />
Data GATE 4<br />
sets<br />
CLCxIF<br />
flag<br />
lcxg1<br />
lcxg2<br />
lcxg3<br />
lcxg4<br />
AND - OR OR - XOR<br />
lcxg1 lcxg1<br />
lcxg2<br />
lcxg3<br />
lcxq<br />
lcxg2<br />
lcxg3<br />
lcxg4 lcxg4<br />
LCxMODE=000 LCxMODE=001<br />
4-input AND S-R Latch<br />
lcxg1 lcxg1<br />
lcxg2<br />
lcxg3<br />
lcxq<br />
lcxg2<br />
lcxg3<br />
lcxg4 lcxg4<br />
LCxMODE=010 LCxMODE=011<br />
1-input D Flip-Flop with S and R 2-input D Flip-Flop with R<br />
<strong>EE</strong><strong>Web</strong> | Electrical Engineering Community Visit www.eeweb.com 11<br />
lcxg4<br />
lcxg2<br />
lcxg1<br />
lcxg3<br />
D<br />
S Q<br />
R<br />
lcxq<br />
LCxMODE=100 LCxMODE=101<br />
J-K Flip-Flop with R 1-input Transparent Latch with S and R<br />
lcxg2<br />
lcxg1<br />
lcxg4<br />
lcxg3<br />
Figure 4<br />
J Q<br />
K<br />
R<br />
lcxq<br />
lcxg4<br />
lcxg2<br />
lcxg4<br />
lcxg2<br />
lcxg1<br />
lcxg3<br />
lcxg1<br />
lcxg3<br />
LCxMODE=110 LCxMODE=111<br />
D<br />
LE R<br />
S Q<br />
S Q<br />
D Q<br />
Another nice feature to find in such a small chip is the<br />
Complementary Waveform Generator (CWG). This<br />
allows you generate controllable waveforms for use in a<br />
half bridge or switching power supply for example. The<br />
module allows for selectable input sources and have<br />
some nice and simple auto-shutdown controls. Dead<br />
time is also programmable for both the rise and fall side.<br />
I’ve seen similar modules on the larger chips but found<br />
this much easier to understand and more independent of<br />
the code that may be running on the core.<br />
Both the CLC and CWG could be really nice units if only<br />
you have a clock source that is easy to control and whose<br />
frequency is easy to set. Well the chips now also come<br />
with a Numerically Controlled Oscillator (NCO) that can<br />
be used to feed the above CLC and CWG modules. This<br />
is no Phase Lock Loop (PLL) but will allow for simple<br />
clock division. The module works by having a configured<br />
value added to an accumulator on each clock cycle.<br />
The overflow is then used as a raw output that can be<br />
R<br />
R<br />
lcxq<br />
lcxq<br />
lcxq<br />
lcxq<br />
TECHNICAL ARTICLE
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