Phase splitter Concertina Phase Splitter

Phase splitter
Concertina Phase Splitter
This circuit provides two output signals in phase opposition. The output resistances of
the two outputs are very different. Therefore, the signals should be fed into high-inputresistance
circuits if the correct relative signal magnitudes are to be maintained.
Rs
Vs
+
Vin
-
C1
R1
VB
R2
RC
VC
BJT
VE
RE
VCC
VO1
VO2
Assembly on the breadboard.

Phase splitter
Synthesis
The biasing voltages of the collector (V CQ) and emitter (V EQ) are chosen so to ensure
maximum dynamic of the signals on the collector and emitter.
V CQ=3V CC/4 e V EQ=V CC/4 consequently V CEQ=V CC/2
1) On R C and R E there is the same voltage drop, therefore the two resistors must have the
same value (R) which is obtained by the equation on the output mesh:
R1
R2
V B
I C
BJT
V CC
Rc
V CQ
V EQ
R E
V −V
VCC = I CQ·2·R+ VCEQ ⇒ R=
I ·2
2) Calculate R 2 :
3) Calculate R 1:
CC CEQ
CQ
1 1
R2 = ⋅hFE ⋅ R = ⋅
10 10
h FE min·hFEmax ⋅R
or
VB R2= I
VB =
10⋅I VB
=
10⋅I
⋅ h FE min·hFEmax R2BQ CQ
V −V
R = R
CC B
1
VB
2

Phase splitter
Long-tailed pair Phase Splitter
This circuit is known as a long-tailed pair because the two BJT's share the resistor REE. A signal applied at the CEC input causes an opposite signal Vout1 and a signal with same
phase at the CBC input.
So, the signal Vout2 has same phase of the signals at the input of the CBC.
Consequently the signals Vout1and Vout2 have opposite phase.
|Vout1|=|Vout2| results if the signal current iREE=0 (and iQ1=iQ2) or for real conditions |Vout1|º|Vout2| if iREE 100
1+ h
fe
CEC
For the BC107 (h ie=4kΩ, h fe=250)
R EE > 1.6kΩ
V in
R1
C1
R2
Rc
V out1
V CC
Rc
Q1 Q2
i Q1
i REE
-V EE
V out2
R EE
i Q2
R1
R2
C2
+
CBC

C 1
V in
R 1
V B1
R 2
V C1
R c
V out1
V CC
R c
V out2
Q1 Q2
I REE
V E
R EE
-V EE
V C2
R 1
V B2
R 2
+
C 2
+
V in
Vout1 RCRC =− ≅− h
V h + R h
in ie ie
-
i b
R 1//R 2
fe
h fei b
h ie
R C
V out1
R C
R EE
h fei b
i b
h ie
hie hie
R= R EE // ≅
1+ h 1+ h
fe fe

Phase splitter
Synthesis
The circuit is symmetric so the emitter resistor can be divided in two parallel resistors with
value 2REE and the synthesis can be done considering half circuit.
The following assumptions are used VCC=-VEE=10V,VBEQ=0.65V, ICQ=1 mA,VCEQ=5V, VEQ=0. CC CEQ
1) Calculate RC : RC= = 5kΩ
ICQ
2) Calculate 2R EE :
3) Calculate R 2 :
4) Calculate R 1:
V −V
VEQ + VEE10V 2REE = = = 10kΩ
I 1mA
CQ
The R EE condition must be veryfied :
For the BC107 h = h ⋅0.95 ≅ 211
FE 1mA FE 2mA
ICQ 1mA
IR2 = 10I BQ = 10 ≅10 ≅47μ
A
h 211
VB V BE 065 . V
R2 = = ≅ ≅14kΩ
I I 47μ
A
R2 R2
FE 1mA
VCC −VBE9.35V
IR1 ≅ IR2→ R1= = ≅ 200kΩ
I 47μA R1
( )
R > 100 ⋅ h / 1+ h
EE ie fe
R1
R2
V B
I R1
I R2
I BQ
I CQ
BJT
V CC
Rc
V CQ
V EQ
2R EE
-V EE

Differential Amplifier
This circuit allows to obtain an output signal
proportional to the difference of the input signals.
Where A d is the differential gain.
v out = A d (v in1-v in2)
On the other hand, there is an output signal also in
thecaseofV IN1 =V IN2, this signal depends from (not
desired) common mode amplification A C.Therefore
for a real differential amplifier, in general, we can write:
v out = A d (v in1-v in2) + A c (v in1+v in2)/2
vin1
RC
BJT1
REE
VCC
IC+ic1 IC+ic2
ic1d=-ic2d
-VEE
BJT2
RC
2IC+2ic1c
-V EE and R EE (R EE with high value) work as a current generator that:
determines the bias current I C of the two BJT and
contrasts the current variations of R EE.
The collector currents (i c1, i c2) related to v in1, v in2 consist of two components:
i = i + i ; i = i + i
C3
vin2
c1 c1d c1c c2 c2d c2c One relative to the difference of the signals the other relative to the common mode signal.
i = i ; i = - i
The current generator requires that |i c1d|>>|i c1c| and |i c2d|>>|i c2c|.
c2c c1c c1d c2d vout

v out = A d (v in1-v in2) + A c (v in1+v in2)/2
RC
BJT1
VCC
IC+icd1 IC+icd2
ic1d= -ic2d
REE
2IC
-VEE
+ vd -
BJT2
C3
vout
v in1 = v d/2 and v in2 = -v d/2
RC
+
Vc
-
vin1
RC
BJT1
REE
VCC
IC+icc1 IC+icc2
-VEE
BJT2
2IC+2icc1
v in1 = v in2 = v c
RC
vin2
C3
vout
+
Vc
-

The two amplifications can be estimated by considering two situations:
1) V in1 = V in2 = V s
+
vS
-
vin1
RC
BJT1
VCC
IC+ics1 IC+ics2
REE
BJT2
2IC+2ics1
-VEE
RC
vin2
C3
vout
+
vS
-
A
c
vin1=vs
RC
2REE
BJT1
IC+ic1s IC+ic2s
BJT2
RC
V Rh
o
C fe
= =−
V 2 h + 1+ h 2R
( )
2REE
vout
vin2=vs
in ie fe EE
ic2s
BJT2
RC
2REE
vout
vin2=vs

2) V in1 = V d/2 and V in2 = -V d/2
+
vd/2
-
vin1
RC
BJT1
VCC
IC+icd1 IC+icd2
REE
ic1d
2IC
-VEE
BJT2
RC
vin2
C3
vout
-
vd/2
+
vin1=vd/2
BJT1
Vo V Rh o V Rh
o
= =− ; Ad
= =
V 2 −V
/ 2 h V 2h
C fe C fe
in d ie d ie
Electronics: a systems approach by N. Storey
RC
IC+ic1d IC+ic2d
E
REE
c
BJT2
RC
C3
vout
v in2= - v d/2
ic2d
BJT2
RC
vout
vin2=- vd/2
The parameter, which specifies how the real amplifier is close to that ideal, is the
common mode rejection ratio:
Ad
CMRR =
A
The behavior of the differential amplifier is close to that ideal if CMRR is great, in
other words if A d is much larger than A c.

The differential stage which will be realized in experiments is shown in the figure.
V in1
R 1
R C
R 2
BJT1
i C1
R EE
For the biasing network, the synthesis procedure is the same of the long-tailed
pair phase splitter.
So dividing the circuit, knowing the V EE and V CC values and selecting the
biasing voltages and currents of the components the biasing network can be
defined.
V CC
i C2
-V EE
R C
BJT2
R 2
R 1
C 3
V out
V in2
100kΩ C1 C
A
2 100kΩ
R L

To measure the two amplification you can proceed in several ways, but two
measures must be made, here are some methods.
A) 1 st measure V in1=-V in2=V test, in this case A d =V out1/(2V test)
2 nd measure V in1=V in2=V test, in this case A c =V out2/V test
B) 1 st measure V in1= V test ,V in2=0, in this case V out1=A dV test+A cV test/2
2 nd measure V in1= 0,V in2= V test, in this case V out2= -A dV test+A cV test/2
V out2 is in phase opposition respect to V out1 so -V out2 is assumed, adding the two
obtained output signals :
V out1 +V out2 =A cV est A c= (V out1 +(-V out2))/V test
V out1 -V out2 =2A dV test A d =(V out1 - (-V out2))/2V test
C) 1 st measure V in1=V in2=V test, in this case A c =V out1/V test
2 nd measure V in1= V test ,V in2=0, in this case V out2=A dV test+A cV test/2
From which is obtained:
A d =V out1 /V test -A c /2

v out = A d (v in1-v in2)
v in1 non-inverting input
v in2 inverting input
vin 1
R C
BJT 1
in1
Volt.
in2
Volt.
IC+i c1
ic1d=-ic2d
R EE
V CC
BJT1
Cur.
BJT2
Cur.
I C+i c2
BJT2
2I C+2i c1s
-VEE
R C
BJT2
Cur.
Out
Volt.
C 3
v in 2
v ou t
Out
Volt.