ANAGRAM Hardware for HiFi™ Family Data Sheet June ... - ABC PCB

Q5M-DS-110A JUNE-2007 

Abstract 

Q5 asynchronous sample rate converter data sheet. 

ANAGRAM Hardware for HiFi Family 

Copyright © Anagram Technologies SA 

All rights reserved. No part of this work covered by Anagram Technology SA copyright may be reproduced or 

copied in any form or by any means (graphic, electronic or mechanical, including photocopying, recording, 

taping or information retrieval systems) without the written permission of Anagram Technology SA. 

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Data Sheet 

June 2007 

ANAGRAM Technologies SA 

ZI Le Trési 6A 

1028 Préverenges 

Switzerland 

Phone: + 41 21 804 1960 

Fax: + 41 21 804 1961 

info@anagramtech.com

Document History 

Q5M-DS-110A 

Q5 Data Sheet 

Document Control 

No. Primary Author(s) Description of Version Date Completed 

100A TLn Initial revision 30-08-2005 

110A PHi Update to match the User Manual 110A 19-06-2007 

Related Documentation 

Part Number Description 

Q5M-PB-100A Q5 product brief. 

Q5E-UM-110A Q5 Evaluation board user manual. 

Ordering Information 

Part Number Description Package 

Q5M-PL-100A Asynchronous sample rate converter. Plastic 

Release Notice 

This document is under configuration control and updates will only be issued as a replacement document 

with a new version number. 

. 

Submit Documentation Feedback Page 2 of 56

About This Data Sheet 

Company Address 

Notice 

Q5M-DS-110A 


Preface 

Preface 

This document provides the information needed to design and integrate the Q5 

asynchronous sample rate converter module into your product. For more information about 

this product, please refer to the product description available from the ANAGRAM 

Technologies web site at http://www.anagramtech.com. 

ANAGRAM Technologies SA 

ZI Le Trési 6A 

1028 Préverenges 

Switzerland 

Phone +41 21 804 1960 

Fax +41 21 804 1961 

Email info@anagramtech.com 

ANAGRAM Technologies S.A. provides the enclosed product(s) under the following 

conditions: 

The user assumes all responsibility and liability for proper and safe handling of the goods. 

Further, the user indemnifies ANAGRAM Technologies from all claims arising from the 

handling or use of the goods. Please be aware that the products received may not be 

regulatory compliant or agency certified (FCC, UL, CE, etc.). EXCEPT TO THE EXTENT 

OF THE INDEMNITY SET FORTH ABOVE, NEITHER PARTY SHALL BE LIABLE TO 

THE OTHER FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL 

DAMAGES. ANAGRAM Technologies currently deals with a variety of customers for 

products, and therefore our arrangement with the user is NOT EXCLUSIVE. ANAGRAM 

Technologies assumes NO LIABILITY FOR APPLICATIONS ASSISTANCE, CUSTOMER 

PRODUCT DESIGN, SOFTWARE PERFORMANCE, OR INFRINGEMENT OF PATENTS 

OR SERVICES DESCRIBED HEREIN. 

Please read the Data Sheet and, specifically, the Warnings and Restrictions notice in the 

Data Sheet prior to handling the product. This notice contains important safety information 

about temperatures and voltages. For further safety concerns, please contact the 

ANAGRAM Technologies customer support. Persons handling the product must have 

electronics training and observe good laboratory practice standards. No license is granted 

under any patent right or other intellectual property right of ANAGRAM Technologies 

covering or relating to any machine, process, or combination in which such ANAGRAM 

Technologies products or services might be or are used. 

Module Warnings and Restrictions 

It is important to operate this product within the specified input and output ranges described 

in the Data Sheet. Exceeding the specified input range may cause unexpected operation 

and/or irreversible damage to the Module. If there are questions concerning the input 

range, please contact ANAGRAM Technologies customer support prior to connecting the 

input power. Applying loads outside of the specified output range may result in unintended 


Q5M-DS-110A 


Preface 

operation and/or possible permanent damage to the Module. Please consult the Data 

Sheet prior to connecting any load to the Module. If there is uncertainty as to the load 

specification, please contact ANAGRAM Technologies customer support. 

How to Use This Document 

Throughout this document, the abbreviation QM and the term Q5 Module are 

synonymous with the Q5 Asynchronous Sample Rate Converter. 

Chapter 1 Overview of the Q5 Module functionality. 

Chapter 2 Electrical and performance characteristics. 

Chapter 3 Interfacing and application information for hardware and systems engineers. 

Chapter 4 Software mode operation. 

Chapter 5 Hardware mode operation. 

Chapter 6 Typical performance plots. 

Chapter 7 Mechanical and packaging information. 

Information About Cautions and Warnings 

If You Need Assistance 

Note 

A NOTE provides additional or special information to assist 

operation and maintenance personnel. Disregarding a NOTE 

may cause inconvenience but will not result in personal injury or 

equipment damage. 

Caution 

A CAUTION is provided in a procedure whenever electrical or 

mechanical damage may occur. Failure to heed a CAUTION 

may result in some form of damage to the equipment; however, 

personal injury is unlikely. 

If you have questions regarding either the use of this module or the information contained 

in the accompanying documentation, please contact the ANAGRAM Technologies 

Customer Support +41 (21) 804-1960 or visit the ANAGRAM Technologies web site at 

http://www.anagramtech.com. 


Repair and Maintenance 

Copyright 

Q5M-DS-110A 


Preface 

Routine maintenance is not required. This product named as Q5 Module is warranted to 

be free of any defect with respect to performance, quality, reliability and workmanship for a 

period of SIX (6) months from the date of shipment from ANAGRAM Technologies SA. 

In the event that your product proves to be defective in any way during this warranty period, 

we will gladly repair or replace this piece of equipment with a unit of equal or superior 

performance characteristics. 

Should you find this Q5 Module has failed after your warranty period has expired, we will 

repair your defective piece of equipment for as long as suitable replacement components 

are available. You, the owner, will bear any labor and/or component costs incurred in the 

repair or refurbishment of said equipment, beyond the SIX (6) months warranty period. Any 

attempt to repair this product by anyone during this period other than by ANAGRAM 

Technologies SA or any authorized 3 rd party, will void your warranty. 

ANAGRAM Technologies SA reserves the right to assess any modifications or repairs 

made by you and decide if they fall within warranty limitations, should you decide to return 

your product for repair. In no event shall ANAGRAM Technologies SA be liable for direct, 

indirect, special, incidental, or consequential damages (including loss and profits) incurred 

by the use of this product. Implied warranties are expressly limited to the duration of this 

warranty. 

A Return Material Authorization number (RMA) will be issued to you, as well, as specific 

shipping instructions, should you wish our factory to repair your Q5 Module. The RMA 

number has to be requested from ANAGRAM Technologies S.A before sending back the 

failed module. A temporary replacement, if required, will be made available for a nominal 

charge. Any shipping costs incurred, will be the responsibility of the customer. All products 

shipped to you from ANAGRAM Technologies SA, will be shipped collect. 

© 2006 ANAGRAM Technologies SA. All right reserved 

Contents of this publication may be not reproduced in any form without the written 

permission of ANAGRAM Technologies S.A. Reproduction or reverse engineering of 

copyrighted software is prohibited. 


Q5M-DS-110A 


Table of Contents 

LIST OF FIGURES ............................................................................................................ 8 

LIST OF TABLES.............................................................................................................. 9 

LIST OF PLOTS .............................................................................................................. 10 

1 INTRODUCTION....................................................................................................... 12 

1.1 Highlights........................................................................................................................................12 

1.2 Functional Block Diagram...............................................................................................................12 

1.3 DSS Synchronization..................................................................................................................13 

1.4 Q5 Upsampling ...........................................................................................................................14 

1.5 ATF Adaptive Time Filtering .......................................................................................................14 

1.6 DSD to PCM Conversion................................................................................................................15 

1.7 DSF Filtering ...............................................................................................................................16 

2 CHARACTERISTICS AND SPECIFICATIONS ........................................................ 17 

2.1 Electrostatic Discharge Warning ....................................................................................................17 

2.2 Recommended Operating Conditions ............................................................................................17 

2.3 Absolute Maximum Operating Conditions......................................................................................17 

2.4 Performance Specifications............................................................................................................18 

2.5 Digital Filter Characteristics............................................................................................................18 

2.6 Pin Descriptions..............................................................................................................................18 

3 INTERFACING AND OPERATION........................................................................... 21 

3.1 General Description........................................................................................................................21 

3.2 Typical Connections .......................................................................................................................22 

3.3 Interfacing to Digital Audio Receivers and Transmitters ................................................................23 

3.4 Interfacing to High Performance D/A Converters...........................................................................24 

3.5 Reference Master Clock.................................................................................................................24 

3.6 Reset and Power On ......................................................................................................................25 

3.7 Audio Serial Ports - RX0 Input .......................................................................................................25 

3.8 Audio Serial Ports - TX0 Output .....................................................................................................27 

3.9 Audio Serial Ports – TX1 Output ....................................................................................................28 

3.10 Data Resolution and Dither ............................................................................................................28 

3.11 Incoming Sampling Rate and Locking............................................................................................29 

3.12 Muting.............................................................................................................................................29 

3.13 Phase Inversion..............................................................................................................................29 

3.14 Direct Downsampling......................................................................................................................29 

3.15 Stereo DSD to PCM Conversion ....................................................................................................29 

3.16 Interrupt Request / Unlock Detection .............................................................................................30 

3.17 Data Valid Input ..............................................................................................................................30 

3.18 Serial Port Interface (SPI Port).......................................................................................................30 


4 SOFTWARE MODE .................................................................................................. 33 


4.2 Module Registers Overview ...........................................................................................................33 

4.2.1 Input Control Register ..............................................................................................33 

4.2.2 Output Control Register............................................................................................34 

4.2.3 Process Control Register .........................................................................................34 

4.2.4 Software Revision Register ......................................................................................34 

4.2.5 Product ID Register ..................................................................................................35 

5 HARDWARE MODE ................................................................................................. 36 


5.2 Default Configuration......................................................................................................................36 

5.3 Function Selection..........................................................................................................................36 

6 PERFORMANCE PLOTS ......................................................................................... 37 

6.1 Standard Measurement Conditions................................................................................................37 

6.2 FFT Plot, Sine wave, 0dBFS, 1kHz Performance Plots .................................................................37 

6.3 FFT Plot, Sine wave, -60dBFS, 1kHz Performance Plots..............................................................40 

6.4 FFT Plot, Sine wave, 0dBFS and -3dBFS, 20kHz Performance Plots...........................................43 

6.5 FFT Plot, Sine wave, 0dBFS, 80kHz Performance Plots ...............................................................46 

6.6 Linearity, 200Hz Tone, 0 -140dBFS input, Performance Plots ......................................................47 

6.7 FFT Plot, IMD, 10 and 11kHz Performance Plots ..........................................................................49 

6.8 THD+N vs Input Amplitude.............................................................................................................51 

6.9 THD+N vs Input Frequency............................................................................................................53 

6.10 Passband Ripple ............................................................................................................................55 

7 PACKAGING AND DIMENSIONS ............................................................................ 56 

7.1 Package Dimensions Metric...........................................................................................................56 

Q5M-DS-110A 



Q5M-DS-110A 


List of Figures 

Figure 1 Functional block diagram.................................................................................................13 

Figure 2 Clock domain block diagram illustrating DSS ..............................................................13 

Figure 3: ATF vs standard upsampling ..........................................................................................14 

Figure 4: ATF vs standard upsampling error path .........................................................................15 

Figure 5: ATF vs standard upsampling jitter response ..................................................................15 

Figure 6: ATF vs standard upsampling jitter analysis ....................................................................15 

Figure 7 Pinout top down view.......................................................................................................20 

Figure 8 Typical connections in software mode.............................................................................22 

Figure 9 Typical connections in hardware mode. ..........................................................................22 

Figure 10 Interfacing to a digital receiver.......................................................................................23 

Figure 11 Interfacing to a digital transmitter...................................................................................23 

Figure 12 Interfacing with dual mono 384kHz D/A converters.......................................................24 

Figure 13 Reset timing requirements.............................................................................................25 

Figure 14 Input stereo data formats...............................................................................................26 

Figure 15 TX0 output data formats ................................................................................................27 

Figure 16 TX1 output data format ..................................................................................................28 

Figure 17 SPI protocol for register read / write operations ............................................................31 

Figure 18 SPI port timing requirements .........................................................................................32 

Figure 19 Housing physical dimensions (metric). ..........................................................................56 


Q5M-DS-110A 


List of Tables 

Table 1 Recommended operating ratings......................................................................................17 

Table 2 Absolute maximum ratings................................................................................................17 

Table 3 Performance specifications...............................................................................................18 

Table 4 Digital filter characteristics ................................................................................................18 

Table 5 Pinout Descriptions. ..........................................................................................................20 

Table 6 Reference master clock frequency ...................................................................................24 

Table 7 Reset timing requirements ................................................................................................25 

Table 8 Serial input clocks in PCM mode ......................................................................................26 

Table 9 Serial input clocks in DSD mode.......................................................................................27 

Table 10 TX0 output frequency sampling vs CLKIN frequency .....................................................27 

Table 11 TX0 output clocks ...........................................................................................................27 

Table 12 TX1 output frequency sampling vs CLKIN frequency .....................................................28 

Table 13 TX1 output clocks ...........................................................................................................28 

Table 14 SPI byte definitions for register read / write operations ..................................................31 

Table 15 SPI port timing requirements ..........................................................................................32 

Table 16: Overview of command registers ....................................................................................33 

Table 17 Input Control Register .....................................................................................................34 

Table 18 Output Control Register ..................................................................................................34 

Table 19 Process Control Register ................................................................................................34 

Table 20 Software Revision Register.............................................................................................35 

Table 21 Product ID Register.........................................................................................................35 


Q5M-DS-110A 


List of Plots 

Plot 1: FFT 0dBFS 1kHz PCM 32.0 - PCM 48.0............................................................................37 

Plot 2: FFT 0dBFS 1kHz PCM 32.0 - PCM 192.0..........................................................................37 








Plot 10: FFT 0dBFS 1kHz PCM 192.0 - PCM 192.0......................................................................39 

Plot 11: FFT 0dBFS 1kHz DSD - PCM 96.0 ..................................................................................39 

Plot 12: FFT 0dBFS 1kHz PCM 192.0 - PCM 96.0........................................................................39 

Plot 13: FFT 0dBFS 1kHz DSD - PCM 48.0 ..................................................................................39 

Plot 14: FFT 0dBFS 1kHz DSD - PCM 192.0 ................................................................................39 

Plot 15: FFT -60dBFS 1kHz PCM 44.1 - PCM 48.0.......................................................................40 

Plot 16: FFT -60dBFS 1kHz PCM 44.1 - PCM 192.0.....................................................................40 





Plot 21: FFT-60dBFS 1kHz PCM 192.0 - PCM 192.0....................................................................41 



Plot 24: FFT -60dBFS 1kHz DSD - PCM 48.0 ...............................................................................41 


Plot 26: FFT-60dBFS 1kHz DSD - PCM 192.0 ..............................................................................42 







Plot 33: FFT 0dBFS 20kHz PCM 192.0 - PCM 192.0....................................................................44 





Plot 38: FFT -3dBFS 20kHz DSD - PCM 192.0 .............................................................................45 

Plot 39: FFT 0dBFS 80kHz PCM 192.0 - PCM 192.0....................................................................46 

Plot 40: LINEARITY 200Hz PCM 44.1 - PCM 48.0........................................................................47 

Plot 41: LINEARITY 200Hz PCM 44.1 - PCM 192.0......................................................................47 






Plot 46: LINEARITY 200Hz PCM 192.0 - PCM 192.0....................................................................48 



Plot 49: IMD -7dBFS 10kHz 11kHz PCM 44.1 - PCM 48.0 ...........................................................49 

Plot 50: IMD -7dBFS 10kHz 11kHz PCM 44.1 - PCM 192.0 .........................................................49 





Plot 55: IMD -7dBFS 10kHz 11kHz PCM 192.0 - PCM 192.0 .......................................................50 

Plot 56: THD+N vs AMPL 1kHz PCM 44.1 - PCM 48.0 .................................................................51 

Plot 57: THD+N vs AMPL 1kHz PCM 44.1 - PCM 192.0 ...............................................................51 









Plot 66: THD+N vs FREQ 0dBFS PCM 44.1 - PCM 48.0 ..............................................................53 

Plot 67: THD+N vs FREQ 0dBFS PCM 44.1 - PCM 192.0 ............................................................53 



Plot 70: THD+N vs FREQ PCM 48.0 - PCM 96.0..........................................................................54 

Plot 71: THD+N vs FREQ PCM 96.0 - PCM 48.0..........................................................................54 

Plot 72: THD+N vs FREQ PCM 192.0 - PCM 48.0........................................................................54 




Plot 76: Passband Ripple 0dBFs PCM 44.1 - PCM 48.0 ...............................................................55 

Plot 77: Passband Ripple 0dBFs PCM 44.1 - PCM 192.0 .............................................................55 

Q5M-DS-110A 



Q5M-DS-110A 


Introduction 

1 Introduction 

This chapter gives a brief introduction to the features and principle technologies behind the 

Q5 Module a 384kHz high performance asynchronous sample rate converter. 

1.1 Highlights 

The Q5 Module is a high performance asynchronous sample rate converter designed for 

high end, pro and consumer audio applications. Key features for the Q5 Module include: 

High resolution asynchronous 24bit / 384kHz sample rate converter. 

Integrates with DSS synchronization technology for superb jitter rejection. 

DSD to PCM conversion with Q5 Upsampling for seamless audio format 

integration. 

Automatic input sampling frequency sensing. 

Supports sample rates input from 32 to 192kHz and word length from 16 to 24bit. 

Up to -147dBFS THD+N (1kHz, 0dBFS). 

Two digital output ports, 8xFS upsampled output port and an additional direct 

downsampled 1x / 2x / 4xFS output port are available. 

Input format: I2S or 2 channel DSD. 

Output format: I2S and DSP. 

Selectable output word length and dithering. 

Standalone hardware and configurable software modes available. 

1.2 Functional Block Diagram 

The Q5 Module integrates four key technologies, Q5 Upsampling, DSS 

Synchronization, ATF Adaptive Time Filtering, and DSF SACD Conversion for DSD 

processing support to deliver a highly integrated asynchronous sample rate converter and 

digital synchronizer. The module features a single audio input port capable of supporting 

PCM data up to 24bit from frequencies 32 to 192kHz or stereo DSD (2.8224MHz). In either 

case, the DSD signal or the direct PCM input are upsampled to a common internal 8xFS 

PCM format. 


Q5M-DS-110A 


1.3 DSS Synchronization 

Figure 1 Functional block diagram 

Introduction 

The Q5 Module employs a concept of clock management called DSS synchronization 

which allows any incoming audio stream to be resynchronized and retimed to a local high 

quality clock. By using a stable clock reference, the negative effects of inter-component 

jitter can be minimized. When converting the digital audio signal to an analog through high 

performance D/A converters, this reduction in jitter has enormous benefits in the level of 

detail and clarity in the reconstructed analog sound. 

Figure 2 Clock domain block diagram illustrating DSS 


Q5M-DS-110A 


1.4 Q5 Upsampling 

Introduction 

Q5 Upsampling allows digital audio signals from virtually any audio source to be 

resampled, resynchronized and retimed to extraordinary levels of detail. In effect, 

upsampling the digital data stream (up to 384kHz) allows existing “standard” CDs to have 

the enhanced audio clarity, richness and dynamic range that would normally be associated 

with SACD or DVD-A disks “upgrading” the tremendous investment that has already been 

made in high quality CD recordings. You may be astonished once you begin to hear what 

you have been missing! 

Three proprietary ANAGRAM technologies are included in Q5: adaptive time filtering, 

data-to-system synchronization, and a virtual time-domain model. These technologies 

effectively reduce noise artefacts caused by imperfect digital systems and allow the digital 

signal to closer represent the true analog sound of the studio mastered audio data. 

1.5 ATF Adaptive Time Filtering 

Adaptive Time Filtering or ATF is a resampling process that allows audio data to be 

interpolated at a higher precision than standard techniques used in off-the-shelve sample 

rate converters. ATF uses an advanced polynomial curve fitting algorithm that closer 

matches the original audio data, than sample-and-hold, or piece-wise linear estimation 

interpolators, commonly used today. This advanced technique allows jitter invoked errors in 

the resampling process to be minimized to a point where they no longer become relevant, 

and as this process is extremely efficient, ATF allows Q5 Upsampling to be implemented 

on low cost DSPs boosting overall system performance without impacting on cost. 

Standard interpolators are of two types, sample-and-hold, or piece-wise linear and typically 

have a maximum output signal sampling frequency limited to 192kHz. The diagram below 

shows a comparison between normal upsampling and Q5 Upsampling running at 384kHz 

using ATF in the theoretical case where all clocking is jitter free. In the following diagrams 

we will show how ATF provides superior performance in the presence of jitter and how it 

minimizes the impact of resampling jitter. 

Figure 3: ATF vs standard upsampling 

The first thing to notice between ATF and other interpolators is the error path between 

output samples. This error path in a sample-and-hold interpolator will have a path that does 

not follow the original sample data, as show below. In the case of ATF, the error path is 

determined by the smooth curve fitting algorithm, which recalculates a new path every 

sample, resulting in a path that closely follows the original audio input data. 


Q5M-DS-110A 


Introduction 

Figure 4: ATF vs standard upsampling error path 

Having an error path that closely matches the original data will have two benefits: 

resampling errors caused by jitter appearing on data clocks and by using arbitrary non 

integer sample rates e.g. 44.1kHz to 48kHz will be minimized. In the case of Q5 the 

extremely small residual error that is left is designed to be beyond the dynamic range of 

24bit audio which is far superior of that of sample-and-hold or piece-wise linear 

interpolators. 

Figure 5: ATF vs standard upsampling jitter response 

Performing an frequency domain analysis of the resampling error invoked by data jitter or 

arbitrary non integer sample ratios we find that ATF has some interesting properties. Firstly 

since ATF is a non-linear process resampling errors are uncorrelated with amplitude, 

which is not the case with the sample and hold interpolator, and secondly due to the 

smooth time domain function of ATF, error harmonics will be greatly reduced. 

Figure 6: ATF vs standard upsampling jitter analysis 

1.6 DSD to PCM Conversion 

The Q5 Module can use a Direct Stream Digital (DSD) audio stream @ 2.8224MHz (64 x 

44.1kHz) as input audio source. A DSD stream is a one bit delta-sigma modulated digital 

audio signal sampled in a sequence of very high frequency. This format is used to store 

audio on Super Audio Compact Disc (SACD). Audio processing of the input DSD stream 

inside the Q5 Module is done by first converting the DSD data to PCM format thanks to 


Q5M-DS-110A 


Introduction 

the DSF Filtering, then using standard PCM audio processing techniques. The audio 

channel configuration supported by the Q5 Module is 2-channel stereo DSD. 

1.7 DSF Filtering 

Due to its very high sampling rate (2.8224MHz) and one bit nature, DSD is incompatible 

with already implemented signal processing functions targeting standard PCM data. Thus 

Anagram has developed Direct Stream Filtering (DSF Filtering) algorithm that can 

convert DSD streams to PCM up to 8xFS with superb quality. The Q5 Module integrates 

this feature in order to supply very high audio quality from a DSD audio stream and 

therefore significantly enhance performance of any audio applications requiring SACD 

support. 


Q5M-DS-110A 


Interfacing and Operation 

2 Characteristics and Specifications 

This chapter identifies important information regarding the Q5 Module that you should 

know before getting started. 

2.1 Electrostatic Discharge Warning 

Many of the components in the Q5 Module are susceptible to damage by electrostatic 

discharge (ESD). Customers are advised to observe proper ESD handling precautions 

when unpacking and handling the Q5 Module, including the use of a grounded wrist strap 

at an approved ESD workstation. 

Caution 

Failure to observe ESD handling procedures may result in 

damage to the Q5 Module. 

2.2 Recommended Operating Conditions 

Hereafter is given recommended conditions where the module should work properly. 

Exceeding these conditions is not advisable but acceptable. Table 1 summarizes the 

recommended data points. 

Parameter Recommended Condition 

Power Supply +3.3V / +3.6V 

Input Audio VIL(min/max): 0V / +0.4V VIH(min/max): +2.2 / +3.6V 

Input SPI VIL(min/max): 0V / +0.4V VIH(min/max): +2.2 / +3.6V 

Table 1 Recommended operating ratings 

2.3 Absolute Maximum Operating Conditions 

The user should be aware of the absolute maximum operating conditions for the Q5 

Module. Exceeding these conditions may result in damage to the QM. Table 2 summarizes 

the critical data points. 

Parameter Maximum Condition 

Power Supply −0.5V / +3.8V 

Input Audio −0.3 to +3.6V 

Input SPI −0.3 to +3.6V 

Table 2 Absolute maximum ratings 


Q5M-DS-110A 


Caution 


Failure to respect the Absolute Maximum Operating conditions 

may result in damage to the internal Q5 Module components. 

2.4 Performance Specifications 

Parameter Min Typ Max Unit 

Input Resolution 16 - 24 bit 

Input Frequency 32 - 192 kHz 

Sample Rate Ratio – Upsampling 1:12 

Sample Rate Ratio – Downsampling 4:1 

Dynamic Range - 24 - bit 

THD+N -140 -144 -147 dB 

Table 3 Performance specifications 

2.5 Digital Filter Characteristics 

Parameter Typ Unit 

Passband 0.454 x FSin - 

Passband Ripple ±0.004 dB 

Stopband 0.546 x FSin - 

Stopband Attenuation 150 dB 

2.6 Pin Descriptions 

Table 4 Digital filter characteristics 

PIN # Name I/O Description 

1 VDD1 Power 

2 VDD2 Power 

3 RESET 

4 MD_CS Input 

Digital Power - Digital core power supply, 

+3.3V. 

Digital Power - Digital core power supply, 

+3.3V. 

Input Reset – Active low. 

Control port Chip Select (SPI) – Internally 

pulled-up with a 10k resistor. 

5 MD_SCLK Input Control Port Clock - SPI port clock input 


Q5M-DS-110A 


6 MD_MOSI Input 


Serial Control Data Input (SPI) – MD_MOSI 

is the input data line for the control port 

interface. 

7 MD_MISO Output 

Serial Control Data Output (SPI) – 

MD_MISO is the ouput data from the control 

port interface. 

8 DGND1 Ground Ground for I/O and core logic. 

9 CLKIN Input 

10 DGND2 Ground Cut Pin 

Master Clock Input – Master clock input for 

module. Typically a crystal based source at 

24.5760MHz. 

11 FLAG0 Input Not used – Connect to GND. 

12 FLAG1 Input 

DSD Input – High indicates that the incoming 

audio is a 2 channels DSD audio stream, low 

for 2 channels PCM stream . 

13 FLAG2 Input Not used – Connect to GND. 

14 FLAG3 Input 

15 DETECT Input 

Data Valid – When low, the incoming audio 

data stream is valid and should be processed. 

When high, the incoming audio data stream is 

not valid and the output is muted. 

Reserved for Backwards Compatibility – 

Do not connect this pin. 


17 RX0_FSYNC Input 

18 RX0_BITCLK Input 

19 RX0_SDATA1 Input 

20 RX0_SDATA2 Input 

PCM Serial Audio Input Frame Sync – 

Frame sync clock for audio data on 

RX0_SDATA1 pin. Do not connect in DSD. 

Serial Audio Input bit Clock – PCM/DSD 

Serial bit clock for audio data on on 

RX0_SDATA1 pin. 

Serial Audio Data PCM / DSD Left – Stereo 

PCM audio data serial input pin. DSD left- 

channel audio data serial input pin. 

Serial Audio Data DSD Right – DSD rightchannel 

audio data serial input pin. 


22 TX1_FSYNC Output 

23 TX1_BITCLK Output 

24 TX1_SDATA1 Output 

Serial Audio Output Frame Sync – Frame 

sync clock for audio data on TX1_SDATA1 / 

TX1_SDATA2 pin. 

Serial Audio Output bit Clock – Serial bit 

clock for audio data on on TX1_SDATA1 / 

TX1_SDATA2 pin. 

Serial Audio Output Left / Stereo – 

Upsampled left mono channel PCM audio 

data serial output pin when configured for 

8xFS Upsampling. 

25 TX1_SDATA2 Output 

Serial Audio Output Right – Upsampled 

right channel PCM audio data serial output pin 

when configured for 8xFS Upsampling. 



Q5M-DS-110A 



27 TX0_FSYNC Output 

Serial Audio Output Frame Sync – Frame 

sync clock for audio data on TX0_SDATA1 

pin. 

28 TX0_BITCLK Output 

Serial Audio Output bit Clock – Serial bit 

clock for audio data on on TX0_SDATA1 pin. 

Serial Audio Output Stereo – Direct 

29 TX0_SDATA1 Output downsampled stereo channel PCM audio data 

serial output pin. 

30 TX0_SDATA2 Output Serial Audio Output Reserved– Reserved. 


32 INTREQ Output 

32 

Interrupt Request – Uses when event occurs 

(like unlock). 

Table 5 Pinout Descriptions. 

INTREQ 

DGND6 

TX0_SDATA2 

TX0_SDATA1 

TX0_BITCLK 

TX0_FSYNC 

DGND5 

TX1_SDATA2 

TX1_SDATA1 

TX1_BITCLK 

TX1_FSYNC 

DGND4 

RX0_SDATA2 

RX0_SDATA1 

RX0_BITCLK 

RX0_FSYNC 

Top down view 

17 

1 16 

VDD1 

VDD2 

RESET 

MD_CS 

MD_SCLK 

MD_MOSI 

MD_MISO 

DGND1 

CLKIN 

DGND2 

FLAG0 

FLAG1 

FLAG2 

FLAG3 

DETECT 

DGND3 

Figure 7 Pinout top down view 


Q5M-DS-110A 



3 Interfacing and Operation 

This chapter provides practical application information for hardware and systems engineers 

who will be designing the Q5 Module into their product. 

3.1 General Description 

The Q5 Module is a two-channel, asynchronous sample rate converter (ASRC) with input 

sampling frequencies from 32 to 192kHz, and outputs up to 384kHz being supported. Bestin-class 

dynamic range and THD+N are achieved by employing an innovative upsampling 

kernel known as Q5 with better than 144dB of image rejection. The digital filters provide 

for lower latency processing and a direct downsampling option allows for dual digital output 

ports driven at different sampling frequencies. 

The audio input port supports the I2S standard and the 2 channels 2.8224MHz DSD audio 

data formats for supporting virtually any standard audio source from CD, USB, HDMI or 

SACD. The output port supports the I2S standard and DSP audio data formats. Word 

lengths from 16 to 24bit are supported. Input ports are operated in Slave mode, deriving 

their word and bit clocks from external input devices. Output ports are operated in Master 

mode allowing the incoming data stream to be reclocked and synchronized around a single 

high quality master clock, referred to as DSS synchronization. In the Master mode of the 

output ports, the FSYNC and BITCLK clocks are derived from the system master clock 

CLKIN. 

The Q5 Module includes a four-wire SPI port, which is used to access on-chip control 

and status registers in Software mode. The SPI port facilitates interfacing to 

microprocessors or digital signal processors that support synchronous serial peripherals. In 

Hardware mode, dedicated control flags are provided for basic functions. These pins can 

be hard-wired or driven by logic or host control. In addition to the normal control interfaces, 

the Q5 Module provides a soft mute function in software mode as well as automatic input 

frequency sensing. 


Q5M-DS-110A 


3.2 Typical Connections 


The Q5 Module can be operated in software mode where the SPI port is used to 

configure the module. 

Figure 8 Typical connections in software mode. 

The Q5 Module can be operated in hardware mode whereby the SPI port is not needed 

to configure the module but rather the FLAG pins. In that mode, the MD_CS pin has to be 

left unconnected. 

Figure 9 Typical connections in hardware mode. 


Q5M-DS-110A 



3.3 Interfacing to Digital Audio Receivers and Transmitters 

The Q5 Module audio input and output ports are designed to interface to a variety of 

audio devices, including receivers and transmitters commonly used for AES/EBU and 

S/PDIF communications. Figure 10 illustrates interface between CS8416 receiver and the 

Q5 Module input port which works as Slave and the receiver as Master. 

Figure 10 Interfacing to a digital receiver. 

Figure 11 shows the interface between the Q5 output port and the DIT4192 transmitter 

input port whereby the Q5 Module works as Master and the transmitter as Slave. 

Figure 11 Interfacing to a digital transmitter. 


Q5M-DS-110A 



3.4 Interfacing to High Performance D/A Converters 

In addition to drive transmitters, the Q5 Module is designed specifically to drive high 

performance D/A converters. Thus the module is able to drive bother dual 384kHz 

compatible DACs and an external transmitter at the same time. Connection to dual DACs, 

configured in mono mode, and to the transmitter is given in Figure 12. In that case the Q5 

works as Master and the DACs / Transmitter as Slave. 

Figure 12 Interfacing with dual mono 384kHz D/A converters. 

3.5 Reference Master Clock 

The Q5 Module requires a master clock for operation. This clock must be supplied at the 

CLKIN input (pin 9). The Q5 Module can be clocked by an external crystal, a sine wave 

input, or a buffered, shaped clock derived from an external clock oscillator. 

The Q5 Module is designed to work with a single frequency. As a result, all the audio 

output sampling frequencies will be derived from a multiple of 48kHz. 

Parameter Typ Unit 

CLKIN frequency 24.5760 MHz 

Table 6 Reference master clock frequency 


Q5M-DS-110A 


3.6 Reset and Power On 

Note 


To reduce clock perturbations, a correct line adaptation is required 

on the CLKIN input. Dedicated clock lines, ending and serial 

resistors can help to minimize perturbations. 

The Q5 Module may be reset using the RESET input (pin 3). This latter has to be held 

low for a minimum of 450ns to guaranty a proper reset. Figure 13 shows the reset timing for 

the Q5 Module. 

Parameter Description Typ Unit 

Timing Requirements 

tCKIN Serial Clock High Period 40.7 ns 

tCKINL Serial Clock High Period 20.3 ns 

tCKINH Serial Clock High Period 20.3 ns 

tWRST Serial Clock Low Period (min) 450 ns 

Table 7 Reset timing requirements 

Figure 13 Reset timing requirements 

There is an internal power on reset, so the user should not need to force a reset sequence 

after power up in order to initialize the module. 

In Software mode, there is a 200ms delay after the RESET rising edge before attempting 

to write to the SPI port due to internal logic requirements. 

3.7 Audio Serial Ports - RX0 Input 

The RX0 audio input port is a four-wire synchronous serial interface working in slave mode. 

In PCM mode, the port use three signals, namely RX0_FSYNC (pin 17), RX0_BITCLK (pin 

18) and RX0_SDATA1 (pin 19). RX0_FSYNC provides the frame synchronization clock 

while RX0_DATA1 and RX0_BITCLK are used to respectively transfer the serial audio data 


Q5M-DS-110A 



and clock the serial data into the port. The latter supports sampling frequencies up to 

192kHz. The audio data word length may be up to 24bit and the audio data is always binary 

two’s complement with the MSB first. 

In DSD mode, the port uses three signals, namely RX0_BITCLK (pin 18), RX0_SDATA1 

(pin 19) and RX0_SDATA2 (pin 20) pins. RX0_BITCLK provides the DSD clock 

synchronization (2.8224MHz) while RX0_SDATA1 and RX0_SDATA2 are respectively the 

left and right channel data. 

Figure 14 illustrates the audio data stream of each mode. Table 8 and Table 9 give more 

information about clocks of each mode. 

In software mode, the Input Control Register (see § 4.2.1) allows to select the input audio 

data format mode. Two bit are used to choose the mode, namely FMT0 and FMT1. The 

configuration in the Input Control register is OR-ed with the DSD Input (see below for 

further detail on DSD Input). 

In hardware mode, it is the DSD Input pin (FLAG1) that allows the input audio data format 

mode to be configured. When DSD Input flag is high, the DSD mode is selected as 

opposed to low where the PCM mode is enabled. 

FSYNC 

BITCLK 

SDATA 

BITCLK 

SDATA1 

SDATA2 

I2S Data Format 16-24bits 

Left Channel 

MSB LSB 

DSD Data Format 1-bit 

Left Channel Data 

Right Channel Data 

Right Channel 

MSB LSB 

Figure 14 Input stereo data formats 

Parameter Description Min Max Unit 

FSYNC Frame Sync Clock 32 192 kHz 

BITCLK Serial bit Clock 2.048 12.288 MHz 

Table 8 Serial input clocks in PCM mode 


Q5M-DS-110A 


Parameter Description Value Unit 

FSYNC Frame Sync Clock Not used 

BITCLK Serial bit Clock 2.8224 MHz 

Table 9 Serial input clocks in DSD mode 

3.8 Audio Serial Ports - TX0 Output 


The TX0 audio output port is a three-wire synchronous serial interface working in master 

mode. TX0_SDATA1 (pin 29) output is the PCM downsampled serial data output. The 

TX0_BITCLK (pin 28) output operates at a rate of 64xFSYNC. The left/right word clock 

referred to as frame sync, TX0_FSYNC (pin 27) is also configured as output pin and it can 

be set to operate at rates of 1xFS, 2xFS or 4xFS (see § 4.2.2). 

The audio data word length may be up to 24bit. The audio data is always Binary Two’s 

Complement with the MSB first. Refer to Figure 15 TX0 output data formats for the output 

data formats. 

FSYNC 

BITCLK 

SDATA 

CLKIN Frequency 

I2S Data Format 16-24bits 

Left Channel 

MSB LSB 

Right Channel 

MSB LSB 

Figure 15 TX0 output data formats 

TX0 Output Frequency 

1xFS 2xFS 4xFS 

24.5760MHz 48 96 192 kHz 

Table 10 TX0 output frequency sampling vs CLKIN frequency 

Parameter Description Value 

FSYNC Frame Sync Clock 48/96/192kHz 

BITCLK Serial bit Clock 64xFSYNC 

Table 11 TX0 output clocks 

Unit 


Q5M-DS-110A 


3.9 Audio Serial Ports – TX1 Output 


The TX1 audio output port is a four-wire synchronous serial interface working in master 

mode. The TX1_SDATA1 (pin 24) and TX1_SDATA2 (pin 25) pins are the PCM upsampled 

serial data output. The TX1_BITCLK (pin 23) output operates at a rate of 32xFSYNC. The 

word clock TX1_FSYNC (pin 22) is also configured as output pin and it can be set to 

operate at rates of 8xFS (see § 4.2.2). 

The audio data word length may be up to 24bit. The audio data is always Binary Two’s 

Complement with the MSB first. Refer to Figure 16 for the output data formats. 

FSYNC 

BITCLK 

SDATA1 

SDATA2 

CLKIN Frequency 

DSP Data Format 16-24 bit 

Left Channel (word n) Left Channel (word n+1) 

MSB LSB MSB LSB 

Right Channel (word n) Right Channel (word n+1) 

MSB LSB MSB LSB 

Figure 16 TX1 output data format 

TX1 Output Frequency 

8xFS 

24.5760MHz 384 kHz 

Table 12 TX1 output frequency sampling vs CLKIN frequency 

Parameter Description Value 

FSYNC Frame Sync Clock 8xFS (384kHz) 

BITCLK Serial bit Clock 32xFSYNC 

Table 13 TX1 output clocks 

3.10 Data Resolution and Dither 

When using the serial audio input port in I²S mode all input data is treated as MSB aligned 

2’s complement. Any truncation that has been done prior to the Q5 Module to less than 

32bit should have been done using an appropriate dithering process. There is no dithering 

mechanism on the input side of the Q5 Module, so care must be taken to ensure that no 

truncation occurs. However, dithering is used internally inside the Q5 Upsampling algorithm 

where appropriate. 

The audio output TX0 can be set to 16, 20 or 24bit output word width. Dithering is applied 

and is automatically scaled to the selected output word length. The audio output on port 

TX1 is always set to 32 bit. 

Unit 


Q5M-DS-110A 


3.11 Incoming Sampling Rate and Locking 


When the Q5 Module processes the incoming audio data stream, it calculates the ratio 

between the input and output sample rates and uses this information to set up various 

internal parameters. In PCM input mode, the Q5 Module accepts standard sampling 

frequencies of 32, 44.1, 48, 88.4, 96, 176.4 and 192kHz with a +/- 3% deviation from the 

nominal value. Whereas in DSD input mode, the Q5 Module accepts standard sampling 

frequencies of 2.8224MHz. If a non standard input sampling frequency is found or the 

standard sampling rate deviates more than 3% percent from the nominal value the Q5 

Module will NOT process the incoming data and will be a status of unlocked. 

The Q5 Module can dynamically compensate for drift and fluctuations in the incoming 

input sampling frequency (FSIN) where the module will track the incoming sample rate and 

automatically adjust the sample rate conversion process in order to maintain the highest 

level of audio quality. 

In Software mode, Input Control Register (see §4.2.1) functions as status registers, which 

contains the input frequency sampling detected. The INTREQ pin reflects the lock state of 

the module (see § 3.16). If there is a change in the input FS the INTREQ signal goes low to 

indicate an unlock state until the Q5 Module reacquires a valid ratio. At this point, the 

INTREQ will transition high. 

3.12 Muting 

The TXx_SDATA1, TX1_SDATA2, TXx_BITCLK and TXx_FSYNC pins are all low (hard 

mute) when module is either in reset state or unlocked ( no audio source or Data_Valid = 

1). These pins become valid as soon as the Q5 Module gets locked. When the module is 

locked, TXx_SDATA1and TX1_SDATA2 pins can be set to all zero (soft mute), while 

TXx_BITCLK and TXx_FSYNC are still valid, through the configuration of the “Mute” bit in 

the SPI process control register (see § 4.2.3 ). As a result, in hardware mode, only the 

Data_Valid (FLAG3) pin can be used whereas in software mode, there are two ways to put 

the module in mute which are the Data_Valid pin or the “Mute” bit in the SPI register. 

3.13 Phase Inversion 

The Q5 Module includes a phase inversion function whereby the output data can be 

inverted compared with audio input signal. By default this function is disabled and can only 

be enable in software mode. The selected configuration can be changed through the LSB 

bit called PHI of the Process Control Register (see § 4.2.3). All other features of the module 

don’t affect this function. 

3.14 Direct Downsampling 

The Q5 Module features a direct downsampling function located between the Q5 

Upsampler and the Audio Serial port TX0. The audio Serial port TX1 is directly connected 

to the upsampler. The downsampling function allows the selection of the output audio 

sampling frequency at 1x FSOUT, 2x FSOUT or 4xFSOUT. This makes the direct 

downsampler suitable for application where the output format has to be I2S operating at 48, 

96 or 192kHz e.g. S/PDIF transmitter or stereo DAC. 

In Software mode, Output Control register (see § 4.2.2) allows the TX0 output sampling 

frequency to be configured. In Hardware mode FSOUT is fixed at 48kHz/ 16bit. 

3.15 Stereo DSD to PCM Conversion 

The Q5 Module includes a stereo DSD to PCM converter. This gives the possibility of 

connecting a DSD input stream on the RX0 input port and using this stream as main audio 

source. The selection of the DSD input format is done by setting FLAG1 pin in hardware 


Q5M-DS-110A 



mode (see § 5.3). In software mode, the FMT bit in Input control register (see § 4.2.1) 

allows to enable the DSD input format. 

As described in paragraph 3.7, the RX0 audio input port is a four-wire synchronous serial 

interface that is configured to operate in Slave Mode. The RX0_SDATA1 and 

RX0_SDATA2 lines are the serial audio data inputs for DSD left and right channels 

respectively. DSD data format is 1bit stream, therefore no frame synch is needed (caution: 

Do not connect RX0_FSYNC). The serial bit clock is 2.8224MHz. 

3.16 Interrupt Request / Unlock Detection 

The Q5 Module has an interrupt request pin used to inform external devices when an 

event has occurred in the module. Currently the functionality of this pin is not configurable 

and represents the lock condition of the module. Thus when the IRQ is high the module has 

locked to a valid input sampling frequency from the incoming audio stream. When low, the 

module has not been able to detect a valid input sampling frequency and is unlocked, 

consequently the outputs are hard muted. 

3.17 Data Valid Input 

The Q5 Module uses the Data_Valid (FLAG3) input pin to know whether it should attempt 

to synchronize with the incoming audio data stream. If the Data_Valid pin is high then the 

module will never attempt to lock and the outputs will be hard muted. If the Data_Valid pin 

is low then the module will attempt to find the input sampling frequency and process the 

audio data as long as they are valid. The INTREQ pin can be used to track the module 

state (lock / unlock). 

3.18 Serial Port Interface (SPI Port) 

The SPI port, which is disabled in hardware mode, is the interface used when the Q5 

Module operates in software mode. This port is used to access registers allowing the Q5 

Module to transmit information to the host device (referred as master) and to be configured 

for the desired operational mode and format. The operation of the SPI port may be 

completely asynchronous with respect to the audio stream rates. However, it is 

recommended to keep the port pins static if no operation is required. 

The SPI port is a four-wires serial interface where MD_CS (active low) is the module chip 

select signal, MD_SCLK is the control port bit clock (input into the module from the host 

device), MD_MOSI is the input data line from master and MD_MISO is the output data line 

to the master. Data is clocked in on the rising edge of MD_SCLK and clocked out on the 

falling edge. 

Table 14 SPI byte definitions for register read / write operations and Figure 17 SPI protocol 

for register read / write operations illustrate the operation of the SPI port as well as the 

protocol for register read and write operations. Figure 18 SPI port timing requirements 

shows the critical timing parameters for the SPI port interface, which are listed in Table 15 

SPI port timing requirements. 


Q5M-DS-110A 


SPI Write 

Register 

SPI Read 

Register 

Header Byte 

Data Byte 

MD_CS 

MD_SCLK 

MD_MOSI 

MD_MISO 

MD_MOSI 

MD_MISO 

MSB LSB 

0 0 0 RW 0 A2 A1 A0 

MSB LSB 

D7 D6 D5 D4 D3 D2 D1 D0 

Set MD_CS = 0 to write/read a single register location 

Header Byte Data Byte 

Header Byte 

Hi-Z 


Data Byte 

Hi-Z Hi-Z 

Set A2-0 to register address for read/write operation 

Set to 0 

Set to 0 for Read, Set to 1 for Write 

Set to 0 

Contains register data bits 

Figure 17 SPI protocol for register read / write operations 

Byte Name MSB bit6 bit5 bit4 bit3 bit2 bit1 LSB 

Header Byte 0 0 0 R/W 0 A2 A1 A0 

Data Byte D7 D6 D5 D4 D3 D2 D1 D0 

A2-A0 : Register address selection (See § 4.2 for SPI register address definition) 

R/W : 0 = Register Read / 1 = Register Write 

D0-D7 : Register data (See § 4.2 for SPI register data definition) 

Table 14 SPI byte definitions for register read / write operations 

Parameter Description Min Max Units 

Timing Requirements 

tSPICHS Serial Clock High Period 2tSCLK –1.5 

tSPICLS Serial Clock Low Period 2tSCLK –1.5 


Q5M-DS-110A 


tSPICLK Serial Clock Period 4tSCLK –1.5 

tHDS Last MD_SCLK Edge to MD_CS Not 

Asserted 

2tSCLK –1.5 

tSPITDS Sequential Transfer Delay 2tSCLK –1.5 

tSDSCI MD_CS Assertion to First MD_SCLK 

Edge 

tSSPID Data Input Valid to MD_SCLK Edge 

(Data Input Setup) 

tHSPID MD_SCLK Sampling Edge to Data 

Input Invalid 

Switching Characteristics 

2tSCLK –1.5 


1.6 ns 

1.6 ns 

tDSOE MD_CS Assertion to Data Out Active 0 8 ns 

tDSDHI MD_CS Deassertion to Data High 

Impedance 

tDDSPID MD_SCLK Edge to Data Out Valid 

(Data Out Delay) 

tHDSPID MD_SCLK Edge to Data Out Invalid 

(Data Out Hold) 

Table 15 SPI port timing requirements 

Figure 18 SPI port timing requirements 

0 8 ns 

0 10 ns 

0 10 ns 


Q5M-DS-110A 


Software Mode 

4 Software Mode 

This chapter provides the main information of the software mode including control and 

status register definition. Reset defaults are also shown for each register bit. 


The Q5 Module can work in software mode which requests the device to operate with a 

host system having an SPI port (see Figure 8). This mode allows the host system to 

configure or read information from the Q5 Module by accessing registers through the SPI 

port (see § 3.18 for further details on SPI operational port). The following chapters give 

details and bit definition of each registers as well as their default setting after reset. 

4.2 Module Registers Overview 

Register Data bit 

Addr Name D7 D6 D5 D4 D3 D2 D1 D0 

00 

01 

02 

Input Control 

Register 

Output Control 

Register 

Process Control 

Register 

0 0 0 XFS2 XFS1 XFS0 FMT1 FMT0 

DTH OWW1 OWW0 TX1 TX01 TX00 0 0 

0 0 0 0 0 0 MUTE PHI 

03 Reserved 0 0 0 0 0 0 0 0 

04 Reserved 0 0 0 0 0 0 0 0 

05 Reserved 0 0 0 0 0 0 0 0 

06 

Software Revision 

Register 

REV7 REV6 REV5 REV4 REV3 REV2 REV1 REV0 

07 Product ID Register ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 

Table 16: Overview of command registers 

4.2.1 Input Control Register 

Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 

00 Input Control 0 0 0 XFS2 XFS1 XFS0 FMT1 FMT0 

Read(R) / Write(W) R R R R R R R/W R/W 

Default 0 0 0 0 0 0 0 0 


FMT 1-0: Input Format 

00: I2S 

01: Reserved 

10: Reserved 

11: DSD 

Q5M-DS-110A 


Table 17 Input Control Register 

4.2.2 Output Control Register 

XFS2-0: Input Frequency Sampling 

000: Unlock 100: 88.2kHz 

001: 32kHz 101: 96kHz 

010: 44.1kHz 110: 176.4kHz 

011: 48kHz 111: 192kHz 

Invalid if Input Format is DSD. 

Software Mode 


01 Output Control DTH OWW1 OWW0 TX1 TX01 TX00 0 0 

Read(R) / Write(W) R/W R/W R/W R/W R/W R/W R R 

Default 0 0 0 0 0 1 0 0 

TX0 1-0: TX0 Output FS 

00: Reserved 

01: 1xFS 

10: 2xFS 

11: 4xFS 

TX1: TX1 Output FS 

0: 8xFS 

1: Reserved 

Table 18 Output Control Register 

4.2.3 Process Control Register 

OWW1-0:TX0 Output Word Width 

00: 16bit 

01: 20 bit 

10: 24bit 

11: Reserved 

DTH: TX0 Dithering 

0: Dithering OFF 

1: Dithering ON 


02 Process Control 0 0 0 0 0 0 MUTE PHI 

Read(R) / Write(W) R R R R R R R/W R/W 

Default 0 0 0 0 0 0 0 0 

PHI: Phase Inversion 

0: Phase Inversion OFF 

1: Phase Inversion ON 

MUTE: Mute 

0: Mute OFF 

1: Mute ON 

Table 19 Process Control Register 

4.2.4 Software Revision Register 


06 Software Revision REV7 REV6 REV5 REV4 REV3 REV2 REV1 REV0 

Read(R) / Write(W) R R R R R R R R 

Default - - - - - - - - 


REV7-3: Major revision REV3-0: Minor revision 

Q5M-DS-110A 


Table 20 Software Revision Register 

4.2.5 Product ID Register 

Software Mode 


07 Product ID ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 

Read(R) / Write(W) R R R R R R R R 

Default 0 0 0 0 0 1 0 1 

ID7-0: ID Code for the Q5 Module. Permanently set to 00000101. 

Table 21 Product ID Register 


Q5M-DS-110A 


Hardware Mode 

5 Hardware Mode 

This chapter provides practical application information for hardware and systems engineers 

who will be designing the Q5 Module into their product. 


The Q5 Module can work in hardware mode which allows the device to operate without a 

host system or serial communication on the SPI port. The device is considered in Hardware 

mode when the MD_CS pin is left unconnected or pulled up with a resistor (10 kΩ) to VDD. 

In this mode the module starts in a default configuration. However, the four FLAG pins 

remain valid. 

5.2 Default Configuration 

When the Q5 Module is released from reset, it starts in a default configuration which is 

the same for both Hardware and Software modes. Hereafter is listed the various default 

setting: 

Audio Serial Ports - RX0 Input: I2S format 

Audio Serial Ports - TX0 Output: DSP format, 8xFS, 24bit 

Audio Serial Ports – TX1 Output: I2S format, 1xFS, 16bit, Dithering disabled 

Phase Inversion: OFF 

Output Mute: OFF 

All other non configurable features are available the same way as explained in the above 

chapters. 

5.3 Function Selection 

Beyond the default setting, some FLAG pins are available to select other configurations. 

FLAG0 (pin 11): Not used 

FLAG1 (pin 12): DSD enable. Used to select the audio input stream. Low = 2 

channels PCM stream (I2S format). High = 2 channels DSD stream. For further 

details see § 3.7. 



FLAG3 (pin 14): Data Valid flag. Used to force the Q5 Module to remain 

unlocked and therefore muted. For further details see § 3.17. 


Q5M-DS-110A 


Performance Plots 

6 Performance Plots 

This chapter gives typical performance plots of the Q5 Module in a typical operating 

environment. 

6.1 Standard Measurement Conditions 

Measurements for all performance plots are taken under the following conditions, unless 

otherwise stated: 

VDD1 = VDD2 = 3.3V 

Q5 Module installed in Q5 Evaluation Board 

Serial input and output format 24bit I2S 

Local master clock selected at 24.5760MHz 

Measurement Bandwidth = 20 to (FSout/2)Hz 

Audio Precision AP2700 version 3.10 

FFT 4095K points 

6.2 FFT Plot, Sine wave, 0dBFS, 1kHz Performance Plots 

Measurements for all performance plots are taken under the standard conditions. 

Plot 1: FFT 0dBFS 1kHz PCM 32.0 - PCM 48.0 






Q5M-DS-110A 









Plot 11: FFT 0dBFS 1kHz DSD - PCM 96.0 

Q5M-DS-110A 







Q5M-DS-110A 


Note 


On all plots where the input is in DSD mode, a raised noise level 

can be observed in the high frequencies. This has nothing to do 

with the Q5 Module. It is due to the intrinsic properties of the 

DSD modulator technique. 

6.3 FFT Plot, Sine wave, -60dBFS, 1kHz Performance Plots 


Plot 15: FFT -60dBFS 1kHz PCM 44.1 - PCM 48.0 







Plot 21: FFT-60dBFS 1kHz PCM 192.0 - PCM 192.0 

Q5M-DS-110A 





Plot 24: FFT -60dBFS 1kHz DSD - PCM 48.0 



Q5M-DS-110A 



Plot 26: FFT-60dBFS 1kHz DSD - PCM 192.0 

Note 






Q5M-DS-110A 


6.4 FFT Plot, Sine wave, 0dBFS and -3dBFS, 20kHz 












Q5M-DS-110A 








Q5M-DS-110A 




Note 






Q5M-DS-110A 



6.5 FFT Plot, Sine wave, 0dBFS, 80kHz Performance Plots 




Q5M-DS-110A 



6.6 Linearity, 200Hz Tone, 0 -140dBFS input, Performance 

Plots 


Plot 40: LINEARITY 200Hz PCM 44.1 - PCM 48.0 








Q5M-DS-110A 






Q5M-DS-110A 


6.7 FFT Plot, IMD, 10 and 11kHz Performance Plots 


Plot 49: IMD -7dBFS 10kHz 11kHz PCM 44.1 - PCM 

48.0 


192.0 



96.0 


48.0 



192.0 

Plot 54: IMD -7dBFS 10kHz 11kHz PCM 192.0 - 

PCM 48.0 

Q5M-DS-110A 



Plot 55: IMD -7dBFS 10kHz 11kHz PCM 192.0 - 

PCM 192.0 


Q5M-DS-110A 


6.8 THD+N vs Input Amplitude 


Plot 56: THD+N vs AMPL 1kHz PCM 44.1 - PCM 

48.0 


192.0 



96.0 


48.0 



96.0 


48.0 


48.0 

Q5M-DS-110A 




192.0 


192.0 


96.0 


Q5M-DS-110A 


6.9 THD+N vs Input Frequency 


Plot 66: THD+N vs FREQ 0dBFS PCM 44.1 - PCM 

48.0 


192.0 



96.0 


48.0 


Plot 70: THD+N vs FREQ PCM 48.0 - PCM 96.0 



Q5M-DS-110A 







Q5M-DS-110A 


6.10 Passband Ripple 


Measurements for all performance plots should be taken under the standard conditions. 

Plot 76: Passband Ripple 0dBFs PCM 44.1 - PCM 

48.0 

Plot 77: Passband Ripple 0dBFs PCM 44.1 - PCM 

192.0 


Q5M-DS-110A 


Packaging and Dimensions 

7 Packaging and Dimensions 

This chapter provides the physical packaging dimensions for the Q5 Module. 

7.1 Package Dimensions Metric 

63.00 

15.00 

5.00 

2.55 

83.00 

76.00 

61.00 

Figure 19 Housing physical dimensions (metric). 

M3x10 

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