Combining High-Resolution Pulsed TIVA and ... - ASM International

ISTFA 2010
Proceedings from the 36th International Symposium for Testing and Failure Analysis
November 14–18, 2010, Addison, Texas, USA
Combining High-Resolution Pulsed TIVA and
Nanoprobing Techniques to Identify Drive
Strength Issues in Mixed-signal Circuits
Ravikumar VK 1 , Ho MY 1 , Goruganthu RR 2 , Phoa SL 1 , Narang V 1 , Chin JM 1
Advanced Micro Devices Singapore Pte Ltd 1 , 508 Chai Chee Lane, Singapore 469032,
Advanced Micro Devices, Inc. 2 , 5900 E Ben White Blvd, Austin TX 78741, USA
Phone: (65) 679698888 Fax: (65) 62339080 Email: venkat-krishnan.ravikumar@amd.com
Abstract - This paper uses an interesting case study to
highlight high-resolution pulsed thermal-induced voltage
alteration (TIVA) with solid immersion lens (SIL) as a
technique to isolate a temperature-sensitive failure in
mixed-signal circuitry, followed by circuit analysis and
nanoprobing to confirm a drive strength issue caused by a
process change.
I. INTRODUCTION
Fault isolation for failure analysis (FA) has become
increasingly challenging with technology scaling and devices
growing more sensitive to smaller defects and process changes.
This pushes the need for substantial improvements in
conventional FA techniques.
Thermal-Induced Voltage Alteration (TIVA) is a popular
fault isolation technique for detecting temperature-sensitive
defects [1]. The technique involves biasing the device under
test (DUT) with constant current and monitoring changes in
voltage. A 1340-nm near-infrared (NIR) laser is used to target
specific areas in DUT that cause localized heating and helps
isolate defects or thermally sensitive circuitries. Pulsed TIVA
is essentially similar to TIVA technique. The main
modification in pulsed TIVA is in using a pulsed laser with a
lock-in phase detection system, which improves signal-to-noise
ratio (SNR) and helps remove TIVA artifacts [2]. When
pulsed TIVA is coupled with SIL, it can result in highmagnification,
high-resolution imaging, resulting in increased
accuracy in signal detection [3].
The SIL used for this analysis is made of silicon and is set
to work at a super-hemispherical focus, giving a magnification
of around 240x when combined with a backing 20x lens. It has
an effective numerical aperture (NA) greater than 2.4, which
boosts the resolution of laser imaging significantly. To `use the
SIL effectively, the units are thinned until around 100 um of
silicon remains, then mirror polished with 10 um of tolerance.
Care is taken during polishing to ensure the sample preparation
requirements.
1
Copyright © 2010 ASM International®
All rights reserved
www.asminternational.org
After a site has been successfully isolated using nondestructive
fault isolation techniques, the DUT is de-processed
from the front side, layer by layer, and every metal layer is
thoroughly checked for anomalies. Once the top-most metal
layer of the circuitry of interest is reached, physical fault
isolation (PFI) techniques like AFM and Nanoprobing are
popularly used. PFI helps confirm the presence of the defect
electrically and isolate the defect to a much smaller area of
interest. This process is crucial for the identification and
characterization of the defect, which usually is the final step in
understanding the failure.
In this paper, we discuss a temperature-sensitive failure
case study that utilizes pulsed TIVA with SIL for fault
isolation and subsequent nanoprobing and circuit analysis to
detect a drive strength-related failure in mixed-signal circuitry.
II. FAULT ISOLATION
Failing Signature
The analysis is conducted on failing samples containing
mixed-signal circuitry with limited DFT access to the area
causing the failure.
Tests revealed the samples are temperature-sensitive and
passed more often at elevated temperature. Curve tracing (Fig.
1) showed the faulty signal (solid red) pulled to a high state
instead of remaining at a low state like the good signal (dotted
blue) when the system voltage VDD (pink dashed) is ramped.
Soft defect localization, the popular technique for isolating
temperature-sensitive defects, is rendered unusable because it
is limited in design for test (DFT) features to exercise the
failure continuously. Tests showed that the part is stuck in its
state unless the supply voltage is turned down and ramped
again.
TIVA Analysis
TIVA analysis is performed by biasing the supply and
monitoring the failing signal. The supply voltage is held close
to the voltage at which the failing signal latches into a high

instead of a low state. The analysis showed a strong
disturbance at specific mixed-signal circuitry (Fig. 2).
Fig.1: Curve tracing shows that the bad signal was abnormally
pulled high during power supply ramp.
2(a) 2(b)
Fig. 2(a): Conventional TIVA image; 2(b) is the overlay image.
Streaking makes it impossible to isolate the failing circuitry.
The high sensitivity of the circuit to laser effects caused
streaking, and a change of state in the TIVA image in Fig. 2
made it difficult to isolate the actual part of the circuitry that is
sensitive. To obtain a better isolation, pulsed TIVA (Fig. 3) is
used which showed improvements over conventional TIVA.
3(a) 3(b)
Fig. 3(a): Pulsed TIVA image; 3(b) is the overlay image.
Streaking is substantially reduced.
Using pulsed TIVA, the laser is pulsed and using phase
lock detection, the streaks are effectively reduced to enable
2
isolation of the actual circuits that are sensitive to laser
stimulation (Fig. 3). To improve the isolation further, the
supply voltages are tweaked and the bad signal is monitored
through an oscilloscope when pulsed TIVA is performed.
The laser power is also reduced substantially to cause
minimum artifacts. As seen in Fig. 4(a), the number of TIVA
sites decreased to one, which correlated well to the failing
signature. Fig. 4(b) is a snapshot while the laser scanned the
sensitive circuitry. A dip in the voltage is observed at the
location highlighted by pulsed TIVA.
However, the pulsed TIVA overlay image still pointed to
multiple instances in the area of interest that could potentially
cause the failure. The magnification is not high enough to
isolate the circuitry to a particular instance.
4(a) 4(b)
Fig. 4(a): Pulsed TIVA image with reduced laser power and
optimized supply; 4(b) is the oscilloscope monitor of signal.
The unit is further thinned for imaging using the SIL, which
provides a magnification improvement of a 2.5x in addition to
a 5x resolution improvement compared to the state-of-the-art
air-gap lens. When combining pulsed TIVA with SIL, a higher
resolution image and more accurate fault isolation results are
obtained (Fig. 5).
5(a) 5(b)
Fig. 5(a): Image of the pulsed TIVA with SIL overlay; 5(b) is
the overlay of pulsed TIVA on digitally zoomed and cropped 0.85-
NA 100x air-gap lens.

This is evident when comparing Fig. 5(b), a digitally zoomed
overlay image obtained using a 0.85-NA 100x NIR lens, to
Fig. 5(a), the overlay image obtained by using a SIL in superhemispherical
mode and a 20x NIR backing lens.
Circuit Analysis
The CAD navigation tool showed that the site highlighted
by pulsed TIVA with SIL pointed to a particular transistor. On
circuit analysis and layout tracing, it is unambiguous that the
TIVA signal came from an input to a level restorer circuit that
fed to the failing signal (Fig. 6).
Fig. 6: Block diagram of circuitry of interest. Circled transistor
T1 is highlighted by high-resolution pulsed TIVA.
Transistor T1, a PMOSFET, is the input of a level restorer
circuitry made up of two inverters: the larger D1, which feeds
forward, and the smaller D2, which helps to hold the state. A
wrong input from either a leaky or a slow PMOS T1 could
change the state of the restorer, causing the signal to flip and
the reported failure. The level restorer is powered by the
voltage supplies VDD1 and VDD2, which also supported the
observed failure.
III. Physical Failure Analysis
PFI and PFA approach
As mentioned earlier, with technology scaling of ICs, nonvisible
defects have become common phenomena in FA. On
top of this challenge, the electrical failure signature for many
of the failures is soft, as presented in this study. Therefore, the
utilization of non-destructive PFI is essential to indicate the
exact failing location before attempting PFA. This section
demonstrates the successful use of nanoprobing to reveal faults
in the level restorer. The theory of nanoprobing [4] has been
adequately described in the literature.
This study used a scanning electron microscope (SEM)based
nanoprobing system. This system provides the capability
of maneuvering the probe tips by nanometer range to land
exactly on top of the individual source, drain, and gate
tungsten contact (Fig. 7). The SEM provides a high-resolution
real-time image that facilitates locating the device and placing
3
the probe tips. The SEM is operated at 1 keV to ensure there is
no transistor degradation [5].
Based on the level restorer layout and information from
electrical fault isolation described in Section II, our first
approach was to perform layer-by-layer inspection using SEM.
This traditional PFA technique failed to reveal any obvious
anomalies from metal 4 down to contact level. This is not
surprising, since this is a temperature-sensitive failure (soft
failure).
Fig. 7: SEM image (right) showing three tungsten probes (black
arrows) landing on tungsten contacts of the NMOS transistor in the
inverter image on the left.
With the individual transistor isolated at contact level,
nanoprobing is the one of the best way to obtain full-transistor
electrical characterization. Families of current versus voltage
(I/V) curves are collected on multiple transistors on the good
and failing level restorer. Basic transistor parameters such as
threshold voltage (Vt), saturation drive current (Isat), and N/P
ratio can be extracted with ease. N/P ratio is the value of Nchannel
Isat divided by P-channel Isat. A higher N/P ratio means
the NMOS drive strength is higher than the PMOS drive
strength. Mixed-signal circuits need tight control of this ratio
since they operate in the analog domain of the IV curve.
Data analysis
There are five PMOS and five NMOS transistors in each
level restorer identified as the failing circuit during fault
isolation, four of those inverters in parallel and grouped into
D1 in Fig. 6 while the last one, D2, is used to hold the state of
the restorer like a latch.
Fig. 8(a) shows the one of the five PMOS IDSAT curves
obtained from the failing and good level restorer with the gate
voltage set at -1V. Almost 20% deviation is observed in the
drive current of the good and bad PMOS transistor, with the
bad circuitry showing lower drive strength. Fig. 8(b) shows the
NMOS IDSAT curve with the gate voltage at 1V. The NMOS
transistor does not show a significant deviation between the
good and bad curves.

Fig. 8(a): PMOS transistor in the failing site exhibits 20-30%
lower drive current (see comparison red line) compared to the good
level restorer.
Fig. 8(b): NMOS transistor in the failing site shows comparable
drive current compared to the good level restorer.
This measurement is repeated in the other four PMOS and
NMOS transistors, which showed a similar response of lower
PMOS drive strength. It is therefore obvious that the failing
area exhibited weak PMOS I/V characteristics with acceptable
NMOS characteristics. This, in turn, drove the N/P ratio of the
bad transistors significantly higher than the good transistors.
To validate this result, a similar experiment is conducted on a
second bad DUT (not shown here), and the results are found to
be repeatable.
Defect Identification
After the exact failing transistor is successfully identified
using nanoprobing, defect identification techniques like
focused ion beam (FIB) and scanning tunneling electron
microscopy (STEM) are used, but revealed no physical
defects. A transmission electron microscopy (TEM) sample is
then prepared to understand the low drive current behavior.
The result of TEM, however, revealed no defects, and
construction analysis did not show any difference between
good and bad transistors. While TEM is a proven powerful
tool in FA [6], it has some shortcomings, like the difficulty of
quantifying the extent of implantation.
4
With the feedback of drive strength non-conformance and
the lack of physical defects, the fabrication facility had
increased confidence in its identification of the failure
mechanism, and it corrected the process to increase the drive
strength of the PMOS transistor, resulting in a 100% fix.
IV. Conclusion
This paper discussed the creative use of pulsed TIVA with
SIL to obtain increased sensitivity and resolution during static
fault isolation. This is the first report of this technique being
applied to mixed-signal circuitry to detect drive strength- and
N-P ratio-related failure mechanisms. Fig. 5 clearly highlight
of the capabilities of this technique.
A fault isolation image that resulted from the combination
of pulsed TIVA with SIL resulted in faster identification of the
root cause and, therefore, its fix. The paper also highlights the
importance of nanoprobing to identify non-visual defects and
characterize the electrical performance of circuits.
V. References
[1] Phang, JCH et al., “A Review of Laser Induced
Techniques for Microelectronic Failure Analysis,” Proc
Int Symp Physical & Failure Analysis of Integrated
Circuits (IPFA 2004), 5-8 Jul 04, pp. 255-261, 2004.
[2] Phang, JCH et al., "Resolution and Sensitivity
Enhancements of Scanning Optical Microscopy
Techniques for Integrated Circuit Failure Analysis,” Int
Symp Physical and Failure Analysis of Integrated Circuits
(IPFA 2009), 6-10 Jul 09, pp. 11-18, 2009.
[3] Quah, ACT et al., “Combining Refractive Solid
Immersion Lens and Pulsed Laser Induced Techniques for
Effective Defect Localization on Microprocessors,” Proc
International Symposium for Testing & Failure Analysis
2008, pp. 402-406.
[4] Faure, D and Waggoner, CA, “A New Sub-micron
Probing Technique for Failure Analysis in Integrated
Circuits,” ESREF 2002.
[5] Mizuno, T et al., “Maximum Permissible EB Acceleration
Voltage for SEM-Based Inspection before Electrical
Characterization of Advanced MOS,” IEEE 45th Annual
International Reliability 2007.
[6] Williams, DB and Carter, CB, Transmission Electron
Microscopy: A Textbook for Materials Science, Vols. 1-4
(Plenum Press, New York, 1996).