A Study of the ITU-T G.729 Speech Coding Algorithm ...

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MASTER THESIS
5 Overview of the Flexible ASIC Concept
5.1 Introduction
Datum - Date Rev Dokumentnr - Document no.
04-09-28 PA1
Flexible ASIC, a System-on-Chip architecture, enables the implementation of digital signal
processing functions and is a concept developed for the design of small, cost efficient and
high performance solutions whose essential characteristic is a high degree of reprogramming
flexibility. The integration of DSP cores on a single ASIC chip forms hereby the basis
of the flexible ASIC.
In order to guarantee an even higher degree of flexibility, a library of processor core
building blocks, from which a customized processor core can be assembled, exists. A set
of DSP software development tools, which enable the programming of the processor, are
supported by the Flexible ASIC concept. The concept, which is promoted by the Ericsson
Technology Board, has been used in real projects since 1996 [9].
5.2 Background
Modern digital communication systems place high demands on digital signal processing.
Today, a system’s manufacturing cost and power dissipation largely stem from different
Digital Signal Processors (DSPs), which explains why optimizing both, the software and
hardware implementation of digital signal processing, has become increasingly important.
Additional aspects which have to be considered in the decision of a suitable DSP are, for
instance, the DSP instruction set, clock frequency, chip size, the memory capacity of data
and program memories, the respective software development tools as well as the efficiency
of the C-compiler, in the case algorithms are intended to be written in C.
However, even if a DSP is clocked at a high frequency, it does not necessarily perform
a particular algorithm faster compared to a DSP with a lower clock frequency. In some
cases, the instruction set in the slower DSP might suit the algorithm, which is to be implemented,
better. Since an increase in the performance is related with increases in the
number of instructions which can be executed within a clock cycle, the parallelism of the
DSP represents an essential aspect as well.
The most essential algorithms require the direct implementation in dedicated logic, as
a consequence of speed requirements, in a Field Programmable Gate Array (FPGA) or
an Application Specific Integrated Circuit (ASIC). Since the FPGA offers the possibility of
being reprogrammed in case the functionality of the algorithm has to be changed, it guarantees
a high degree of flexibility. However, the large costs and size, essentially eliminate the
use of FPGAs. In contrast to the FPGA, ASIC delivers generally very good performance
as well as a small circuit area. An ASIC offers however no flexibility since its functionality
cannot be changed once it is manufactured [19].
5.3 ASIC and DSP
Today, the majority of projects requires the possibility to change and update the functionality
of a signal processing system. However, if DSPs would be used only, performance
requirements could not be met. One solution would be to combine the advantages of an
ASIC with the flexibility of the DSP. Figure 20 depicts a comparison of different technolo-
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