A Study of the ITU-T G.729 Speech Coding Algorithm ...

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MASTER THESIS
Figure 21: Flexible ASIC layout
Datum - Date Rev Dokumentnr - Document no.
04-09-28 PA1
ASIC are guaranteed through the use of a small internal Random Access Memory (RAM)
in each DSP core as well as a common external RAM for several DSP cores as a group.
Interfaces of the specific applications are custom made and implemented with the other
ASIC architecture.
A common external memory utilizes the issue that programs often consist of split loops.
A higher level of efficiency regarding memory usage as well as a minimized silicon area
used for memory, is achieved if the common program memory contains the main program
and the internal program memory of an assigned DSP code, contains a copy of a loop
code.
For the case that every DSP core contains a copy of the program, a larger internal
memory would be required and therefore a larger total memory. In addition, since memory
generally requires a large amount of silicon area compared to other logic contained in a
DSP core, the silicon area would increase as well.
As part of the Flexible ASIC project, different DSP-cores have been developed. Figure
22 depicts the general layout of a Flexible ASIC DSP core [19]. The PCU (Program
Control Unit), the basic block, dispatches program instructions, received from the LPM
(Local Program Memory), to the appropriate CU (Computational Unit). The LDM (Local
Data Memory) is connected through the DAAU (Data Address Arithmetic Unit) and provides
an address interface to the LDM which in turn is divided into memory banks of equal
size (1024x16 bit). Also, the architecture enables simultaneous access from two different
memory banks. The CDMIF (Common Data Memory Interface) provides a communication
interface to the CDM (Common Data Memory) which is shared between several cores. Additionally,
the cores are characterized by IRQ (Interrupt Requests) and timer functionality.
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