Smart Power IC-Entwicklung für die Automobiltechnik - HTL Wien 10

Seminar 

Elektronik im KFZ 

Spital/Pyhrn 12/07 

Seite 1 H.Zitta / Smart Power IC-Entwicklung 

Seminar 



Smart Power IC- Entwicklung 

für die Automobiltechnik 

Heinz Zitta 

Infineon Technologies Austria 

Automotive Power 

heinz.zitta@infineon.com 

Inhalt 

Einleitung - Einsatz integrierter Schaltungen im Automobil 

Halbleiter Technologien für Smart Power Schaltungen 

Besondere Anforderungen beim Betrieb im Automobil 

Schaltungstechnik-Beispiele für Smart Power Switches 

Anforderungen an Gehäuse/Montagetechnik - Beispiele 

Systemintegration von Smart Power Produkten 

Zusammenfassung 


• 1


Trends 

Automotive Power - Einsatzgebiete 

Powertrain – „Antriebsstrang“ 

Safety 

o Motorsteuerung, Engine Management 

o Einspritzventile, Zü ndung 

o Getriebesteuerung 

o ABS, ASR, ESP (Elektron. Stabilitäts-Progr.) 

o Airbag 

„B o d y“ – Alles, was in der Karosserie ist 

o Lampenschalter (hoher „inrush-current “) 

o Fensterheber, Zentralverrieg. (T ü rmodul) 

o Relais, Signallampen, LED-Ansteuerung 

• Ersatz aller elektromechanischen durch elektronische Komponenten 

• “ Silicon instead of heatsink” Niedrige Rds- on sparen Verlustleistung 

• Verstärkter Einsatz von Bus- Systemen, Car - Communication 

• H öherer Komfort erhö ht prozentuellen Elektronik- Anteil im Auto 

• “ X by wire” Ersatz von Mechanik, Hydraulik durch Elektroantrieb 

• Ü bergang zu 42V Bordnetz? (war geplant, kommt wohl nicht mehr ...) 

• System on Chip 

• Selbsttest, Diagnosesysteme 

• Treibstoffverbrauchsreduktion (z.B. Benzin Direkteinspritzung) 

• Hohe Anforderung an Zuverlässigkeit f ür elektron. Komponenten 

• Abkehr von reinen kundenspezifischen Lös u n g e n : 

• Custom - specific 

• - > ASIC (Application Specific IC) 

• -> ASSP (Application Specific Standard Product) 

• - > Standard ? 


• 2

Seminar 




Halbleiter Technologien für Smart Power Schaltungen 


Schaltungstechnik-Beispiele f ü r Smart Power Switches 

Anforderungen an Gehä use/Montagetechnik - Beispiele 




Technologie Evolution: Shrinking Possibility Limited for Power Technologies 

W.Ziebert, „Technical and Economical Trends in Microelectronic “. ESSCIRC 2007. München 


• 3

ts 1 

n-substrate 

n-well 

ts 2 

p-substrat 

substrat 

Smart Power Technologien 

Klassifizierung entsprechend der angewandten Isolation: 

• Selbst-Isolation 

Diese Isolationstechnik ist von den CMOS Prozessen her bekannt. Es ist die 

einfachste Art, benachbarte Bauteile werden nur durch Anlegen vo n 

S p a n n u n g e n e n t s p r e c h e n d e r P o l a r i t ä t im Vergleich zum Substratpotential oder 

v o m W a n n e n -Potential voneinander isoliert. 

Smart Power Selbstisolations Prozesse verwenden n-Substrat u. p-W a n n e n . 

• Sperrschicht Isolation (Junction -Isolation) 

Diese Art der Isolation ist von bipolaren Prozessen her bekannt. Auf ein p- 

Substrat wird eine n-dotierte Epischicht aufgebracht. Isolation der Bauteile 

innerhalb der Epischicht durch zusä tzliche, in Sperrschicht betriebene p- 

Diffusionen. Diese Art von Smart Power Prozessen benö tigt einen komplexeren 

Prozessaufbau (=hö her Maskenanzahl) als der Selbstisolations-Prozess, aber ist 

vielseitiger im Hinblick auf m ögliche Bauteile, einschließ l i c h b i p o l a r e r 

Komponenten. (Infineon: SPT, allgemein bekannt als BCD-P rozess) 

• Dielelektrische Isolation (SOI Silicon-o n -Insulator) 

E i n e „echte“ Isolation mittels Oxid. 

Beste Performance hinsichtlich Parasiten und Hochvolt -Festigkeit, jedoch am 

teuersten und daher derzeit nicht Mainstream f ü r automotive Produkte. 

Thermisches Verhalten: Si-Oxid ist ein deutlich schlechterer W ärmeleiter als Si. 


+Vdd 

n-well 

Self-Isolation 

device 1 device 2 

p p p p 

n- substrate 

It is the simplest solution and is used in each MOS process. Iso lation of 

neighbouring components is only done by applying the right voltages to the 

components in respect to the substrat or well connection. The sm art power self - 

isolation processes are based on a n-substrate/p-well CMOS approach. 

Apply a positive voltage to the n-substrate to allow isolation of p-type devices. 


• 4

Gnd (-) 

p 

iso 

p 

n- Epi 

Junction-Isolation 


p - substrat 

p 

This kind of isolation is known from bipolar processes. A n-type epitaxial 

layer is grown on a p-type substrat. The components are inside the epi - 

layer and they are isolated by revers biased junctions realized by pdiffusions. 

This kind of smart power process needs a higher mask count as 

the self isolation approach, but is more flexible in the availab le devices. 

Substrate must be connected to GND or most negative voltage to 

enable the isolation. 


n 

p 


substrat 

Seite 10 H.Zitta / Smart Power IC-Entwicklung 

p 

Dielectric-Isolation 

p 

n 

n 

n 

n 

p 

oxid 

isolation 

This isolation is r e a l l y d o n e with an insulator (oxid ). 

It would give the best results in avoiding parasitics and f o r high voltage capability. 

For power circuits you would have to calculate, that the thermal conductivity o f 

oxid is v e r y l o w compared to silicon. Due to the fabrication process it is the m o s t 

expensive technology and therefore not (yet) the mainstream f o r smart power 

circuits. 

• 5

n 

p 


p - substrate 

Partial Dielectric-Isolation 

Deep Trench Isolation (DTI) 

A oxid isolation o n l y to separate the n- wells is easier to realize than a f u l l dielectric 

isolation, it could be done with deep trench etching . The advantage is a smaller 

chip-size because o f less area wasted f o r the well- isolation compared to the 

junction-isolation. 

Against substrate there is no advantage related to parasitics („reverse current 

problem “) 


S G 

D 

Gate 

p- channel n- channel 

D r a i n 

Source 

S G 

D S G 

D 

B 

p + 

n- Epi 

n+ Substrat 

p- 

D 

n + 

G Bulk 

S 

p 

n 

n 

CMOS Self-Isolation 

oxid 

isolation 


+ 

s u b s t r a t 

n- channel 

p- channel 

Correct biasing of all parasitic diodes 

is necessary to maintain self - isolation 

• 6

MOS: expand voltage capability 

low voltage 

MOS 

p- channel 

high voltage 

MOS 

S G 

D 

S G 

D 

S G 

D 

p + L p + 

L 

p + p- 

p + 

n 

Higher voltage capability requires longer channels for lateral M OS Devices 

- > increasing chip- area, increasing Rds- on 

introduce drain extension as a better solution: 

a h i g h- ohmic (low doped) diffusion of same type (n or p) as device typ ( n o r p - channel) 

increase gateoxid thickness near drain (allow high drain- source voltage) 


LDD High Voltage Device: Electric Field 

VS=0V VG=+5V VD=+50V 

drain extension 

Lightly doped drain 

extension area 

reduces the electric 

field strength in the 

channel region. 

Also called“RESURF“ 

device 

„reduced surface 

field“ 

source: 

Balan, High voltage devices and 

circuits in standard CMOS 

technologies 


• 7

low voltage 

CMOS 

p- Kanal n- Kanal 

S 

G 

D 

B 

S G 

D 

p + 

CMOS: Low Voltage and High Voltage Devices 

can be on same chip 

p- 

n + 

n- Epi 

n+ Substrat 

p- Kanal 

S G 

D 

p + p- 

high voltage 

MOS 


p + 

n- Kanal 

S G 

D 

p- 

n + n- 

Insert a lightly doped drain diffusion for 

higher voltage capability (drain extension) 

• p- f o r P -channel device 

• n- f o r N -channel device Double diffusion MOS = DMOS 

(lateral DMOS) 

S 

p- n + p + 

n- epi 

n+ substrate 

G 

Current flow 

D r a i n 

Vertical DMOS 


n + 

Use the epi- l a y e r 

a s d r a i n e x t e n s i o n . 

The vertical DMOS is born! 

d Epi doping and thickness can be 

adjusted to the required 

breakdown voltage vs. Rds-on 

thumb- r u l e : d = 1 u m e a c h 1 0 V 

D r a i n = S u b s t r a t + 

Gate 

Source 

• 8

p + 

Gate 

low voltage 

CMOS 


p- Kanal 

n- Kanal 

S G 

D 

B 

S G 

D 

S G 

D 

S G 

D 

S 

G 

D r a i n 

Source 

Vertical SMART Power Technologie 

CMOSDMOS, SMART = Selfisolation 

n + 

p- 

n- Epi 

n+ Substrat 

D 

G Bulk 

S 

p + p- 

high voltage 

MOS 

p + 

p- 

n + n- 

Vertical D M O S 

Power Transistor 

+ Vbatt 

D r a i n 

D r a i n = S u b s t r a t + 


n + 

p- n + p + 

Gate 

Highside Switch: Vertical SMART Technology 

Source 

DMOS 

2 x 90 mOhm 

12 A / 60 V 

Analog MOS 

Diagnostic 

Protection 


• 9

p + 

n- epi- l a y e r 

p Substrat 

All components are in 

n- epi- w e l l s , i s o l a t e d b y 

p + i s o l a t i o n d i f f u s i o n s 

Bipolar Technology 

Junction Isolation 

Bipolar 

npn- T r a n s i s t o r 

C B 

E 

p + 

n + 

p 

n- 

n + 

p+ 

Isolation s i n k e r 

buried l a y e r 

C B 

E 

pnp- T r a n s i s t o r ( l a t e r a l ) 

B C E 

n- p p+ 

C E 


B 

CMOS 


Bipolar 

npn- T r a n s i s t o r 

DMOS 

Vertical " U p d r a i n " 

Power Transistor 

S G 

D 

B 

S G 

D 

C 

B 

E D 

S 

G 

p + 

at GND level ( - ) 

„Updrain“-Smart Power Technologie 

BIPOLARCMOSDMOS, SPT = Junction Isolation 

n + 

p Substrat 

p- 

n- Epi 

S 

p -K a n a l 

D 

D 

n -K a n a l 

S 

n + 

p 

p + n- 

n + 

p + 

Isolation s i n k e r 

buried l a y e r 

B 


C 

E 

B 

p- n + p + 

n + 

Drain: no restrictions 

Gate 

Source 

p + 

• 10

Source: Smart Power Ics, Technologies and Applications, B. Murari et al (eds), Springer Verlag 1995, ISBN 3-540-60332-8 


current 

flow 

symbol 

DMOS Cross-section 

IGBT Insulated Gate Bipolar Transistor 

electrical 

subcircuit 

Isolation is done with two 

implantations: 

bottom isolation implanted 

before growing the 

epitaxial layer, top isolation 

implanted from surface 

included parasitics 


• 11

IGBT Insulated Gate Bipolar Transistor 

The IGBT combines the advantage of an easy to control MOS gate structure 

with the low conduction loss of a bipolar transistor. 

Although the symbol shows a npn-transistor, controlled by a gate, in reality it 

is better understood as a pnp-transistor, which base current is controlled by a 

n-channel MOS transistor. Therefore voltage drop in foreward direction is 

always higher than a bipolar diode. 

If we look at included parasitics we will find a thyristor structure, formed from 

npn and pnp device. Under normal operation conditions this thyristor is not 

activated. 

Resulting we can define the IGBT as a device between power-MOS and 

thyristor. 

The Non-Punch-Through (NPT) IGBT has a low doped n- region, designed to 

support the whole blocking voltage of the device. The Punch-Through (PT) 

concept uses an n+ -doped layer which seperates the active region of the 

device from the thick backside p+ emitter. 

A drawback of the IGBT is its lack of reverse blocking capabilit y (compared to 

bipolar) or the absence of a body diode (compared to MOS). 


Compare Characteristics: MOS-FET / IGBT 

SIPMOS BUZ 342 

V DS I D RDS( on) 

50 V 60 A 0,01 Ohm 

IGBT BUP 604 

V CE I C V CE( sat) 

600 V 80 A 2V (@50A) 

T j=25°C 


• 12

Seminar 



R on · A (W*mm 2 ) 

Use the best suited technology for cost 

effective automotive power products 

discrete power transistor t o s y s t e m - i n t e g r a t i o n 

MOSFET 

/IGBT 

TEMPFET 

protected 

PROFET 

fully protected 

Smart 

Power IC’s 

Multi-Channel Switches 

Bridges 

Driver-IC‘s 

Voltage Regulators 

Power 

System IC’s 

Smart Power 

System Integration: 

ABS / AIRBAG 

Powertrain 

Embedded 

Power Products 

single package 

smart power and 

controller integration 

low-side-Switch 

high-side-Switch 

Overload 

Integrated charge 

protection 

pump 

CCAN/LIN Transceiver 

Thermal shutdown 

Overload protectionDC/DC 

Converter 

Current limitation smart IGBT 

HITFET 

Short-circuit 

C u r r e n t limitation 

protection 

Short-circuit 

protection 

Overvoltage 

Overvoltage 

protection 

protection 

Open load detection 

O p e n load 

Diagnostic feedback 

detection 

Multi-Channel 

SFET/IGBT Smart&SFET Smart BIPOLAR, SPT,IGBT SPT / CMOS 


0,5 

0,4 

0,3 

0,2 

0,1 

0 

1990 1995 2000 

lithography 

R-on Reduction of Smart Power Technologies 

vertical updrain 

60 V 

90 V 

2.0 µm 1.2 µm 

0.5 µm 

0.35 µm 


2005 

• 13


P o w e r m e t a l 

(Aluminum) 

Source 

C h a n n e l 

Poly(Gate) 

from Lateral to Trench-DMOS 

p- 

for further R-on*Area reduction 

Lateral High-Voltage MOS 

S D 

n + n- n + 

lateral 

channel 

lateral 

drift region 

Vertical Trench DMOS 

Power-Transistor in Trench-Technik 

Drain 

S 

D 

G 

vertical 

channel 

vertical 

drift region 


• 14

Self - Isolation 

Vertical Smart 

Junction Isolation 

BCD, SPT 

Possible Power Output Configurations 

With Integrated Power Technologies 

High-Side 

Switch 

+ V s 

++ 

Low-Side 

Switch 

1 channel + 

multi- ch. - 

Half- 

Bridge 

H - Bridge 

+ ++ + 

+ 


Four-f old smart power low-side switch in SPT-T e c h n o l o g y 

rated max. 3 A , 60 V each channel 

Analog: 

Driver, 

diagnostic and 

Protection 

DMOS 

It consists of the power DMOS, logic CMOS circuits and analog circuit 

realized in SPT-Technology (TLE 6220) 


CMOS Logic 

- 

- 

• 15

Seminar 




Halbleiter Technologien f ü r Smart Power Schaltungen 








• Hoher Spannungsbereich 5V .. 60 V (90V) 

• Hoher Temperaturbereich 

• - 40 °C .. + 150 °C voll getestet, jedes Device 

• 150 °C .. + 200 °C volle Funktion 

• > 200°C bis 300°C bei Überlast, kontrolliertes Abschalten 

• St ö runempfindlichkeit 

• Übersprechen (Kabelbä u m e ) 

• EMV Einstrahlung (Susceptibility) 

• EMV Abstrahlung (Emission) 

• Hohe Qualitätsanforderungen 

• Zuverlä ssigkeit (Engine-Management) 

• Sicherheitsrelevanz (ABS, Airbag) 


• 16

Operating voltages in automotive applications ... 

42V Power Net 

12V 5 

7 18 

18 

30 nominal voltage 50 

12 24 36 48 60 

42 

Coresponding 

Wafer technology limit 


58 

60 75 

75 

75 90 

… is against the trend of downsizing micro-controller core voltages 

‡0,5µm

V 

12V 

-100V 

Negative Voltage Transients can cause Reverse Current 

10% 

90% 

200ms 

Seminar 




Vbat 

+ 12 .. 60V 

Logic 

IN 

Logic 

OUT 

V C C 

+ 5 V 




Schaltungstechnik-Beispiele für Smart Power Switches 




R 1 

R 2 

I1 

IC 

Q1 

I2 

M1 M2 

Block diagram of a Smart Power Switch 

Prestabilisation 

Voltage Regulator 

I/O Buf 

Digital 

Logic 

Parallel/ 

Seriell 

Interface 

S P I 

C A N -Bus 

. . . . . 

Reference-Voltage 

& B i a s -Current 

Generation 

Internal S u p p l y 

Vref1 

Vref1 

Iref1 

Iref1 

Diagnostic & Protection 

Overlaod 

Overcurrent 

Overtemperature 

Open Load 

Gate Driver 

Slewrate - 

Control 


M3 


DMOS 

• 19

Seminar 



Examples of Analog Smart Power Circuit Blocks 

Reference Voltage & Current Generation 

Bipolar transistor characteristic 

Bandgap reference circuit 

Diagnostic & Protection Circuits 

Temperature sensors 

Current measurement 

Overvoltage protection 

Open load detection 

Gate Driver & Slew-rate Control 

Low side 

High side 


Voltage Reference: Bandgap Circuits 

Vref 


• 20

What characteristic can be used to generate a reference voltage? 

Vbe 

Bipolar MOS 

Base-emitter-voltage Vbe: 

depends on temperature, but is not 

sensitive to process variation. 

Bipolar device is the key 

component for accurate 

voltage reference circuits 

Vgs 

Gate-source-voltage Vgs: 

Depends strong on process variation 

MOS device based voltage 

reference circuits will not 

achieve high accuracy 


I C 

1 mA 

100 µ A 

Characteristic of bipolar transistor Ic = f (Vbe) 

0 , 2 0 , 4 0 , 6 

0 , 8 

I 

C 

V BE ⎛ ⎞ 

⎜ Vt = I ⋅ ⎟ 

S ⎜ 

e −1 

⎟ 

⎝ ⎠ 

log(I C) 

linear scale logarithmic scale 

1 mA 


U BE [V] 

10 µ A 

1 µ A 

I S 

k T 

Vt = mV C 

q 

⋅ 

≈ 26 [ 25° 

] 

0 , 2 0 , 4 0 , 6 

0 , 8 

U BE [V] 


• 21

U BE 

1,2 

1,0 

0,8 

0,6 

0,4 

0,2 

extended temp.range 

Bipolar Transistor: V BE = f (T) 

Temperature behaviour approx. - 2mV/K 

IC=100µA 

IC=10µ A 

0 K 

- 273 C 

300 K 400 K 

Normal operating range for integrated circuits 

in a u t o m o t i v e applications 

-40 C 27 C 

150 175C 


log(Ic) 

1 mA 


10 µ A 

1 µ A 

I S 

Calculation of Delta- Vbe 

0 , 2 0 , 4 0 , 6 

0 , 8 

Ic1 

Ic2 

ΔVBE 

U BE [V] 

absolute value of Vbe depends on transistor parameter Is, 

delta Vbe is independent of individual transistor parameter 

V BE ⎛ ⎞ 

⎜ Vt = I ⋅ ⎟ 

S ⎜ 

e −1 

⎟ 

⎝ ⎠ 


I 

V 

C 

BE 

ΔV 

⎛ I 

= ln 

⎜ 

⎝ I 

BE 

C 

S 

⎛ I 

= ln 

⎜ 

⎝ I 

⎞ 

⎟ ⋅Vt 

⎠ 

C 1 

C 2 

⎞ 

⎟ ⋅Vt 

⎠ 

T 

k T 

Vt = mV C 

q 

⋅ 

≈ 26 [ 25° 

] 

−23 

k = 1, 38⋅10 J/ K 

−19 

q = 1, 602⋅10 As 

T [ ° C ] T [ K ] VT [mV] 

- 4 0 2 3 3 20,1 

2 5 2 9 8 25,7 

1 0 0 3 7 3 32,1 

1 5 0 4 2 3 36,4 

2 0 0 4 7 3 40,7 

• 22

V REF 

Temperature- compensation of Vbe voltage 

Vbe 

Δ Vbe 

T 

T 

25 C 150 C 


-40 C 

Vref = const. 

The negative temperature dependence of Vbe can be compensated 

by the positive temperature dependence of delta-Vbe 

V BE2 

V BE1 

V R1 

V R2 

Temperature-constant Reference Voltage 

“B andgap-Reference” 

Q1 

n : 1 Q2 

R1 

R2 

+Vdd 

Q3 Q4 

I1 I2 C1 

Q5 

R3 

R4 


V REF 

1,2 

0,6 

Vbe 

Δ Vbe 

V REF 

-40 C 

25 C 

T 

Vbe 

Δ 

V BE2 

V R2 

Vbe 

125 C 

T 

T 

T 

• 23

Calculation of b a n d g a p reference circuit 

Assumption: I1 =I2, this i s done b y current mirror Q3,Q4. 

Q1, Q2 have different emitter areas (AE) with AE(Q1) > AE(Q2) . 

Ratio n i s choosen as integer. 

If collector-currents are equal , the base-emitter-voltages (V BE) of Q1, Q2 are different. 

Δ 

V BE 

= Vt ⋅ ln 

V R 1 = Δ V BE 

( n ) 

= 

I 

1 

⋅ R 

1 

AE( Q1) 

n = 

AE( Q2) 

k 

Vt 

q T = ⋅ 

R 2 

V R 2 = ( I 1 + I 2 ) ⋅ R 2 = 2 ⋅ I 1 ⋅ R 2 = 2 ⋅ ⋅ Δ V 

R 

VREF = VBE 

2 + VR 

2 

= 1, 

20... 

1, 

25V 

Example: 

n=10 

Δ V BE = 60 mV [ 25 C ] 

R2/R1 = 5 

V R 2 = 6 0 0 m V 

VBE2=600 m V 

V R E F = 1,2 V 

Voltage drop at R1 equals delta -V b e and has the s a m e positiv tc (temp.coefficient) as V t. So 

a l s o the voltage VR2 has the s a m e tc, the absolute value of V R 2 i s choosen to a value similar 

to V B E . 

T h i s leads to a compensation of the negative tc o f V B E over full temperature range. The 

resulting temperature error i s of 2nd order and i s i n practice lower than 1%. The best 

temperature compensation will be achieved if the voltage Vref i s adjusted to 1.2 - 1.25 V. The 

absolute value o f this reference voltage i s better than + /- 5% assuming all practical 

manufacturing tolerances 


Ibias 

1 

for optimal 

BE 

temp. 

comp. 

Bandgap 

Reference 

Circuit 

Practical example of a 

circuit realized in a 

SPT (BCD) 

technology 


• 24

Startup- Problem of Bandgap- Reference Circuit 

I1 I2 C1 

Q5 

R3 

I1 I2 

Vref 

Q1 

n : 1 Q2 

R1 

R2 

+Vdd 

Q3 Q4 

R4 

V REF 


R1 

R2 

I2 I1 

V BG 

Current Mirror Q3/Q4 forces I1=I1, 

this defines the operating point. 

But there exists a second stable 

operating point: I1=I2=0 

A startup- circuit is required 

Adjustment of bandgap reference voltage 

Vref 

V r e f 

- 40°C - 25°C 150°C 

Adjusting the Vref by changing the value of the resistor ratio R1/R2 changes not only the 

output voltage but also the temperature behaviour. 

There exists one point with minimal temperature depedence (in pr actice < 1%) 

For bipolar technologies this optimal voltage is around 1,25V 

Adjustement can be done during wafer measurement, using „ zener - zapping“ or laser 

trimming. 


T 

• 25

Accuracy of voltage dividers (diffusion resistors) 

V1 

a) b) 

R 1 

R 2 

V2 

well connection 

V2/V1 


k 

k = 

R2 

R + R ) 

( 1 2 

a) all resistors in one well – not suited for precision resistor divider 

b) each resistor in separate well – better accuracy 

Remark: this problem does not exist for polysilicon resistors 

Diffusion Resistor Voltage Divider - Layout 

R 1 R 2 

pp- 

p resistor 

n- well 

resistor p 

p 

presistor 

n- well 

p 

presistor 

n- well 


p 

V1 

a 

b 

a) 

all resistors in one well: 

R2 sees a higher voltage in 

respect to the n- well -> t e n d s 

to be highohmic compared to 

R1, caused by the backgate 

effect. 

b) 

each transistor 

in separate wells: 

better for accurate 

matching 

• 26

CMOS Compatible Bandgap Reference 

If in a CMOS process no real npn is available, u s e t h e „ substrat- npn“ , which always 

is available in a p- well CMOS technology, as bipolar reference . 

e.g . i n the Smart technology this s u b s t r a t- npn exists. 

The collector is f i x e d t o + Vbat ( = substrat in that technologies), so you cannot u s e 

the npn as amplifier . You h a v e only free access to base and emitter , which is enough 

to use the emitter - scaling for t h e D e l t a- Vbe principle. 

Amplifier has t o b e d o n e in MOS which will cause m o r e offset as a pure bipolar 

solution . 


npn 

S G 

D 

B 

S G 

D 

E 

B 

+Vbat = Substrat 

p + 

n + 

p- 

CMOS p- well process 

e.g . logic p a r t of Smart 

n Substrat 

C 


Bandgap reference with all npn-collectors connected to VDD 

+Vdd = Substrat (for p- well CMOS) 


Vref 

B 

M O S O p a m p 

1) This is a possibility solution to realize a bandgap reference in a CMOS 

technology 

take care of opamp offset 

2) This circuit is robust against leakage currents and other parasitic currents at the 

bipolar collectors. So it can also be used with bipolars in the BCD process to 

improve robustness. 

C 

E 

• 27

M 1 M 2 

1 : m 

I1 I2 I3 

Q2 

R3 

n : 1 

Current - Reference 

based on Delta -Vbe 

Q1 

M 3 

I f M 1 = M 2 -> I1 = I2 

ΔVBE 

Vt ⋅ln( 

n) 

I1 = = 

R R1 


1 

If M1, M2 not equal: M2/M1 = m 

Ratio m acts as multiplication-factor: 

ΔV 

BE Vt ⋅ ln( n ⋅ m ) 

I 1 = = 

R R1 

1 

Temperature behaviour: 

A resistor R3 with positive temp.coefficient (e.g. diffusion resistor) 

would give a temperature compensation of ΔVBE 

Diagnostic and Protection of Smart Power Switches 

o n 

status 

reset 

feedback 

- loop 

Overcurrent 


Overvoltage 

Open Load 

measure 

switch - o f f 

latch 

This is really the „Smart“ part of Smart Power devices 


logic 

• 28

C 

200 

150 

100 

50 

K 

450 

400 

350 

300 

Temperature Sensors 

Leakage current detection 

Bipolar VBE monitoring 

Robustness aginst epi- well parasitics 

Position of temperature sensor in layout 


Temperature Sensor (1) 

Using t h e leakage current as temperature signal 

R 1 

I C B 

V+ 

I1 

V TMP 

Leakage current is very low at junction temperatures < 150°C. For higher temperatures it 

increases exponentially, doubling approx. for each 10K of temper ature increase. Therefore 

the leakage current is a good indicator to detect an overtemperature in the range > 150°C in 

integrated smart power circuits. In a MOS technology the always available parasitic substrat 

npn can be used as bipolar device. The temperature threshold is only in a given range 

adjustable by the values of R1 and I1, the exact temperature is not predictable (in contrast to 

direct Vbe measurement) 


I C B 

V TMP 

150 °C 

T 

T 

• 29

Temperature Sensor Circuit ( 2 ) 

C o m p a r i n g of the bipolar VBE voltage with a stable reference 

R 1 

R 2 

I1 

IC 

Q1 

I2 

M 1 M 2 

M 3 

V TMP 

V TMP 


U B E 

V R E F 

IC=I1+I2 

IC=I1 

Bipolar Bipolar characteristic of of approx. -2mV/K -2mV/K of of Vbe Vbe is is very very reliable 

reliable 

Hysterese 

Temperature Sensor with npn- Collector at VCC 

more robust against parasitics of bipolar collector (epi- well) 

Epi well (C of npn) is often affected by 

parasitics 

( reverse current, EMC, 

high temperature leakage currents ...) 

VCC 


Vref 

Solution: 

T e m p -sensor with with npn-C at at supply line, 

line, 

emitter as as temp-information 

T 

T 

Hysteresis 

• 30

Temperature Sensor w i t h D e l a y 

Example of realised circuit 

temp-sensor comparator current-mirror 

delay logic-o u t 


D 

Positioning of Temperature Sensor in Layout 

B 

Power-DMOS 

A 

C 

E 

Where is the best position? 

A center 

B inside, but not center 

C outside, at long edge 

D outside, at short edge 

E outside, chiptemp. 

Use thermal simulation to define the temp.sensor threshold of the sensor 

to ensure protection in case of short circuit with max. power dis sipation 


• 31


3 0 0 µs 

Thermal Simulation 

Ch 3 Ch 6 

Ch 4 

Treiber Treiber Treiber 

Treiber Treiber Treiber 

Dynamic Thermal FEM Simulation 

1ms 

3ms 

Ch 5 

Heat source 

(junction) 

10ms 

Logik 

Ch 2 

Ch 1 

To decide size 

of power-DMOS 

(if not only 

R-on related) 

and best position 

of temperature 

sensors 

Chip cross section 

(through DMOS) 


• 32

Verifying of the the 

thermal model by 

i n f r a r e d t h e r m o g r a f y 


Seminar 



4 

K / W 

3 

2 

1 

T h e r m o g r a f i e ( 3 0 W , 1 4 7 ° C ) 

F E M ( 4 . 5 W , 1 4 1 ° C ) 

• Diagnostic & Protection Circuits 

– Temperature Sensors 

– Current Measurement 

– Overvoltage Protection 

– Openload Detection 

0 

- 2 - 1 0 1 mm 

2 


• 33

R1 

Current Measurement with Shunt- Resistor 

I LAST 

V 1 

V REF 

+ 

- 

I OVL 

Requires a reference v o l t a g e 

I LAST 

V REF 


R1 

V 1 

I OVL 

Current Measurement with Shunt- Resistor 

Comparator uses Delta -V B E principle 

I LAST 

U R1 

I 1 I 2 

Q1 Q2 n : 1 

n = ratio of emitter areas Q1/Q2 

I OVL 

R1 a s aluminum -resistor results in a good first order temperature compensation of Vt (TK AL = 3,8 10 - 3 ) 


I LAST 

U R1 

U S 

U IOVL 

Calculation of threshold U S : 

U V n I2 

S = t ⋅ln( ⋅ ) 

I1 

z.B. I1 = I2 , n=2 U S = 18 mV bei 25C 

• 34

Current Measurement with Sense- Transistor 

Shunt -resistance in series to sense -cell 

I LAST 

I SENS 

M1 z : 1 

M2 

R1 U R1 

I 1 I 2 

Q1 Q2 n : 1 


I OVL 

U 

R1 

1 R 

I LAST = ⋅ 

z + 

The layout of the powerdevice (DMOS) in general consist of many cells (> 1000). One or few 

cells are used as sense cells, the current ratio between main (M1) and sense DMOS (M2) is 

defined by the ratio z. The shunt resistor R1 must therefore not be dimensioned for the full load 

current and, as additional advantage, the shunt resistor does not generate a voltage drop in 

series to the power DMOS. 

M1 

Current Measurement with Sense- Transistor 

without Shunt -Resistor 

I LAST 

z : 1 

M2 

I REF 

VP 

I OVL 

VN VN 

VP = RdsOn( M1) ⋅ I LAST 

Here the voltage drop at the power-transistor itself is used as current measuring device. This 

allows the measurement of high currents (overload) and very low currents (open load 

detection), depending on the choosen value of the reference current. 


I LAST 

VP 

I OVL 

VP = RdsOn ( M 2) 

⋅ I REF 

RdsOn( M 2 ) = z ⋅ 

RdsOn( M 1) 

1 

• 35

+ Vbat 

D 

M1 M2 

z : 1 

S 

I Load 

S- sense 

OUT 

RLoad Rs 

(x Ampere) ( x m A ) 

I FB 

CFB 

M3 

ON 

A / D 

µ C 

Current Feedback 

With sense-cells a given ratio of 

the load current can be mirrored 

to a pin as current feedback 

signal. To obtain the same drain 

voltage at the sense-DMOS as of 

the power-DMOS the gate 

voltage of an additional Transistor 

M3 in series to the sens DMOS 

M2 is controlled by a regulationloop. 

Current can than be acurate 

measured in application by using 

the A/D port of a µC 

Note: For a vertical technology (Highside 

Switch) the Sens Ratio of DMOS cells is 

very accurate, for updrain DMOS (BCD) the 

ratio of few cells to a large DMOS is not so 

good defined. That, and also offset of 

opamp can limit accuracy to approx. 10% . 


Seminar 



• Diagnostic & Protection 

Circuits 






• 36

Freewheeling diode 

disadvantage: 

switch off delay 

Circuit measures against overvoltages 

caused by switching inductances 

Clamping with 

external voltage 

Power transistor is 

switched on at high 

voltages - limits voltage 

like a power Z-diode 


Overvoltage protection - Switching of inductive loads 

Integrating the Z-diode into the smart power device 

U IN 

I O U T 

U O U T 

U S T 

t o n 

I OpenLoad 

t A Z 

Current Imax at switch-off depends on turn-o n t i m e . 

i f t o n > > t i m e-constant L/R than imax is only defined 

by ohmic resistor R of coil 

I m a x 


U Z 

V S 

T i m e t AZ can be calculated from amount of 

energy which is stored in the inductance. 

E m 

L I 

= 

Set magnetic energy equal to electrical 

energy: 

2 

⋅ max 

2 

⎛ 

I = I ⋅ ⎜ − e 

⎝ 

IN 

∫ 

( ) 

E = I ⋅ U − V ⋅ dt 

el out z s 

⎞ 

⎠ 

Vz 

V 

R 

R+L 

Vs 

t 

− 

τ 

max 1 ⎟ 

τ = L 

S 

I max = 

R 

I OUT 

• 37

Clamping with slew rate controlled soft clipping 

Reference 

Voltage 

Vref 

> 70V 

O F F 

> 85V 


DMOS 


Seminar 



Clamping voltage defined by 

bandgap ref, not with z-diodes 

+ 

+ 

R e f -voltage and comparators have to be supplied via drain to guarantee clamping 

function in case of loosing or missing supply voltage 

• Diagnostic & Protection Circuits 






• 38

Open Load Diagnostic (at OFF) 

To detect open load condition the output voltage is measured at off -state. 

A pull down current (or resistor) is used to pull down the output in case of 

an open load (broken line). This pull down device alway is seen l i k e a 

“leakage” current during off -state. Therefore a switch to cut off this current 

(e.g. in reset-mode) should be foreseen to enable real leakage control of 

power DMOS. 

Open 

Load 

Ipd 

e.g. 100 uA 

V r e f 

3 V 

+ V b a t 

R L 

o p e n , 

broken 

Open load detection level calculation: 

V = V −V 

= R ⋅ I 

RL 

V 

R = 


L 

BAT 

BAT 

−V 

I 

PD 

REF 

REF 

with Vref=3V, Ipd=100µA 

L 

PD 

Vbat = 6V - > R L = 3 0 k O h m 

Vbat =16V - > RL = 13 kOhm 

RL > 30 kOhm will allways be detected als open load 

RL < 13 kOhm will never be detected as open load 

Short to GND Diagnostic (at OFF) 

The open load detection in any way will also detect a short to GND 

(or switch bypass). 

To differ between this two conditions, direction of the current can be used: 

For open load the internal pull down current flows into the pin, 

for short to gnd the current flow is out from the pin. 

Short to GND 

I-p u l l u p 

V r e f 

2 V 

+ V b a t 


R L 

Short to 

G N D 

• 39

Blockdiagram of a Lowside Switch with Diagnostic Functions 


Status 

Smart Two C h a n n e l L o w-S ide Switch (TLE 6215) 

ENA Open Load 

IN1 

ST1 

IN2 

ST2 


Overcurre 

n t 

Open Load 

Detection 

(ON mode) 

Open Load 

Detection 

(OFF mode 

LOGIC 


VS 

Thermal o v e r l o a d 

G N D 

Overload 

Open Load 

Overload 

RPD 

RPD 

INTERFACE SMART-PART POWER-PART 

Low Side Switch TLE 6 2 1 5 : 

Blockdiagram of Diagnostic Functions 

Bandgap - 

Referenc 

e 

V S 

I r e f 2 

1 m A 

O U T 1 

O U T 2 

R ref R L 

1kOhm 

Sens-Cells 

0,2 Ohm 

DMOS 

Pull- d o w n 

Resistor 

20k 


V S 

R 1 

R 2 

I r e f 2 

50 u A 

1 : z 

Temperature 

Sensor 

V S 

Power DMOS 

Sens - DMOS for overcurrent 

Sens - DMOS for open load @ on) 

• 40

CS 

TLE6215: Diagnostic at Status Output 

Diagnostic concept is as follows: 

If status output follows the logic input signal, all is okay. 

If status signal is inverted against logic input, it indicates so me error. 

U IN 

I O U T 

V STATUS 

SCLK 

SI 

SO 

Outputs 

U O U T 

normal Overcurrent Openload Open load at OFF 

Overcurrent 

Threshold 

Open Load 

Voltage Threshold 

Open Load 

Current Threshold 


TLE 6220: Readout Diagnostic Information with Serial Interface (SPI) 

Blockdiagram of 

TLE 6220 

4- fold Low- side Switch 

Control Bits 

Data Bits 

64444 74444 

8 64444 74444 

8 

7 6 5 4 3 2 1 0 

MSB LSB 

7 6 5 4 3 2 1 0 

OLD NEW 

SCLK 

SI 

CS 

SO 

IN1 

IN2 

IN3 

IN4 

GND 

VS 

a s C h . 1 

a s C h . 1 

a s C h . 1 

PRG 

Diagnostic Serial OUT (SO) 

7 6 5 4 3 2 1 0 

C h . 4 C h . 3 Ch.2 Ch.1 

Two bits for each 

channel for detailed 

diagnostic 

HH Normal function 

HL Overload, Shorted Load or Overtemperature 

LH Open Load 

LL Shorted to Ground 


RESET 

8 

Serial Interface 

SPI 

VS 


FAULT 

1 4 

8 

Output Control 

Buffer 

4 

GND 

normal function 

SCB / overload 

open load 

short to ground 

Output Stage 

V B B 

OUT1 

OUT4 

• 41

Seminar 



Switching behaviour of a MOS transistor 

L o w-side driver 

H i g h -side driver 

Charge pumps 

Oscillators 

D r i v e r – Circuits 


I 1 

ein 

a u s 

I 2 

Vdd 

Switching behaviour of a MOS transistor 

Cdg 

Cgs 

Vgs 

Vs 

R L 

Id 

Vds 

Vgs 

Vth 

90% 

Vds 

10% 

A: Cgs(off) defines slope 

B: Cdg acts as Miller-C 

C: Cgs(on) > Cgs(off) 

A 

I d 

A 

t f 

t 

d 

t o n 

B 

ein a u s 

R o n . 

I L 

t d t 

r 

t o f f 


C 

• 42

I G 

Gatecharge plot 

to understand switching behaviour of DMOS 

V GS 

The characteristic of the gate- voltage over time in case of 

driving with constant current is presented as Vgs vs Qgate 

(gatecharge) in data sheets of power MOS transistors. 

This allows ewasy to calculate the required 

charge/discharge currents to obtain a given switching 

time. 

Gatecharge is, in contrast to other parameters, not 

dependent from temperature. 

I D 

from datasheet 

BUZ 342 


H o w to Switch on/off a Gate -C h a r g e /Discharge C u r r e n t 

Vdd 

Igate- on 

I gate- off 

V s 

RL 


DMOS 

a) series switches b) parallel switch to current 

m i r r o r 


Vdd 

Low = OFF 

V s 

I gate- off 

RL 


DMOS 

• 43

Vdd 

Ibias 

M1 

IN 

Simple d r i v e r circuit for l o w- side switch 

Gate charge and discharge with constant current 


Vdd 

Ibias 

M1 

IN 

M3 

2 discharge pathes: 

M2 

M6 

M7 

M10 

M8 M9 

M11 

M4 M5 

Low Side Switch 

Improved discharge circuit for switch off 

M3 

M2 

normal 

discharge 

I gate- on 

I gate- off 

V s 

R L 


DMOS 


f a s t 

M4 M5 

M12 

fast 

discharge 

M11 

V s 

RL 


DMOS 

1) l o w discharge current with M5 f o r s l e w rate control 

2) higher discharge current (M11), controlled b y switch M12 

f o r reduce switch-o f f delay t i m e 

• 44

EMI measurements 

confirm the improvement 

of “soft” switching 

I N 

I D = 2 A 

VDS 

dB 

1 0 0 

90 

80 

70 

60 

50 

40 

30 

20 

10 

Abstrahlungsmessung 

Last 7 Ohm + 2m Kabel 

TLE soft Soft 6240 edge 

GP 

0 

100,E+3 1,E+6 1 0 , E + 6 1 0 0 , E + 6 


I N 

ID = 2A 

VD S 

Frequenz [Hz] 

L o w s i d e driver (real circuit) 

slew-rate control 

currnet limit 

current limit 

slower slope 

4 4 m O h m 

Competitor 

normal 

soft edge 

Specification: ton, toff typ . 5 us, Ron typ . 0.3 Ohm (25C), current l i m i t typ . 4 . 5 A , V c l a m p typ . 50V 

44 mOhm 

5000 Zellen 


zener-clamping 

current 

measurement 

with 

sens-DMOS 

• 45

ON 

bias 

current 

Low Side 

Driver 

zoom in (1) 

switching ON 

(charging) & 

switching OFF 

(discharging) 

if overcurrent, 

then 

charging current 

is decreased 


Low Side 

Driver 

zoom in (2) 

gate 

gate for fast discharge 

overcurrent 

Current Limit 

circuit 

z-diode 

clamping 

D r a i n 

resistor to 

protect circuit 

during highvoltage 

gate 

stress 

Pad to allow 

gatestress 

on wafer - level 

metal resistor 

( a l u m i n u m ) 

for current 

measurement 


• 46

High side d r i v e r 

Power DMOS is always a N -channel device. 

For inserting the DMOS as switch in the 

positive supply line („high side switch“), the 

drain is connected to Vbat (plus). A more 

positiv gate-voltage (higher than Vbat) is 

therefore necessary to drive the DMOS. 

The usual way to g e n e r a t e this voltage is a 

capacitive voltage multiplier called „charge 

p u m p“ 


Principle circuit of a one- step charge pump 

O s c il la to r 

VS VC V C P 

VCP(max) = 2⋅( 

Vs−Vd) 

turn-on time to charge C2: 

Ton≥ 2⋅( 

C2/ 

C1) 

⋅T 

1 

T = f o r faster switching t i m e increase C1 and/or f r e q u e n c y 

f 


C 1 

C 2 

• 47

B 

n + p 

S G 

D 

n+ Substrat 

parasitic substrat- npn 

inside a n- channel MOS 

Oszillator 

Charge pump in CMOS based t e c h n o l o g y 

(no bipolar diodes avalable) 

VBatt 

(substrate) 

n- channel MOS- “ Diodes“ 


V C P 

Example: 2- stage VCP≤ ⋅( 

Vbatt−V 

) 

3 th(MOS) 

Oscillator circuits for charge pump driving 

Ring- oscillator 

RC-oscillator 

Operating-frequency defined by R and C 

Odd number of inverters, usually 5 or 7 

Operating-frequency defined by internal delay (depends on technology) 


R 

C 

• 48


5 V 

0 V 

Charge pump 

3 -step with ring-o s c i l l a t o r 

V S VCP 

advantage: simple 

disadvantage: frequency not defined 

IN 

High voltage level shifter 

V d d + 5 V 

Ibias 

H 

H 

H ... Highvoltage transistor 

V s + 5 0 V 

H 

H 


OUT 

5 0 V 

also for highvoltage transistors 

Vgs cannot withstand > 5..10V 

(depend on gateoxid thickness) 

- > z- diode protection required 

0 V 

Vgs 

Gate 

Source 

D r a i n 

Vds 

• 49

R IS 

3 

1 

5 

I N 

ST 

IS 

Blockdiagram of a Smart Power Highside Switch 

( Profet BTS 640) 

Voltage 

source 

V L o g i c 

Voltage 

sensor 

ESD Logic 

S i g n a l G N D 

Overvoltage 

protection 

Charge pump 

Level shifter 

Rectifier 

2 

G N D 

Current 

limit 

Limit for 

unclamped 

ind. loads 

Temperature 

sensor 


Seminar 



I IS 

Output 

Voltage 

detection 

Gate 

protection 

Current 

Sense 

R O 

+ V b b 

OUT 

G N D 

P R O F E T ® 

4 

6 , 7 

I L 

Load 

L o a d G N D 





Anforderungen an Gehäuse/Montagetechnik - Beispiele 



Seite 100 H.Zitta / Smart Power IC-Entwicklung 

• 50

Montagetechnik -Beispiel Nr.1 

Optimale Realisierung einer Power H-Brücke 

HS: Drain an VBAT = Plus, 

ideal f ür vertikale Smart Technologie 

LS: Source an GND = Minus: 

On -chip Integration mit HS nur in 

Updrain SPT Technologie m öglich 

D r a i n D r a i n 

Source Source 

Nachteil: R -on grösser als bei Vertikaler Smart-Techn. gleicher Chipfläche 


New Technologies chip/package 

Chipflächenoptimale Lösung für H-Brücken 

Lowside- 

MOSFET 

High -Side- 

Smart -FET 

High-Side HS 

Low-Side LS 

TRILITHIC Family 


• 51

R I S 

3 

1 

5 

IN 

S T 

I S 

Montagetechnik -Beispiel Nr.2 

Realisierung eines sehr niederohmigen 

Smart Power Schalters ( < 20 mOhm) 

mit vollen Schutz und Diagnosefunktionen 

V o l t a g e 

source 

V o l t a g e 

sensor 

E S D L o g i c 

I I S 

V L o g i c 

S i g n a l G N D 

O v e r v o l t a g e 

p r o t e c t i o n 

Charge pump 

L e v e l s h i f t e r 

R e c t i f i e r 

2 

GND 

Current 

l i m i t 

L i m i t f o r 

u n c l a m p e d 

i n d . l o a d s 

T e m p e r a t u r e 

sensor 


Chip on Chip 

Power Switch 

Control / Top-Chip 

Output 

V o l t a g e 

d e t e c t i o n 

G a t e 

p r o t e c t i o n 

Multi Chip Packaging 

Example: Chip on Chip 

Costs 

Leistungschalter 

Base-Chip (4-5 Masken) 

Chip on Chip 

S-Smart or SPT 4 

with 

S-FET 

On State Resistance 

Monolithic 

S-Smart 

SPT 4 

Current 

Sense 

R O 

+ V b b 

OUT 

GND 

PROFET ® 

4 

6 , 7 

I L 

Load GND 

Monolithic 

Power Switch 


Load 

• 52

Cost benefit of Chip-on-Chip solutions 

Smart control chip is glued on top of power transistor 

Comparison of two devices with same RDS-On 

Chip on Chip solution 

Monolithic device 

12 mOhm PROFET 


Seminar 



BTS 550 4 mOhm 


• 53

Features: Features 

• Vclp = 400 V 

• Ic, max = 9 ... 15 A 

• Tj,max = 175°C 

• Current limitation 

• Current Feedback 

• Voltage Feedback 

• ESD Protection 

• Soft Shutdown 

• PT- IGBT Process 

• µC compatible Input 

Smart Ignition IGBT 

BTS 2145 

BTS 2140 

IN 

IFL 

SSD 

VS 

Protection , 

Limitation 

Current feedback 


VFL 

1 

SMD 

Top Chip OUT 

IGBT + Smart-Power-Chip = Smart IGBT 

BTS 2145 

Bottom - Chip: 

IGBT 

Top- Chip: 

Smart Control Chip 

Chip- on chip Montagetechnik erlaubt hier die gemeinsame Integration v on 

sonst “ inkompatiblen” Technologien wie IGBT und SPT - Ansteuerung/Diagnose 

als Systemlösung in einem Geh äuse. 


GND 

Base Chip 

7 

12 V 

GND 

• 54


Seminar 



Hochpolige Leistungsgehäuse 

High-Integration of 16 Power Switches for 

new Generation of Engine Management Platform 

SoC - System on Chip 

Highintegration 

• Reduced Board Space 

• Reduced Devices for Assembly 

• Reduced Overall Package Costs 

• Increased Reliability 








Seite 110 H.Zitta / Smart Power IC-Entwicklung 

• 55

Automotive Smart Power System Integration 

micro system 

sensor 

bus interface 

signal preconditioning 

Interface 

bus 

Interface & Signal 

preconditioning 

System A 

uC 

EEPROM 

Supply & 

application specific 

functions 

System B 


activate, diagnosis 

valves 

relay 

lamps 

motors 

... 

Door module 

lamp module 

airbag, .... 


System Integration eines ABS Systems (excl. µP) 

Beinhaltet: 

Sensor - Interface 

CAN Tranceiver 

Spannungsregler 5V 

Spannungsregler 3V 

Ü berwachungslogik 

(Watchdog) 

Leistungsschalter 

weiters: 


µ 

µ 

Leistungschalter 

f ür V e n t i l e 

Lampentreiber 

Leitungstreiber 

Diagnosefunktionen 

Diagnose Schnittstelle 

• 56

12V 

IASG 

curr./volt. 

ISO 

9141 

Crash 

Sensors 

System Integration eines Airbag-Systems 

Zwei integrierter DC/DC Konverter zur Sicherstellung 

der el. Airbag-Zündung auch beim Ausfall der 

Batterieausfall bei einem Unfall 

12v -> 30 V (Speicherung in Elkos ) -> 5 V 

Umfangreiche Selbstü berwachung, Diagnosefunktionen 

Buck 

and 

Boost 

Converter 

Optional 

Outputs 

Diagnostics 

Interface 

Sensor & 

Satellite 

Interface 

Input 

Interface 

Airbag Power ASSP 

5V 

Microcontroller 

(e.g. C164CG-xFM) 

Electronic 

Accelerator 

Serial Control 

Interface Unit 

30V 

CAN 

Transceiver 

Squib 

Diagnosis 

Quad 

Squib 

Drivers 

Additional 

Belt 

Pretentioners 

and 

Airbag 

Belt 


Power System Integration von 18 Endstufen 

Quelle: Bosch Presseinfo/Internet 


• 57

System on Chip 

für das 

Engine- 

Management: 


Seminar 



18 Endstufen 

komplexe 

Diagnose- 

Funktionen 

SPI- Logik 

Der Einsatz integrierter Schaltungen im Automobil bietet breite Einsatzm 

öglichkeiten vom einfachen Smart- Power Schalter bis zu komplexen 

System - L ösungen. 

Der Fokus der Technologieentwicklung liegt hier nicht vorwiegend auf der 

Strukturgr össe, Eigenschaften wie: 

• Robustheit 

• Zuverlässigkeit 

• Niedriger Ron 


• Hoher Temperatur - Bereich 

• Beherschung von Montagetechniken 

s i n d m aßgebend f ür den wirtschaftlichen Erfolg. 

Neben bereits etablierten Anwendungen wie ABS, Airbag, Engine- 

Management werden das zukünftige 42V Bordnetz (?), „ X by wire“ 

Anwendungen(elektrische Lenkung, el. Ventilsteuerung), erweiterte 

Bus- und Kommunikations- Systeme sowie ein allgemeiner Trend zu 

„ Komfort“ den Anteil von Smart- Power Schaltungen im Auto weiter 

erhöhen und interessante Herausforderungen f ür die 

Halbleiterindustrie darstellen. 


• 58

Smart Power IC-Entwicklung für die Automobiltechnik - HTL Wien 10

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