Decoders

EE207: Digital Systems I,
Semester I 2003/2004
CHAPTER 3 -ii: ii:
Combinational Logic Design –
Design Procedure, Encoders/Decoders
(Sections 3.4 – 3.6)

Design Procedure
Code Converters
Design Procedure
Code Converters
Binary Decoders
Overview
Binary Decoders
Expansion
Circuit implementation
Circuit implementation
Binary Encoders
Priority Encoders

Combinational Circuit Design
Design of a combinational circuit is the
development of a circuit from a
description of its function.
Design
Starts with a problem specification and
produces a logic diagram or set of
boolean equations that represent the
circuit.

Design Procedure
1. Determine the required number of inputs
and outputs and assign variables to them.
2. Derive the truth table that defines the
required relationship between inputs and
outputs.
3. Obtain and simplify the Boolean function (K-
maps, algebraic manipulation, CAD tools, …). ).
Consider any design constraints (area, delay,
power, available libraries, etc).
4. Draw the logic diagram.
5. Verify the correctness of the design.

Design Example
Design a combinational circuit with 4
inputs that generates a 1 when the # of
1s equals the # of 0s. Use only 2-input 2 input
NOR gates
…

ore Examples - Code Converters
Code Converters transform/convert
information from one code to another:
BCD-to BCD to-Excess Excess-3 3 Code Converter
Useful in some cases for digital arithmetic
BCD-to BCD to-Seven Seven-Segment Segment Converter
Used to display numeric info on 7 segment
displays

BCD CD-to to-Excess Excess-3 3 Code Converter
Design a circuit that converts a binary-
coded-decimal coded decimal (BCD) codeword to its
corresponding excess-3 excess 3 codeword.
Excess-3 Excess 3 code: Given a decimal digit n, , its
corresponding excess-3 excess 3 codeword (n+3) 2
Example:
n=5 n+3=8 1000 excess-3 excess
n=0 n+3=3 0011 excess-3 excess
We need 4 input variables (A,B,C,D) and 4
output functions W(A,B,C,D), X(A,B,C,D),
Y(A,B,C,D), and Z(A,B,C,D).

BCD CD-to to-Excess Excess-3 3 Converter (cont.)
The truth table relating the input and output variables is shown below
Note that the outputs for inputs 1010 through 1111 are don't cares cares
(n
shown here).

Maps for BCD-to-Excess-3 Code Converter
he K-maps K maps for are constructed using the don't care terms

CD-to CD to-Excess Excess-3 3 Converter (cont.

Another nother Code Converter Example:
CD-to CD to-Seven Seven-Segment Segment Converter
Seven-segment Seven segment display:
7 LEDs (light emitting diodes), each one
controlled by an input
a
1 means “on”, 0 means “off”
Display digit “3”?
f
g
b
Set a, b, c, d, g to 1
Set e, f to 0
e
d
c

CD-to CD to-Seven Seven-Segment Segment Converter
Input is a 4-bit 4 bit BCD code 4 inputs (w,
x, y, z).
Output is a 7-bit 7 bit code (a,b,c,d,e,f,g) that
allows for the decimal equivalent to be
displayed.
a
Example:
Input: 0000 BCD
Output: 1111110
(a=b=c=d=e=f=1, g=0)
f g
e
d
c
b

BCD
BCD-to
to-Seven
Seven-Segment (cont.)
Segment (cont.)
Truth Table
Truth Table
11100X0
11100X0
0111
0111
7
X011111
X011111
0110
0110
6
1011011
1011011
0101
0101
5
0110011
0110011
0100
0100
4
1111001
1111001
0011
0011
3
1101101
1101101
0010
0010
2
0110000
0110000
0001
0001
1
1111110
1111110
0000
0000
0
abcdefg
abcdefg
wxyz
wxyz
Digit
Digit abcdefg
abcdefg
wxyz
wxyz
Digit
Digit
XXXXXXX
XXXXXXX
1111
1111
XXXXXXX
XXXXXXX
1110
1110
XXXXXXX
XXXXXXX
1101
1101
XXXXXXX
XXXXXXX
1100
1100
XXXXXXX
XXXXXXX
1011
1011
XXXXXXX
XXXXXXX
1010
1010
111X011
111X011
1001
1001
9
1111111
1111111
1000
1000
8
??

Decoders
A combinational circuit that converts
binary information from n coded inputs
to a maximum 2 n decoded outputs
n-to to- 2n decoder
n-to to-m decoder, m = 2n Examples: BCD-to BCD to-7-segment segment decoder,
where n=4 and m=7

coders (cont.)

o-4 Decoder

o-4 Active Low Decoder

address
3-to to-8 8 Decoder
data

3-to to-8 8 Decoder (cont.)
Three inputs, A 0, , A 1, , A 2, , are decoded into
eight outputs, D 0 through D 7
Each output D i represents one of the
minterms of the 3 input variables.
Di = 1 when the binary number A 2A1A0 = i
Shorthand: D i = m i
The output variables are
The output variables are mutually exclusive; exclusive;
exactly one output has the value 1 at any time,
and the other seven are 0.

Implementing Boolean functions
using decoders
Any combinational circuit can be constructed
using decoders and OR gates! Why?
Here is an example:
Implement a full adder circuit with a decoder
and two OR gates.
Recall full adder equations, and let X, Y, and Z
be the inputs:
S(X,Y,Z) = X+Y+Z = Sm(1,2,4,7) m(1,2,4,7)
C (X,Y,Z) = Sm(3, m(3, 5, 6, 7).
Since there are 3 inputs and a total of 8
minterms, we need a 3-to 3 to-8 8 decoder.

Implementing a Binary Adder
Using a Decoder
S(X,Y,Z) = Sm(1,2,4,7)
C(X,Y,Z) = Sm(3,5,6,7)

Decoder Expansions
Larger decoders can be constructed using
a number of smaller ones.
-> HIERARCHICAL design!
Example:
A 6-to-64 decoder can be designed using
four 4-to-16 and one 2-to-4 decoders.
How? (Hint: Use the 2-to-4 decoder to
generate the enable signals to the four 4to-16
decoders).

-to to-8 8 decoder using two 2-to 2 to-4 4 decoders

4-input input tree decoder

Encoders
An encoder is a digital circuit that
performs the inverse operation of a
decoder. An encoder has 2 n input lines
and n output lines.
The output lines generate the binary
equivalent of the input line whose value
is 1.

Encoders (cont.)

Encoder Example
Example: 8-to 8 to-3 3 binary encoder (octal-to (octal to-binary) binary)
A 0 = D 1 + D 3 + D 5 + D 7
A 1 = D 2 + D 3 + D 6 + D 7
A 2 = D 4 + D 5 + D 6 + D 7

Encoder Example (cont.)

Simple Encoder Design Issues
There are two ambiguities associated with
the design of a simple encoder:
1. Only one input can be active at any given time. If
two inputs are active simultaneously, the output
produces an undefined combination (for example,
if D 3 and D 6 are 1 simultaneously, the output of
the encoder will be 111.
2. An output with all 0's can be generated when all
the inputs are 0's,or when D 0 is equal to 1.

Priority Encoders
Solves the ambiguities mentioned above.
Multiple asserted inputs are allowed;
one has priority over all others.
Separate indication of no asserted
inputs.

Example: 4-to 4 to-2 2 Priority Encoder
Truth Table

-to to-2 2 Priority Encoder (cont.)
The operation of the priority encoder is
such that:
If two or more inputs are equal to 1 at
the same time, the input in the highest-
numbered position will take precedence.
A valid output indicator, indicator,
designated by
V, is set to 1 only when one or more
inputs are equal to 1. V = D 3 + D 2 + D 1 +
D0 by inspection.

Example: 4-to 4 to-2 2 Priority Encoder
K-Maps Maps

Example: 4-to 4 to-2 2 Priority Encoder
Logic Diagram

8-to to-3 3 Priority Encoder

Matrix of switches = Keypad
C0 C1 C2 C3
1 2 3 F
4 5 6 E
7 8 9 D
0 A B C
R0
R1
R2
R3

Keypad Decoder IC - Encoder
1 2 3 F
4 5 6 E
7 8 9 D
0 A B C
COL.
4-bit
ROW
4-bit
4-bit
Binary
(encoded

Priority Interrupt Encoder
Interrupting
Devices
Device A
Device B
Device C
Device D
Schematic
Interrupt
Encoder
Req(1:0)
IntRq
Microprocessor

Priority Encoding - Interrupt
Interrupting Device
A B C D
0
0
0
0
0
0
0
0
0
1
0
0
1
1
0
Requests
0
1
0
1
0
Req (1:0)
0 0
0 0
0 1
0 1
1 0
IntRq
0
Exercise: Complete this table?
1
1
1
1