Simultaneous Switching Output (SSO) Analysis Using Xilinx Virtex-4 ...

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VCCO_9 and IO’s of Interest IO’s VCCO_9 NOTE: The entire package structure is simulated to include all coupling.
SIwave Simulation Run Time � ALL relevant couple structures are taken into account � Fast interpolating sweep � Total memory ~ 800 MB � Total Simulation Time less than 2 hours!
Page 1 and 2: Simultaneous Switching Output (SSO)
Page 3 and 4: Xilinx Virtex-4® FPGAs : Laborator
Page 5 and 6: SSO (Simultaneous Switching Output)
Page 7 and 8: � Via field under BGA Inductive C
Page 9 and 10: Mutual Inductance Coupling Regions
Page 11 and 12: Mutual Inductance Coupling Regions
Page 13 and 14: Ref: BGA Crosstalk by Howard Johnso
Page 15 and 16: Xilinx Virtex-4® FPGA and ML481 Te
Page 17 and 18: Xilinx FPGA: Virtex-4 LX60 FF1148 P
Page 19 and 20: � Create materials, or � Use Ma
Page 21 and 22: SIwave: Automated Grouped Nodes �
Page 23: Package Ports: Grouped References D
Page 27 and 28: Crosstalk Analysis Setup in Nexxim
Page 29 and 30: Crosstalk: Aggressor Proximity Aggr
Page 31 and 32: SIwave Ports at Ball Pads
Page 33 and 34: Terminations for Switched IO’s
Page 35 and 36: SSO Simulation and Results: Measure
Page 37 and 38: Simulation Mirrors Measurement
Page 39 and 40: SSO Measured versus Simulated Measu
Page 41 and 42: High Performance Design Solution Cr
Page 43 and 44: � Measure plane impedances at dif
Page 45 and 46: Frequency Sweeps �Add voltage sou
Page 47: Conclusions � System level valida

Simultaneous Switching Output (SSO) Analysis Using Xilinx Virtex-4 ...

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