Simultaneous Switching Output (SSO) Analysis Using Xilinx Virtex-4 ...

Simultaneous Switching Output (SSO)
Analysis Using Xilinx Virtex-4® FPGAs
Xilinx Corporation
Ansoft Corporation

Overview
� Goal: Create a repeatable, accurate and practical
methodology for SSO analysis
� SSO and crosstalk discussion
� Xilinx package setup and crosstalk results
� Xilinx test board setup
� SSO measurement vs. simulation results

Xilinx Virtex-4® FPGAs :
Laboratory measurements
performed by Xilinx and
Dr. Howard Johnson, Sigcon
www.sigcon.com
www.xilinx.com

SSO Description
� SSO is the noise due to several I/O pins switching at the same time
� Induced voltage due to changing current in lead pins
� Simultaneous switching noise can be attributed to
� Poor signal to ground ratio
� Return path discontinuity
� The following factors can help contain SSO
� Avoid return path discontinuities
� Minimize total inductance of return path and keep it low
� On-die decoupling capacitor strategy to cancel inductive noise

SSO (Simultaneous Switching Output)
Ref: BGA Crosstalk by Howard Johnson, March 1, 2005
�Setup
�“Schematic View” or real
representation
�BGA between PCB power
and ground planes
�At time zero switches C
and A drive LOW -> huge
I/O current transient
�Victim D will pick voltage
glitch Vglitch

� Crosstalk is the coupling of energy from one line to another:
� Mutual capacitance (electric field)
� Mutual inductance (magnetic field)
� BOTH add to NEXT (Near End crosstalk) and FEXT (Far End crosstalk)
� The mutual inductance will induce current on the victim line
opposite of the driving current (Lentz’s law)
Ref: Intel Developer Forum, by Richard Mellitz
Crosstalk: General Overview

� Via field under BGA
Inductive Crosstalk
� Primary coupling mode is inductive
� Magnitude of inductive crosstalk based on spatial
arrangement and proximity of power and ground pins
� Current loops of aggressors and victim couple
Ref: BGA Crosstalk by Howard Johnson, March 1, 2005

1 mm
Ball Pitch
o o o o o o o o o o o o o o o o o
Ref: BGA Crosstalk by Howard Johnson, March 1, 2005
Die and Package Scale
FPGA Die
775um
Bump
75um
Pkg (10L)
1068um
Ball
500um height
700 um width
PCB
(22Layer)
3125um

Mutual Inductance Coupling Regions
175 um
Bump Pitch
1 mm
Ball Pitch
o o o o o o o o o o o o o o o o o
Ref: BGA Crosstalk by Howard Johnson, March 1, 2005
Surface Vertical Region, through bumps and metal layers
(very short distance: ~ 85 um, very small mutual inductance)
Ground Plane
} Signals
Ground Plane

Mutual Inductance Coupling Regions
175 um
Bump Pitch
1 mm
Ball Pitch
o o o o o o o o o o o o o o o o o
Ref: BGA Crosstalk by Howard Johnson, March 1, 2005
Surface Horizontal Region, signal traces run close to ground plane.
Can be fairly long: ~ 14000 um. Source of some mutual inductance
from the neighboring traces, contribution from other traces falls off rapidly
Ground Plane
} Signals
Ground Plane
Transmission Line Construction Via to Die Bump

Mutual Inductance Coupling Regions
175 um
Bump Pitch
1 mm
Ball Pitch
o o o o o o o o o o o o o o o o o
Ref: BGA Crosstalk by Howard Johnson, March 1, 2005
Package Via Crosstalk Region. This is a region of
some mutual inductance coupling. The total height
in this area is approximately 1068 um.
Ground Plane
} Signals
Ground Plane

Mutual Inductance Coupling Regions
175 um
Bump Pitch
1 mm
Ball Pitch
o o o o o o o o o o o o o o o o o
Ref: BGA Crosstalk by Howard Johnson, March 1, 2005
PCB Via Crosstalk Region, includes package balls, printed
circuit vias. This is the primary problem area. This is a region
of significant mutual inductance coupling (or via crosstalk).
The total height in this area is approximately 3635 um for a
signal going all the way through a 22 layer PCB.
Ground Plane
} Signals
Ground Plane

Ref: BGA Crosstalk by Howard Johnson, March 1, 2005
Package Pinout
O15 Load Load GND Load Load SPY SPY O15 Load Load Load GND Load Load O25 Load Load GND clko clko Load Load O25 GND
GND Load Load GND Load Load Load O15 Load Load Load GND Load O25 Load Load Load GND Load Load Load Load O25 Load Load Load GND
GND Load Load Load O15 Load Load Load Load GND Load Load Load Load O25 Load Load Load GND Load Load Load O25 Load Load Load GND Load clko clko
Load Load O15 Load Load Load GND Load Load Load O15 Load Load Load GND Load Load O25 SPY Load GND Load Load Load Load O25
Load Load Load GND Load Load O15 Load Load Load GND Load Load Load Load O25 Load GND SPY Load Load Load O25 Load Load Load Load
Load GND Load Load Load O15 Load AUX Load Load GND Load Load Load O25 clki AUX Load Load GND Load Load Load Load O25 Load Load Load GND Load Load
Load Load Load O15 Load Load Load GND Load Load Load Load O25 Load Load Load clki GND INT INT O25 Load AUX Load GND Load Load Load Load O25
O15 Load Load Load GND Load Load Load Load O15 Load Load Load SPY GND Load Load Load O25 Load AUX Load Load GND Load Load Load VDO Load Load Load
GND Load Load Load Load O15 AUX INT GND Load SPY INT O25 Load Load INT GND Load Load INT Load O25 clko Load Load GND clko
Load Load Load O15 Load INT Load Load GND INT GND INT Load O25 Load Load Load GND INT GND INT Load O25 Load Load Load Load GDO Load Load SPY
Load O15 Load Load Load GND Load INT GND INT GND Load Load GND Load Load INT GND INT GND AUX Load Load GND Load Load Load Load O25 SPY
Load Load GND Load Load SPY Load O15 Load AUX GND INT GND INT clki Load Load O25 Load INT GND INT GND Load Load Load O25 Load Load Load Load GND
GND Load O15 SPY AUX Load Load GND Load INT clki O25 Load Load Load Load GND Load Load INT Load O25 Load INT Load Load GND
Load Load GND Load Load Load O15 INT GND INT GND INT Load O25 Load AUX Load Load GND
GND Load O15 Load INT GND INT GND INT GND AUX GND O25 Load Load Load Load GND
GND AUX Load Load GND INT GND INT GND O25 GND INT GND INT GND GND
GND O25 GND AUX GND VDI GDI INT GND
GND INT GND INT GND VDA GND O25 GND
GND GND INT GND INT GND O25 GND INT GND INT GND Load Load AUX GND
GND Load Load Load O33 Load AUX GND INT GND INT GND INT Load O25 GND
GND Load AUX Load O33 Load Load INT GND INT GND INT O25 Load Load Load Load GND Load Load
GND Load Load INT Load O33 Load INT Load GND Load Load Load clki O25 GND INT Load Load GND Load Load AUX Load O25 GND
GND Load Load Load O33 Load Load Load GND INT GND INT Load O25 Load INT clki INT GND INT GND AUX O25 Load Load Load Load GND Load Load Load
SPY Load O33 Load Load Load GND Load Load AUX GND INT GND INT Load Load GND Load Load GND INT GND INT Load GND Load Load Load Load O25
SPY Load Load Load GND Load Load Load Load O33 Load INT GND INT GND Load Load Load O25 Load INT GND INT GND Load INT Load O25 Load clko clko
Load GND Load Load Load O33 INT Load GND INT Load Load SPY O25 Load INT Load Load GND INT Load AUX O25 Load Load GND Load
Load Load O33 Load Load GND Load Load AUX Load O25 Load SPY Load Load GND SPY Load Load Load O25 Load Load Load Load GND Load Load Load Load O25
O33 Load Load Load GND Load AUX O33 Load INT Load INT GND clki Load Load SPY O25 Load Load GND Load Load Load Load O25 Load Load Load
Load Load GND Load Load Load Load O33 Load Load Load GND Load Load AUX clki O25 Load Load Load GND Load Load AUX Load O25 Load Load Load GND
Load Load Load O33 Load Load Load GND Load Load Load O25 Load Load Load GND Load Load Load O25 Load Load GND Load Load Load
Load O33 Load Load Load GND Load Load Load Load O33 Load Load Load Load GND Load Load Load Load O25 Load Load Load Load GND Load Load Load O25 Load Load
Load Load Load GND Load Load O33 Load Load Load GND Load Load Load O25 Load Load Load Load GND Load Load Load Load O25 Load Load Load GND
GND Load Load Load O33 Load Load Load Load GND Load Load O25 GND GND GND Load Load Load Load O25 Load Load Load Load GND Load GND
GND O33 Load Load Load GND Load Load Load O33 Load Load GND Load clko clko O25 SPY SPY Load Load GND Load Load Load O25
The LX60 FF1148 package is tessellated with a
regular array of power and ground pins, called a
“Sparse Chevron” pattern
8 signals : 1 power : 1 ground = min loop area
Load GND Load Load
Load Load Load VCCo
VCCo Load Load Load
Load Load GND Load
Unit Tile

The Xilinx “spiral test” exercises 100 nearestneighbor
aggressors in succession, working
around and around location A10 to increasingly
distant locations
Ref: BGA Crosstalk by Howard Johnson, March 1, 2005
SSN: Function of Proximity

Xilinx Virtex-4® FPGA and
ML481 Test Board: Setup and
EM Simulation in SIwave
Automated Setup and Simulation

� 8-layer package on 24
layer test board
� Test points are at SMA
connectors (Spyholes)
Xilinx System Overview

Xilinx FPGA: Virtex-4 LX60 FF1148 Package
� 8-layer flip-chip BGA package
� Single Core
� 34 x 34 mm
� 1148 Balls
� 49 port simulation
� 40 IO
� 5 Spyhole IO
� 2 VCCO_9
� 2 Decaps

� AnsoftLinks
Xilinx Virtex-4® FPGA –
Automation Step 1
� It is a translator/editor/link from a 3 rd party layout tool to Ansoft environment
� Compatible with Cadence (APD, Allegro), Mentor (Boardstation, PowerPCB, Expedition),
Zuken CR5000, and Synopsys Encore
Cadence Advanced
Package Designer (APD)
Access Ansoft Tools
directly from APD!

� Create materials, or
� Use Material Library
SIwave: Layer Stackup
� Frequency Dependent
� Enter Information
� Layer Thickness
� Materials
NOTE: Sometimes
proper stackup data is
not in the layout tool

SIwave: Solderballs and Solderbumps
Automatic Solderball/Solderbump
Generation

SIwave: Automated Grouped Nodes
� Automated Pin Grouping: pins shorted for easy analysis
� Parts, Pin and Net
names preserved
� User can define
region for grouping

SIwave: Automated Port Creation
� Assign ports by Pin names or Pin Groups
� Reference pins
can be assigned
by distance
� All Parts have
imported pin
names

Package Ports: Grouped References
Die Side Ports Ball Side Ports

VCCO_9 and IO’s of Interest
IO’s
VCCO_9
NOTE: The entire
package structure is
simulated to include
all coupling.

SIwave Simulation
Run Time
� ALL relevant couple structures are taken into account
� Fast interpolating sweep
� Total memory ~ 800 MB
� Total Simulation Time less than 2 hours!

Designer with Nexxim
� Circuit is automatically created from SIwave results
� Each port becomes a sub-circuit terminal
� Xilinx IBIS driver models are used
as stimulus
� All lines properly terminated
� Aggressors sequentially added,
victim left quiet

Crosstalk Analysis Setup in Nexxim
Xilinx Virtex 4 IBIS driver models ver 3.2
LVCMOS 2.5V, 24 mA Fast
Package
Decaps
Die Side Ball Side
Power
Supply

Crosstalk Results
� Crosstalk analysis results vs. number of aggressors
� Increase in number of aggressors will increase crosstalk
� Inductive crosstalk is dominating factor

Crosstalk: Aggressor Proximity
Aggressors progressively
further from victim trace
Crosstalk falls off quickly as you move the
aggressor further and further from the victim

Xilinx ML481 Test Board
� Virtex-4 FPGA half of test board
� Board components included
� 24 layer, FR4 Board
� 7.5 in x 20 in
� 28 Ports
� 23 IO ports
� 3 spyhole ports
� 1 VCCO_9 port
� 1 VRM port

SIwave Ports at Ball Pads

VDO Spyhole Net
Board IO’s of Interest
L34 Spyhole Net
L34 Spyhole SMA
VDO Spyhole SMA
Terminated IO’s

Terminations for Switched IO’s

Board Simulation Profile
� ALL relevant couple structures are considered
� Fast interpolating sweep
� Total memory ~ 1 GB
� Total Simulation Time less than 2.5 hours!

SSO Simulation and Results:
Measurement vs. Simulation

SSO Analysis Setup in Nexxim
Xilinx Virtex-4 IBIS drivers ver 3.2
LVCMOS 2.5V, 24 mA Fast
Spyhole IO’s
held low at die
Package
Board

Simulation Mirrors Measurement

Ref: BGA Crosstalk by Howard Johnson, March 1, 2005
Measurement Setup
�Setup
�Worst case scenario
�Victim is kept at “high”
or “low”
�Many I/O’s driven at
the same time
�Inductive crosstalk
received by I/O’s

SSO Measured versus Simulated
Measured SIwave + Nexxim
� 125 MHz Clock, 400 ps edge
� SSO Measured at L34 Spyhole

SSO Measured versus Simulated
Measured SIwave + Nexxim
� 125 MHz Clock, 400 ps edge
� SSO Measured at VDO Spyhole

High Performance Design Solution
Critical Elements needed to Converge
• Accuracy, Capacity and Speed
• Time and Frequency Domain
• Robust Design Automation

SIwave’s Additional Capabilities
� Impedance Profile
� Measure Z11, Z21 etc. for different locations
� Decoupling Analysis
� Change component values/placement and measure Z change
� Resonant Mode Simulation
� Find Hotspots on your board
� Frequency Sweep
� Measure VRM effectiveness across board
� EMI/EMC Analysis
� SIwave dynamically links to HFSS as radiation source

� Measure plane impedances at
different locations on a PCB or
Package
� Simulation and Lab
measurements for below PCB
shown on right
Impedance Profile
1.00E+04
1.00E+03
1.00E+02
1.00E+01
1.00E+00
1.00E+05 1.00E+06 1.00E+07 1.00E+08 1.00E+09 1.00E+10
1.00E-01
1.00E-02
Simulated
Measured
SIwave 2.0 2003.11.10|Z22| Measured 3p3 |Z22|

� Resonant modes
highlight potential problem
areas of a PCB or Package
� Red and blue areas indicate
high impedances at a particular
frequency
Resonant Modes
Resonant Modes

Frequency Sweeps
�Add voltage sources to a PCB or
Package to simulate the frequency
dependent voltage distribution

EMI/EMC Analysis
� SIwave solution can be used as a radiation source for HFSS
� Project is dynamically linked
Board Solution in
SIwave
Board as Source inside
enclosure in HFSS

Conclusions
� System level validation with EM and Circuit is successful
� Good correlation shown: Measurement vs. Simulation
� Negative crosstalk spike representing inductive coupling
� IBIS Driver results correlate to measured SSO results
� SIwave/Nexxim can easily and accurately perform SSO and
crosstalk analysis
� Future work
� Incorporate Nexxim encrypted driver models
� Simulate merged package and board