Maintaining Cache Coherence with AMD Opterons using FPGAs

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Caching Engine (CPU) Core Automatic SrcTag, Node Information Insertion into Requests Handles 32 Requests in-flight (Max for HyperTransport) Handles Out – of – Order Responses for Requests Optional 1K Internal Buffers on Tx and Rx Interfaces Caching Engine 14 Maintaining Cache Coherency with AMD Opteron Processors using FPGA’s February 11, 2008
Coherent Memory (MCT) Core Core capable of having Cache Coherent Memory Developed by AMD Dresden Design Center and University of Heidelberg 8K Memory - Supports 128 Cache Lines All incoming Cache Block Requests are Routed to Memory Controller FPGA Coherent Memory (MCT) can also be cached by Caching Engine (CPU) Core Coherent Memory 15 Maintaining Cache Coherency with AMD Opteron Processors using FPGA’s February 11, 2008
Page 1 and 2: Maintaining Cache Coherency with AM
Page 3 and 4: Introduction 3 Maintaining Cache Co
Page 5 and 6: Our Approach Coherent HyperTranspor
Page 7 and 8: FPGA Internals HT 7 Maintaining Cac
Page 9 and 10: Coherent HyperTransport Core 9 Main
Page 11 and 12: Application Interface 11 Maintainin
Page 13: Caching Engine (CPU) Core 13 Mainta
Page 17 and 18: Configuration Space and X-BAR Confi
Page 19 and 20: FPGA Cache Coherent Node Platform
Page 21 and 22: Platform BIOS Made changes to AGES
Page 23 and 24: Results 23 Maintaining Cache Cohere
Page 25 and 26: Future Enhancements & Conclusion 25
Page 27 and 28: Conclusion Developed a Cache Coher
Page 29 and 30: Questions ? 29 Maintaining Cache Co

Maintaining Cache Coherence with AMD Opterons using FPGAs

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