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Maintaining Cache Coherence with AMD Opterons using FPGAs

Maintaining Cache Coherence with AMD Opterons using FPGAs

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Configuration Space and X-BAR<br />

Configuration Space<br />

Similar to <strong>AMD</strong> Family 10 Architecture Configuration<br />

Space<br />

Supports Fn0, Fn1, Fn3 and Fn4 Registers<br />

Added support for HyperTransport 3.0<br />

X-BAR<br />

Developed by University Of Heidelberg<br />

Routes packets between Units (Caching Engine<br />

(CPU), Coherent Memory (MCT) Core) and Coherent<br />

HT Core<br />

Uses Routing Table Registers from Configuration to<br />

Route Packets to Units<br />

17 <strong>Maintaining</strong> <strong>Cache</strong> Coherency <strong>with</strong> <strong>AMD</strong> Opteron Processors <strong>using</strong> FPGA’s<br />

February 11, 2008

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